CN102495352B - Multifunctional test circuit of integrated circuit stress degradation and test method thereof - Google Patents

Abstract

The invention belongs to the technical field of reliability testing of integrated circuits, and in particular relates to a multifunctional testing circuit and testing method for integrated circuit stress degradation. The core part of the test circuit is based on the ring oscillator, adding several auxiliary transistors, switching transistors and control terminals. By applying the circuit and method of the present invention, the stress of negative bias temperature instability, positive bias temperature instability, hot hole injection or hot electron injection can be applied to pMOSFETs or nMOSFETs in the ring oscillator inverter respectively, or Make the ring oscillator in the state of normal oscillation and stress oscillation, and also make the pMOSFETs or nMOSFETs of the inverter in the ring oscillator in the measurement state of charge pumping. The degradation of MOSFETs in ring inverters can be characterized both by the change of the ring oscillation frequency after stress and by the change of the CP current (Icpp or Icpn) of pMOSFETs or nMOSFETs in the ring oscillator.

Description

A multifunctional test circuit and test method for integrated circuit stress degradation

technical field

The invention belongs to the technical field of reliability testing of integrated circuits, and in particular relates to a testing circuit and a testing method for stress degradation of integrated circuits.

Background technique

Bias temperature instability (BTI) and hot carrier injection (HCI) are two fundamental issues affecting the reliability of complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs). For nanoscale CMOSFETs composed of SiO2 or SiON gate dielectrics, the negative bias temperature instability (NBTI) of pMOSFETs is the main reason affecting the device lifetime. However, for CMOSFETs constructed of high-k gate dielectrics, both the positive bias temperature instability (PBTI) of nMOSFETs and the HCI of p and nMOSFETs have a significant impact on device reliability.

BTI and HCI degradation result in reduced drive current for MOSFETs, or increased device delay. At the level of CMOS circuits, the aforementioned degradation can be characterized by the frequency change of a ring oscillator (ring oscillator or RO) after stress. One of the simplest measurement circuits is a single RO as the core, through the voltage change of the control terminal (OE) and the power supply terminal, the RO is in the state of static stress, dynamic stress or normal oscillation [V. Reddy et al., Impact of NBTI on Digital Circuit Reliability, IRPS, 2002, p.248]. Although the circuit composed of a single RO has a simple structure, the measurement accuracy of the frequency change is not high. An improved method to improve the measurement accuracy is to use two ROs in the circuit, one of which is used as a reference, without stress, and the other RO is stressed, and the frequency difference (Δf) of the two ROs is measured by a phase comparator, so as to obtain the post-stress Degradation characteristics of RO [T. H. Kim, R. Persaud, and C. H. Kim, Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits, IEEE JSSC vol.43, p.874, 2008 ].

In the measurement method described above, it is possible to combine the dynamic stress degradation (both BTI and HCI) and static stress degradation (BTI only) measurements to distinguish the degradation contributions of BTI and HCI for CMOSFETs in RO, but not for CMOSFETs The NBTI of pMOSFETs and the PBTI degradation of nMOSFETs cannot distinguish the HCI degradation of pMOSFETs and nMOSFETs [J. Keane et al., On-chip reliability monitors for measuring circuit degradation, Microelectronics Reliability, vol. 50, p.1039, 2010]. Since the PBTI degradation of nMOSFETs and the NBTI degradation of pMOSFETs have different mechanisms, they will have different contributions to the degradation or lifetime model of the circuit. Therefore, in the degradation measurement of the circuit, distinguishing the PBTI degradation of nMOSFETs and the NBTI degradation of pMOSFETs is of great significance for predicting integrated circuits. working life is required. Similarly, it is also necessary to apply HCI stress independently to pMOSFETs and nMOSFETs in the circuit and measure HCI degradation after stress.

The physical reasons for the BTI and HCI degradation of MOSFETs are the generation of interface defects (interface states) between the channel/dielectric and the generation of defects or charges inside the dielectric under stress. Since the interface state, dielectric defect and injected charge (oxide layer charge) generated by stress have different effects on the electrical characteristics of the device, the development of a measurement method that can distinguish the interface state, dielectric defect and injected charge generated under stress is very important for the establishment of MOS devices. And the degradation model of the circuit, it is of application value to characterize the life of the device and the circuit.

The traditional method for measuring the interface state density of MOSFET is the method of charge pumping (CP). This is an external measurement method. The excitation signal is provided by an external pulse generator, and is connected to the lead-out pad (Pad) of the MOSFET under test through a cable and a probe. This method encounters great difficulties when it is used to measure MOSFETs at the nanometer scale. Because the device area (W×L) is too small, the CP current Icp is too small to measure at the commonly used excitation pulse frequency (￡MHz). If the excitation pulse frequency is increased, the Icp of the MOSFET will be covered by the parasitic signal due to the parasitic effect of the measurement system such as cables and probes. In order to solve the CP measurement of nanoscale MOSFETs, an on-chip CP measurement method was proposed internationally [R. Fernandez et al., AC NBTI studied in the 1Hz-2GHz range on dedicated on-chip CMOS circuits, IEDM 2006, p.1039], That is, the device under test and the circuit that generates the excitation pulse are integrated together, so that the excitation frequency of the CP can reach 2GHz. However, the device under test in the above measurement method is still discrete (single device), that is, the device under test does not constitute any form of circuit. The stress degradation of the device can only be reflected by static characteristics such as IdVg and Icp, and cannot be reflected by the dynamic characteristics of the device such as delay, so it cannot be directly related to the application of the circuit.

Contents of the invention

The purpose of the present invention is to provide a multifunctional testing circuit and testing method for integrated circuit stress degradation. Utilize test circuit and test method of the present invention, can respectively impose NBTI, PBTI, HCI and dynamic stress to key CMOSFETs in test circuit, then utilize the frequency of ring oscillation circuit or the change of CP current Icp to measure key CMOSFETs under various stresses degradation characteristics.

The multifunctional test circuit for integrated circuit stress degradation provided by the present invention, its core part (core circuit) is based on a ring oscillator (RO_CP), and a group of auxiliary pMOSFET and nMOSFET, wherein the sources of the auxiliary pMOSFET and nMOSFET are respectively connected to the high potential Vdd1 and low potential Vss of RO_CP. The drains of each group of pMOSFETs and nMOSFETs are connected together, and are respectively connected to the output of the previous-stage inverter and the input of the subsequent-stage inverter through a switching transistor S1 and another switching transistor S2. The gates of all auxiliary pMOSFETs are connected together and connected to the first control terminal Vp; the gates of all auxiliary nMOSFETs are connected together and connected to the second control terminal Vn. Gates of all switch transistors S1 are connected together and connected to the third control terminal VS1; gates of all switch transistors S2 are connected together and connected to the fourth control terminal VS2. The substrates of pMOSFETs in all inverters of RO_CP are connected together and connected to an external connection terminal Icpp; the substrates of nMOSFETs in all inverters of RO_CP are connected together and connected to another external connection terminal Icpn. The switching transistor can consist of a single nMOSFET (switching transistor) or a complementary switching circuit consisting of two CMOSFETs. All switching transistors are I/O devices with thicker gate dielectrics, and their operating voltage is higher than that of the core circuit to avoid threshold loss during high-level transmission. the

The output of the core circuit is connected to the input of the first frequency divider, the output of the first frequency divider is connected to the input of the first buffer, and the output of the first buffer is connected to the first external measurement terminal OUT1 of the test circuit. The high potential terminals of the first frequency divider and the first buffer are connected to another high power supply terminal Vdd2 of the circuit, and are isolated from the high power supply terminal Vdd1 of the core circuit. If the normal oscillation frequency of the core circuit is f, and the dynamic range of the measuring instrument (such as an oscilloscope or a spectrum analyzer) is fd, then the frequency division factor of the frequency divider is N>f/fd.

In addition to the core circuit, the test circuit also includes a reference circuit RO_ref with the same structure as the core circuit. The output of the reference circuit is connected to the input of the second frequency divider, the output of the second frequency divider is connected to the input of the second buffer, and the output of the second buffer is connected to the second external measurement terminal OUT2 of the test circuit. The high potentials of the second frequency divider and the second buffer are connected together with the high potentials of the first frequency divider and the first buffer, and are connected to another high power supply terminal Vdd2 of the test circuit. If the normal oscillation frequency of the reference circuit is fref, and the dynamic range of the measuring instrument (such as an oscilloscope or spectrum analyzer) is fd, then the frequency division factor of the frequency divider is N>fref/fd.

The test circuit also includes a phase comparator. The output of the core circuit and the reference circuit are connected to the two inputs of the phase comparator, the output of the phase comparator is connected to the input of the third buffer, and the output of the third buffer is connected to the third external measurement terminal of the test circuit OUT3. The high potential terminals of the phase comparator and the third buffer are connected together with the high potential terminals of other frequency dividers and buffers, and connected to another high power supply terminal Vdd2 of the test circuit. Except for the core circuit (RO_CP), the low potential terminals of all other circuits in the test circuit are connected together, connected to another low potential terminal GND of the test circuit, and isolated from the low potential terminal Vss of the core circuit.

The output of the reference circuit RO_ref is also connected via several switching transistors S to the inputs of all inverters in the core circuit RO_CP. The gates of all switching transistors S are connected together and connected to an external control terminal VS. The switch S can be composed of a single nMOSFET (switching transistor), or a complementary switching circuit composed of two CMOSFETs. All switching transistors in RO_ref are always on, so the gates of all switching transistors in RO_ref are connected together, connected to another high power supply terminal Vdd3 of the test circuit, and isolated from the other two high power supply terminals Vdd1 and Vdd2 .

The whole circuit has 15 external contact pads (Pad), a high power supply terminal Vdd1 used by the core circuit, a low power supply terminal Vss of the core circuit, and a high power supply commonly used by the reference circuit, frequency divider, buffer and phase comparator Terminal Vdd2, a low power supply terminal GND commonly used by the reference circuit, frequency divider, buffer period and phase comparator, a control terminal Vdd3 of all switches in the reference circuit, and control terminals VS and VS1 of the three switches S, S1, and S2 , VS2, the control terminals Vp and Vn of the two pMOSFETs and nMOSFETs auxiliary transistors, the voltage application and current (Icpp and Icpn) measurement terminals of the two CPs, and the output terminals OUT1, OUT2, and OUT3 of the three circuits.

To sum up, the present invention proposes a multifunctional test circuit and test method for integrated circuit stress degradation. The core part of the test circuit (core circuit) is based on a ring oscillator (ring oscillator or RO), with additional auxiliary transistors, switching transistors and external control terminals. By controlling the on/off state of the auxiliary transistor and the switching state of the switching transistor through the control terminal, the core circuit can be in normal oscillation, stress oscillation, negative bias temperature instability (NBTI) stress of pMOSFETs, and positive bias of nMOSFETs. Voltage-temperature instability (PBTI) stress, hot hole injection (HHI or pHCI) or hot electron injection (HEI or nHCI) stress of pMOSFETs or nMOSFETs, and charge pumping (CP) measurement states of pMOSFETs or nMOSFETs. In addition to the core circuit, the test circuit also includes auxiliary circuits such as a reference circuit, a phase comparator, two frequency dividers and three buffers. The structure of the reference circuit is the same as that of the core circuit, but the CMOSFETs in the circuit are not subject to any stress, that is, the output frequency of the reference circuit is always the same as that of the core circuit in the normal oscillation state. In the stress degradation test of the core circuit, the reference circuit can be used as a frequency reference, and can also be used as a pulse generation source for CP measurement of CMOSFETs in the core circuit inverter. Therefore, the circuit of the present invention can measure the stress degradation characteristics of CMOSFETs devices and circuits, including dynamic stress degradation characteristics, NBTI stress degradation characteristics of pMOSFETs, and PBTI stress of nMOSFETs, through the frequency variation of ring vibration and the CP current variation of CMOSFETs. Degradation characteristics, hot hole injection degradation characteristics of pMOSFETs and hot electron injection degradation characteristics of nMOSFETs. the

Description of drawings

Fig. 1 is a structural diagram of the reliability test circuit of the present invention.

Figure 2 is the core part of the test circuit: the core circuit diagram.

Figure 3 is the reference part of the test circuit: reference circuit diagram.

Figure 4 is an alternative circuit diagram of the switch.

Fig. 5 is a circuit structure diagram of a frequency divider.

Fig. 6 is a kind of circuit structural diagram of buffer;

FIG. 7 is a structural diagram of a phase comparator.

Figure 8 is a layout architecture of the test circuit.

Fig. 9 is a connection and configuration diagram of the test circuit and peripheral instruments.

FIG. 10 is a bias voltage configuration diagram when the core circuit RO_CP is in a normal oscillation state.

Figure 11 is a diagram of the bias configuration of the pMOSFETs in the core circuit RO_CP inverter under NBTI stress.

Figure 12 is a bias configuration diagram of the nMOSFETs in the core circuit RO_CP inverter under PBTI stress.

Figure 13 is a diagram of the bias configuration of the pMOSFETs in the core circuit RO_CP inverter under HCI stress.

Figure 14 is a bias configuration diagram of the nMOSFETs in the core circuit RO_CP inverter under HCI stress.

Figure 15 is a diagram of the bias voltage configuration of the CMOSFETs in the RO_CP inverter of the core circuit when they are under dynamic stress.

Figure 16 is a diagram of the bias voltage configuration of the pMOSFETs in the RO_CP inverter of the core circuit during Icpp measurement.

Figure 17 is a diagram of the bias voltage configuration of the nMOSFETs in the RO_CP inverter of the core circuit when Icpn is measured.

Numbers in the figure: 1 is the ring oscillator RO_CP, 3 is the first frequency division circuit, 4 is the first buffer circuit, 5 is the reference circuit RO_ref, 6 is the second frequency division circuit, 7 is the second buffer circuit; 8 is the phase Comparator, 9 is the third buffer circuit; 11 is the auxiliary pMOSFET, 12 is the auxiliary nMOSFET, 13 is the switching transistor S1, 14 is the switching transistor S2, 51 is the switching transistor S; 201 is the high potential of the ring oscillator RO_CP, 202 is The low potential Vss of RO_CP, 203 is the first control terminal Vp, 204 is the second control terminal Vn; 205 is the third control terminal VS1, 206 is the fourth control terminal VS2; 207 is the external connection terminal Icpp; 208 is the external connection terminal Icpn; 209 is the external measurement terminal OUT1, 210 is the external measurement terminal OUT2; 211 is the third external measurement terminal OUT3, and 212 is the external control terminal VS. the

Detailed ways

The circuit and method of the invention are used for reliability testing of integrated circuits, especially for degradation testing of CMOSFETs in integrated circuits under NBTI, PBTI, HCI and dynamic stress. The test parameters include the frequency change caused by the stress degradation of CMOSFETs in the ring oscillator inverter, and also include the CP current generated by the CMOSFETs under stress. The overall circuit is shown in Figure 1. There are a total of 15 external contact pads (Pad), which are the high power supply terminal Vdd1 of the core circuit, the low power supply terminal Vss of the core circuit, and the reference circuit, frequency divider, buffer and phase comparator. The high power supply terminal Vdd2 used, the low power supply terminal GND commonly used by the reference circuit, frequency divider, buffer and phase comparator, the control terminal Vdd3 of all switches in the reference circuit, the control terminals VS, VS1 of switches S, S1, and S2 , VS2, control terminals Vp and Vn of pMOSFETs and nMOSFETs auxiliary transistors, voltage (Vcpp and Vcpn) application and current (Icpp and Icpn) test terminals during CP measurement, and output terminals OUT1, OUT2, OUT3 of the circuit.

Figure 2 is the core circuit RO_CP composed of ring oscillator, auxiliary transistors nMOSFETs and pMOSFETs, switching transistors S1 and S2. FIG. 3 is a reference circuit RO_ref having the same structure as the core circuit. Figure 4 is an alternative circuit for the switch. Fig. 5 is a circuit structure diagram of a frequency divider. Fig. 6 is a circuit configuration diagram of a buffer. Fig. 7 is a circuit diagram of a phase comparator. Figure 8 is a layout design architecture of the test circuit.

The peripheral instrument configuration connection of the circuit during measurement is shown in Figure 9. Among them, Vdd1, Vdd2, Vdd3, Vss, GND, VS, VS1, VS2, Vp, Vn are connected to external voltage sources, and different voltages (or grounding) can be applied according to different stresses and measurement modes. Icpp and Icpn are connected to the source measurement unit (SMU) in the semiconductor parameter analyzer to measure the current while applying the voltage. OUT1, OUT2, OUT3 can be connected with oscilloscope or spectrum analyzer.

Figure 10 is the bias voltage configuration of the core circuit in the normal oscillation state, which is used to measure the oscillation frequency of the ring oscillation: add the operating voltage Vdd0 of the integrated circuit to Vdd1, Vp, and Icpp, and ground Vn, Icpn, and Vss, VS1=VS2= VddI/O>Vdd0+Vthn, and the switching transistor S in FIG. 1 is turned off, that is, VS is grounded. In this configuration, the switching transistors S1 and S2 in the core circuit Figure 2 are turned on, and the auxiliary transistors pMOSFETs and nMOSFETs are turned off, so the core circuit is in a normal oscillation state, and the frequency-divided oscillation signal OUT1 can be measured by an oscilloscope , from which the output frequency fout can be read, thereby obtaining the normal oscillation frequency f=N*fout of the core circuit, where N is the frequency division coefficient of the frequency divider.

Figure 11 is the bias configuration of the pMOSFETs in the core circuit inverter under NBTI stress: Vstress is added to Vdd1, Icpp, Vp and Vn, VS1, Icpn, Vss are grounded, VS2=VddI/O>Vstress+Vthn, and Turn off the switch transistor S in Figure 1, that is, VS is grounded. In this configuration, the switching transistor S1 in the core circuit Figure 2 is turned off, S2 is turned on, the auxiliary transistor pMOSFETs are in the off state, and the nMOSFETs are in the on state. Therefore, the input of each stage inverter in RO_CP is at low potential 0, and the output of the inverter is at high potential Vstress, that is, the pMOSFETs in the RO_CP inverter are all in the NBTI stress state, while the nMOSFETs in the RO_CP inverter are not under stress.

Figure 12 is the bias configuration of nMOSFETs in the core circuit inverter under PBTI stress: Vstress is added to Vdd1 and Icpp, VS1, Icpn, Vp, Vn and Vss are grounded, VS2=VddI/O>Vstress+Vthn, and make The switching transistor S in FIG. 1 is turned off, that is, VS is grounded. In this configuration, the switching transistor S1 in the core circuit Figure 2 is turned off, the switching transistor S2 is turned on, the auxiliary transistor pMOSFETs are in the on state, and the nMOSFETs are in the off state. Therefore, the input of each inverter in RO_CP is at high potential Vstress, and the output of the inverter is at low potential 0, that is, the nMOSFETs in the RO_CP inverter are all in the PBTI stress state, while the pMOSFETs in the RO_CP inverter are not under stress.

Figure 13 is the bias configuration of pMOSFETs in the core circuit inverter under HCI stress: Vstress is added to Vdd1, Icpp, Vp and Vn, Icpn and Vss are grounded, VS1=VS2=VddI/O>Vstress+Vthn, and make The switch S in Fig. 1 is cut off, that is, VS is grounded. In this configuration, the switching transistor S1 and switching transistor S2 in the core circuit Figure 2 are turned on, the auxiliary transistor pMOSFETs are in the off state, and the nMOSFETs are in the on state. Therefore, the input and output of each inverter in RO_CP are at a potential between 0 and Vthn, that is, the pMOSFETs in the RO_CP inverter are under HCI stress, while the nMOSFETs in the RO_CP inverter are not under stress.

Figure 14 is the bias configuration of nMOSFETs in the core circuit inverter under HCI stress: Vstress is added to Vdd1 and Icpp, Vp, Vn, Icpn and Vss are grounded, VS1=VS2=VddI/O>Vstress+Vthn, and make The switch S in Fig. 1 is cut off, that is, VS is grounded. In this configuration, the switching transistor S1 and the switching transistor S2 in the core circuit Fig. 2 are turned on, the auxiliary transistor pMOSFETs are in the on state, and the nMOSFETs are in the off state. Therefore, the input and output of each stage inverter in RO_CP are at the potential between (Vstress+Vthp) and Vstress, that is, the nMOSFETs in the RO_CP inverter are in the HCI stress state, and the pMOSFETs in the RO_CP inverter are all Free from stress.

Figure 15 is the bias configuration of the core circuit under stress oscillation or dynamic stress: Vstress is added to Vdd1, Icpp and Vp, Vn, Icpn and Vss are grounded, VS1=VS2=VddI/O>Vstress+Vthn, and the figure The switch S in 1 is cut off, that is, VS is grounded. In this configuration, the switching transistor S1 and switching transistor S2 in the core circuit Figure 2 are turned on, and the auxiliary transistors pMOSFETs and nMOSFETs are turned off, so the core circuit is in a stress oscillation state, that is, a dynamic stress state.

Figure 16 is the bias voltage configuration of the pMOSFETs in the core circuit inverter when it is in CP measurement: add the operating voltage Vdd0 of the integrated circuit to Vdd2, apply the voltage Vdd≈Vdd0/2 to Vdd1 and Vss, Vp, Vn, VS2 and Icpn Grounded, VS1=Vdd3=VddI/O>Vdd0+Vthn, and switch S in FIG. 1 is turned on, that is, VS=VddI/O>Vdd0+Vthn. In this configuration, the switching transistor S1 in the core circuit Figure 2 is turned on, the switching transistor S2 is turned off, the auxiliary transistor pMOSFETs are turned on, and the nMOSFETs are turned off. The gate of the pMOSFETs in the inverter is provided with excitation pulses by RO_ref, and the source and drain voltages It is Vdd≈Vdd0/2, and the CP current Icpp can be measured while applying the voltage Vcpp=Vdd≈Vdd0/2 to the substrate.

Figure 17 is the bias voltage configuration of the nMOSFETs in the inverter of the core circuit when it is in CP measurement: add the operating voltage Vdd0 of the integrated circuit to Vdd2, Vp, Vn and Icpp, and apply the voltage Vdd≈Vdd0/2, VS2 to Vdd1 and Vss Grounded, VS1=Vdd3=VddI/O>Vdd0+Vthn, and switch S in FIG. 1 is turned on, that is, VS=VddI/O>Vdd0+Vthn. In this configuration, the switching transistor S1 in the core circuit Figure 2 is turned on, the switching transistor S2 is turned off, the auxiliary transistor pMOSFETs are turned off, and the nMOSFETs are turned on. The gate of the nMOSFETs in the inverter is provided with excitation pulses by RO_ref, and the source and drain voltages are It is Vdd≈Vdd0/2, and the CP current Icpn can be measured while applying the voltage Vcpn=Vdd≈Vdd0/2 to the substrate.

Utilize the circuit of the present invention to measure the NBTI stress degeneration steps of pMOSFETs in the core circuit inverter as follows:

(1) As shown in Figure 9 and Figure 10, the output frequency fout of the unstressed new circuit (Fresh circuit) is measured through the output terminal OUT1, and the normal state of the core circuit is calculated from the output frequency fout and the frequency division coefficient N of the frequency divider. Oscillation frequency f0.

(2) As shown in Figure 11, apply the NBTI stress of Vstress on the core circuit. the

(3) After the stress time tstress1, the circuit configuration returns to the normal oscillation state shown in Figure 10, and the oscillation frequency f1 (NBTI, tstress1) of the core circuit is measured. the

(4) Repeat steps (2) and (3) to measure the oscillation frequency f2(NBTI, tstress2), f3(NBTI, tstress3) etc.

(5) Calculate the frequency change of the core circuit under NBTI stress Δf1(NBTI)=f1(NBTI, tstress1)-f0, Δf2(NBTI)=f2(NBTI, tstress2)-f0, Δf3(NBTI)=f3(NBTI, tstress3) -f0 etc.

Utilize the circuit of the present invention to measure the PBTI stress degeneration steps of nMOSFETs in the core circuit inverter as follows:

(1) As shown in Figure 9 and Figure 10, the output frequency fout of the unstressed new circuit (Fresh circuit) is measured through the output terminal OUT1, and the normal state of the core circuit is calculated from the output frequency fout and the frequency division coefficient N of the frequency divider. Oscillation frequency f0.

(2) As shown in Figure 12, apply the PBTI stress of Vstress on the core circuit.

(3) After the stress time tstress1, the circuit configuration returns to the normal oscillation state shown in Figure 10, and the oscillation frequency f1 (PBTI, tstress1) of the core circuit is measured.

(4) Repeat steps (2) and (3) to measure the oscillation frequencies f2(PBTI, tstress2), f3(PBTI, tstress3) etc. of the core circuit under PBTI stress for the time tstress2, tstress3, etc. respectively.

(5) Calculate the frequency change of the core circuit under PBTI stress Δf1(PBTI)=f1(PBTI, tstress1)-f0, Δf2(PBTI)=f2(PBTI, tstress2)-f0, Δf3(PBTI)=f3(PBTI, tstress3) -f0 etc.

Utilize the circuit of the present invention to measure the HCI (HHI) stress degradation steps of pMOSFETs in the core circuit inverter as follows:

(1) As shown in Figure 9 and Figure 10, the output frequency fout of the unstressed new circuit (Fresh circuit) is measured through the output terminal OUT1, and the normal state of the core circuit is calculated from the output frequency fout and the frequency division coefficient N of the frequency divider. Oscillation frequency f0.

(2) As shown in Figure 13, apply the HCI stress of Vstress on the core circuit.

(3) After the stress time tstress1, the circuit configuration returns to the normal oscillation state shown in Figure 10, and the oscillation frequency f1 (HHI, tstress1) of the core circuit is measured.

(4) Repeat steps (2) and (3) to measure the oscillation frequencies f2(HHI, tstress2), f3(HHI, tstress3) etc. of the core circuit under HHI stress for the time tstress2, tstress3, etc. respectively.

(5) Calculate the frequency change of the core circuit under HHI stress Δf1(HHI)=f1(HHI, tstress1)-f0, Δf2(HHI)=f2(HHI, tstress2)-f0, Δf3(HHI)=f3(HHI, tstress3) -f0 etc.

Utilize the circuit of the present invention to measure the HCI (HEI) stress degradation steps of nMOSFETs in the core circuit inverter as follows:

(1) As shown in Figure 9 and Figure 10, the output frequency fout of the unstressed new circuit (Fresh circuit) is measured through the output terminal OUT1, and the normal state of the core circuit is calculated from the output frequency fout and the frequency division coefficient N of the frequency divider. Oscillation frequency f0.

(2) As shown in Figure 14, apply the HCI stress of Vstress on the core circuit.

(3) After the stress time tstress1, the circuit configuration returns to the normal oscillation state shown in Figure 10, and the oscillation frequency f1 (HEI, tstress1) of the core circuit is measured.

(4) Repeat steps (2) and (3) to measure the oscillation frequencies f2(HEI, tstress2), f3(HEI, tstress3) etc. of the core circuit under HEI stress for tstress2, tstress3, etc. respectively.

(5) Calculate the frequency change of the core circuit under HEI stress Δf1(HEI)=f1(HEI, tstress1)-f0, Δf2(HEI)=f2(HEI, tstress2)-f0, Δf3(HEI)=f3(HEI, tstress3) -f0 etc.

Utilize the circuit of the present invention to measure the dynamic (Dynamic) stress degradation steps of CMOSFETs in the core circuit inverter as follows:

(1) As shown in Figure 9 and Figure 10, the output frequency fout of the unstressed new circuit (Fresh circuit) is measured through the output terminal OUT1, and the normal state of the core circuit is calculated from the output frequency fout and the frequency division coefficient N of the frequency divider. Oscillation frequency f0.

(2) As shown in Figure 15, a dynamic stress of Vstress is applied to the core circuit.

(3) After the stress time tstress1, the circuit configuration returns to the normal oscillation state shown in Figure 10, and the oscillation frequency f1 (Dynamic, tstress1) of the core circuit is measured.

(4) Repeat steps (2) and (3) to measure the oscillation frequencies f2 (Dynamic, tstress2), f3 (Dynamic, tstress3) etc. of the core circuit under dynamic stress for tstress2, tstress3, etc. respectively.

(5) Calculate the frequency change of the core circuit under dynamic stress Δf1 (Dynamic) = f1 (Dynamic, tstress1) - f0, Δf2 (Dynamic) = f2 (Dynamic, tstress2) - f0, Δf3 (Dynamic) = f3 (Dynamic, tstress3) -f0 etc.

Utilize the phase comparator in the circuit of the present invention to measure the stress degradation step of MOSFETs in the core circuit inverter as follows:

(1) As shown in Figures 11, 12, 13, 14 and 15, apply NBTI, PBTI, HHI, HEI or dynamic stress of Vstress on the core circuit, respectively.

(2) After the stress time tstress1, the circuit configuration returns to the normal oscillation state shown in Figure 10, and the frequency difference Δf1(Stress, tstress1)=fOUT3 between the core circuit and the reference circuit RO_ref is measured through OUT3.

(3) Repeat steps (1) and (2), measure the frequency difference Δf2 (Stress, tstress2), Δf3 (Stress, tstress3) of the core circuit and the reference circuit RO_ref after the core circuit is under various stresses for tstress2, tstress3, etc. through OUT3 )wait.

It should be noted that because the circuit is affected by factors such as layout mismatch during design or process deviation during manufacturing, the output frequency of the reference circuit RO_ref and the unstressed new circuit RO_CP in the normal oscillation state may not be equal, but there is A certain deviation, at this time, the deviation f0 can be measured through the output terminals OUT1, OUT2, and OUT3, and f0 can be subtracted (or added) from the frequency difference measured in step (2).

Utilize the circuit of the present invention to measure the stress degradation step of the CP current Icpp of pMOSFETs in the core circuit inverter as follows:

(1) As shown in Figure 9 and Figure 16, measure the CP current Icpp0 of the unstressed new circuit (Fresh circuit) through the Icpp terminal.

(2) As shown in Figures 11, 12, 13, 14 and 15, apply NBTI, PBTI, HHI, HEI or dynamic stress of Vstress on the core circuit, respectively.

(3) After the stress time tstress1, the circuit configuration returns to the configuration shown in Figure 16, and the CP current Icpp1 (Stress, tstress1) is measured through the Icpp terminal.

(4) Repeat steps (2) and (3), and measure the CP current Icpp2 (Stress, tstress2), Icpp3 (Stress, tstress3), etc. of the core circuit under various stresses for tstress2, tstress3, etc. through Icpp.

(5) Calculate the CP current change of the core circuit under various stresses ΔIcpp1 (Stress) = Icpp1 (Stress, tstress1) - Icpp0, ΔIcpp2 (Stress) = Icpp2 (Stress, tstress2) - Icpp0, ΔIcpp3 (Stress) = Icpp3 ( Stress, tstress3)-Icpp0, etc.

Utilize the circuit of the present invention to measure the stress degradation step of the CP current Icpn of nMOSFETs in the core circuit inverter as follows:

(1) As shown in Figure 9 and Figure 17, measure the CP current Icpn0 of the unstressed new circuit (Fresh circuit) through the Icpn terminal.

(2) As shown in Figures 11, 12, 13, 14 and 15, apply NBTI, PBTI, HHI, HEI or dynamic stress of Vstress on the core circuit, respectively.

(3) After the stress time tstress1, the circuit configuration returns to the configuration shown in Figure 17, and the CP current Icpn1 (Stress, tstress1) is measured through the Icpn terminal.

(4) Repeat steps (2) and (3), and use Icpn to measure the CP current Icpn2 (Stress, tstress2), Icpn3 (Stress, tstress3), etc. of the core circuit under various stresses for tstress2, tstress3, etc. respectively.

(5) Calculate the CP current change of the core circuit under various stresses ΔIcpn1 (Stress) = Icpn1 (Stress, tstress1) - Icpn0, ΔIcpn2 (Stress) = Icpn2 (Stress, tstress2) - Icpn0, ΔIcpn3 (Stress) = Icpn3 ( Stress, tstress3)-Icpn0 etc.

Claims (4)

1. A multifunctional test circuit for integrated circuit stress degradation, characterized in that it includes a core circuit, which includes a ring oscillator RO_CP (1); every two stages of inverters in the ring oscillator RO_CP (1) Between them, a group of auxiliary pMOSFETs (11) and nMOSFETs (12) are connected, wherein the sources of the auxiliary pMOSFETs and nMOSFETs are respectively connected to the high potential Vdd1 (201) and low potential Vss (202) of the ring oscillator RO_CP, each group The drains of pMOSFETs and nMOSFETs are connected together, and are respectively connected to the output of the previous stage inverter and the input of the latter stage inverter through the switching transistor S1 (13) and switching transistor S2 (14); the gates of all auxiliary pMOSFETs are connected to together and connected to the first control terminal Vp (203), the gates of all auxiliary nMOSFETs are connected together and connected to the second control terminal Vn (204); the gates of all switching transistors S1 are connected together and connected to To the third control terminal VS1 (205), the gates of all switching transistors S2 are connected together and connected to the fourth control terminal VS2 (206); the substrates of the pMOSFETs in all inverters of the ring oscillator RO_CP are connected together , separately connected to an external connection terminal Icpp (207); the substrates of nMOSFETs in all inverters of the ring oscillator RO_CP are connected together, and separately connected to an external connection terminal Icppn (208); all switching transistors are I/ O devices, whose operating voltage is higher than that of the core circuit to avoid threshold loss during high-level transmission; The test circuit also includes a first frequency division circuit (3) with a frequency division factor of N and a first buffer circuit (4); the output of the core circuit (1) is connected to the first frequency division circuit (3) Input, the output of the first frequency division circuit (3) is connected to the input of the first buffer circuit (4), and the output of the first buffer circuit (4) is connected to an external measuring terminal OUT1 (209). 2. The multifunctional test circuit for integrated circuit stress degradation according to claim 1, characterized in that the test circuit also includes a reference circuit RO_ref (5) with the same structure as the core circuit, and a second frequency circuit with the same structure as the first frequency division circuit Two frequency division circuit (6) and a second buffer circuit (7) identical to the first buffer circuit; the output of the reference circuit RO_ref is connected to the input of the second frequency division circuit (6), and the second frequency division circuit (6) The output of the second buffer circuit (7) is connected to the input of the second buffer circuit (7), and the output of the second buffer circuit (7) is connected to another external measurement terminal OUT2 (210); in addition, the test circuit also includes a phase comparator (8 ) and the third buffer circuit (9); the output of the core circuit (1) is also connected to an input of the phase comparator (8), and the output of the reference circuit RO_ref (5) is also connected to the other of the phase comparator (8) Input, the output of the phase comparator (8) is connected to the input of the third buffer circuit (9), and the output of the third buffer circuit (9) is connected to the third external measurement terminal OUT3 (211); refer to the circuit RO_ref (5) The output of the output is also connected to the input of each stage inverter in the ring oscillator RO_CP (1) through several switching transistors S (51), and the gates of all switching transistors S are connected together and connected to the external control terminal VS (212) . 3. The multifunctional test circuit of integrated circuit stress degradation as claimed in claim 2, is characterized in that: In the core circuit, when the control terminal voltage VS of the switching transistor S=0V, and when the control terminal voltage VS1 of the switching transistors S1 and S2=VddI/O>Vdd+the threshold voltage Vthn of the switching transistor, p and n auxiliary The control voltage Vp=Vdd and Vn=Vss of the transistor, the charge pump control terminal voltage Vcpp=Vdd and Vcpn=Vss of the p and n transistor, the high power supply terminal voltage of the core circuit Vdd1=Vdd, Vdd=Vdd0, Vdd0 is the integrated circuit The operating voltage of the switching transistor S is off, the switching transistor S1 and the switching transistor S2 are on, all the p and n auxiliary transistors are off, and the ring oscillator RO_CP is in a normal oscillation state; In the reference circuit RO_ref (5), when the high power supply terminal voltage Vdd2=Vdd of the reference circuit, the switch control terminal voltage Vdd3=VddI/O>Vdd+Vthn in the reference circuit, Vdd=Vdd0 is the working voltage of the integrated circuit When , all MOSFETs in the reference circuit RO_ref are not stressed, and RO_ref is always in a normal oscillation state, that is, the output frequency of RO_ref is always the same as the output frequency of the core circuit; In the core circuit, when the switch control terminal VS=0V, and when VS1=0V, VS2=VddI/O>Vdd+Vthn, Vp=Vn=Vdd, Vcpp=Vdd, Vcpn=Vss, Vdd1=Vdd, wherein When Vdd=Vstress>Vdd0 is the stress voltage, the switching transistor S and the switching transistor S1 are turned off, the switching transistor S2 is turned on, the p auxiliary transistor is turned off, the n auxiliary transistor is turned on, and the gates, sources and gates of pMOSFETs in all inverters of RO_CP The drains are at Vss, Vdd, and Vdd, respectively; the gates and sources of the corresponding nMOSFETs are at Vss, that is, the pMOSFETs in all inverters of RO_CP are in a stress state of negative bias temperature instability (NBTI), while the corresponding nMOSFETs in a non-stressed state; In the core circuit, when the switch control terminal VS=0V, and when VS1=0V, VS2=VddI/O>Vdd+Vthn, Vp=Vn=Vss, Vcpp=Vdd, Vcpn=Vss, Vdd1=Vdd, Vdd =Vstress>Vdd0 is the stress voltage, the switching transistor S and the switching transistor S1 are off, the switching transistor S2 is on, the p auxiliary transistor is on, the n auxiliary transistor is off, and the gates and sources of pMOSFETs in all inverters of RO_CP are at Vdd, the gate, source, and drain of the corresponding nMOSFETs are at Vdd, Vss, and Vss, respectively, that is, the nMOSFETs of all inverters in RO_CP are in the stress state of positive bias temperature instability (PBTI), while the corresponding pMOSFETs are at non-stress state; In the core circuit, when the switch control terminal VS=0V, and when VS1=VS2=VddI/O>Vdd+Vthn, Vp=Vn=Vdd, Vcpp=Vdd, Vcpn=Vss, Vdd1=Vdd, Vdd=Vstress > When Vdd0 is the stress voltage, the switching transistor S is turned off, the switching transistor S1 and the switching transistor S2 are turned on, the p auxiliary transistor is turned off, the n auxiliary transistor is turned on, and the pMOSFETs of all inverters in RO_CP are in the conductive state, and the gate and The drains are at the same potential, but the corresponding nMOSFETs are in the off state, that is, the pMOSFETs of all inverters in RO_CP are in the stress state of hot carrier injection (pHCI), while the corresponding nMOSFETs are in the unstressed state; In the core circuit, when the switch control terminal VS=0V, and when VS1=VS2=VddI/O>Vdd+Vthn, Vp=Vn=Vss, Vcpp=Vdd, Vcpn=Vss, Vdd1=Vdd, Vdd=Vstress When >Vdd0 is the stress voltage, the switching transistor S is off, the switching transistor S1 and the switching transistor S2 are on, the p auxiliary transistor is on, the n auxiliary transistor is off, and the pMOSFETs of all inverters in RO_CP are in the off state, but the corresponding nMOSFETs are in the on state The on state, and the gate and drain are at the same potential, that is, the nMOSFETs of all inverters in RO_CP are in the stressed state of hot carrier injection (nHCI), while the corresponding pMOSFETs are in the unstressed state; In the core circuit, when the switch control terminal VS=0V, and when VS1=VS2=VddI/O>Vdd+Vthn, Vp=Vdd, Vn=Vss, Vcpp=Vdd, Vcpn=Vss, Vdd1=Vdd, Vdd When =Vstress>Vdd0 is the stress voltage, the switching transistor S is turned off, the switching transistor S1 and the switching transistor S2 are turned on, and the p and n auxiliary transistors are both turned off, that is, RO_CP is in a state of stress oscillation, or the CMOSFETs in RO_CP are in a state of dynamic stress; In the core circuit, when the switch control terminal VS=VddI/O>Vdd0+Vthn, and when VS1=VddI/O>Vdd0+Vthn, VS2=0V, Vp=Vn=0V, Vcpp=Vdd, Vcpn=0V , Vdd1=Vss=Vdd, Vdd≈Vdd0/2, the switching transistor S and the switching transistor S1 are turned on, the switching transistor S2 is turned off, the p auxiliary transistor is turned on, the n auxiliary transistor is turned off, and the pMOSFETs of all inverters in RO_CP are in charge Pumping (CP) test state, that is, the gate of pMOSFETs is provided with excitation pulses by RO_ref, the source and drain voltages are both Vdd≈Vdd0/2, and the substrate voltage Vcpp=Vdd≈Vdd0/2 can be measured at the same time. CP current Icpp; In the core circuit, when the switch control terminal VS=VddI/O>Vdd0+Vthn, and when VS1=VddI/O>Vdd0+Vthn, VS2=0V, Vp=Vn=Vdd0, Vcpp=Vdd0, Vcpn=Vdd , Vdd1=Vss=Vdd, when Vdd≈Vdd0/2, the switching transistor S and the switching transistor S1 are turned on, the switching transistor S2 is turned off, the p auxiliary transistor is turned off, the n auxiliary transistor is turned on, and the nMOSFETs of all inverters in RO_CP are at CP In the test state, the gate of nMOSFETs is provided with excitation pulses by RO_ref, the source and drain voltages are both Vdd≈Vdd0/2, and the CP current Icpn can be measured while the substrate voltage is Vcpn=Vdd≈Vdd0/2. 4. Utilize the method for test circuit measurement integrated circuit stress degradation as claimed in claim 3, it is characterized in that: 1. The steps to measure the NBTI stress degradation of pMOSFETs in the core circuit inverter are as follows: (1) Measure the output frequency fout of the unstressed new circuit, that is, the Fresh circuit, through the output terminal OUT1, and calculate the normal oscillation frequency f0 of the core circuit from the output frequency fout and the frequency division coefficient N of the frequency divider; (2) Apply the NBTI stress of Vstress on the core circuit; (3) After the stress time tstress1, the circuit configuration returns to the normal oscillation state, and the oscillation frequency f1 of the core circuit is measured (NBTI, tstress1); (4) Repeat steps (2) and (3) to measure the oscillation frequencies f2 (NBTI, tstress2) and f3 (NBTI, tstress3) of the core circuit under NBTI stress with time tstress2 and tstress3 respectively; (5) Calculate the frequency change of the core circuit under NBTI stress Δf1(NBTI)=f1(NBTI, tstress1)-f0, Δf2(NBTI)=f2(NBTI, tstress2)-f0, Δf3(NBTI)=f3(NBTI, tstress3) -f0; 2. Measure the PBTI stress degradation steps of nMOSFETs in the core circuit inverter as follows: (1) Measure the output frequency fout of the unstressed new circuit through the output terminal OUT1, and calculate the normal oscillation frequency f0 of the core circuit from the output frequency fout and the frequency division coefficient N of the frequency divider; (2) Apply the PBTI stress of Vstress on the core circuit; (3) After the stress time tstress1, the circuit configuration returns to the normal oscillation state, and the oscillation frequency f1 of the core circuit is measured (PBTI, tstress1); (4) Repeat steps (2) and (3) to measure the oscillation frequencies f2 (PBTI, tstress2) and f3 (PBTI, tstress3) of the core circuit under PBTI stress for the time tstress2 and tstress3 respectively; (5) Calculate the frequency change of the core circuit under PBTI stress Δf1(PBTI)=f1(PBTI, tstress1)-f0, Δf2(PBTI)=f2(PBTI, tstress2)-f0, Δf3(PBTI)=f3(PBTI, tstress3) -f0; 3. Measure the HCI stress degradation steps of pMOSFETs in the core circuit inverter as follows: (1) Measure the output frequency fout of the unstressed new circuit through the output terminal OUT1, and calculate the normal oscillation frequency f0 of the core circuit from the output frequency fout and the frequency division coefficient N of the frequency divider; (2) Apply the HCI stress of Vstress on the core circuit; (3) After the stress time tstress1, the circuit configuration returns to the normal oscillation state, and the oscillation frequency f1 (HHI, tstress1) of the core circuit is measured; (4) Repeat steps (2) and (3) to measure the oscillation frequencies f2(HHI, tstress2) and f3(HHI, tstress3) of the core circuit under HHI stress for the time tstress2 and tstress3 respectively; (5) Calculate the frequency change of the core circuit under HHI stress Δf1(HHI)=f1(HHI, tstress1)-f0, Δf2(HHI)=f2(HHI, tstress2)-f0, Δf3(HHI)=f3(HHI, tstress3) -f0; 4. Measure the HCI stress degradation steps of nMOSFETs in the core circuit inverter as follows: (1) Measure the output frequency fout of the unstressed new circuit through the output terminal OUT1, and calculate the normal oscillation frequency f0 of the core circuit from the output frequency fout and the frequency division coefficient N of the frequency divider; (2) Apply the HCI stress of Vstress on the core circuit; (3) After the stress time tstress1, the circuit configuration returns to the normal oscillation state, and the oscillation frequency f1 (HEI, tstress1) of the core circuit is measured; (4) Repeat steps (2) and (3) to measure the oscillation frequencies f2(HEI, tstress2) and f3(HEI, tstress3) of the core circuit under HEI stress for the time tstress2 and tstress3 respectively; (5) Calculate the frequency change of the core circuit under HEI stress Δf1(HEI)=f1(HEI, tstress1)-f0, Δf2(HEI)=f2(HEI, tstress2)-f0, Δf3(HEI)=f3(HEI, tstress3) -f0; 5. The steps to measure the dynamic stress degradation of CMOSFETs in the core circuit inverter are as follows: (1) Measure the output frequency fout of the unstressed new circuit through the output terminal OUT1, and calculate the normal oscillation frequency f0 of the core circuit from the output frequency fout and the frequency division coefficient N of the frequency divider; (2) Apply the dynamic stress of Vstress on the core circuit; (3) After the stress time tstress1, the circuit configuration returns to the normal oscillation state, and the oscillation frequency f1 (Dynamic, tstress1) of the core circuit is measured; (4) Repeat steps (2) and (3) to measure the oscillation frequencies f2 (Dynamic, tstress2) and f3 (Dynamic, tstress3) of the core circuit under dynamic stress for tstress2 and tstress3 respectively; (5) Calculate the frequency change of the core circuit under dynamic stress Δf1 (Dynamic) = f1 (Dynamic, tstress1) - f0, Δf2 (Dynamic) = f2 (Dynamic, tstress2) - f0, Δf3 (Dynamic) = f3 (Dynamic, tstress3) -f0; 6. Another method for measuring the stress degradation of MOSFETs in the core circuit inverter is as follows: (1) Apply NBTI, PBTI, HHI, HEI or dynamic stress of Vstress on the core circuit; (2) After the stress time tstress1, the circuit configuration returns to the normal oscillation state, and the frequency difference between the core circuit and the reference circuit RO_ref is measured through OUT3 Δf1 (Stress, tstress1) = fOUT3; (3) Repeat steps (1) and (2), and measure the frequency difference Δf2 (Stress, tstress2) and Δf3 (Stress, tstress3) of the core circuit with the reference circuit RO_ref after the time of tstress2 and tstress3 of the core circuit under various stresses through OUT3 ; 7. Measure the stress degradation steps of the CP current Icpp of the pMOSFETs in the inverter of the core circuit as follows: (1) Measure the CP current Icpp0 of the unstressed new circuit through the Icpp terminal; (2) Apply NBTI, PBTI, HHI, HEI or dynamic stress of Vstress on the core circuit; (3) After the stress time tstress1, the circuit configuration returns to the configuration of step (1), and the CP current Icpp1 (Stress, tstress1) is measured through the Icpp terminal; (4) Repeat steps (2) and (3), and measure the CP current Icpp2 (Stress, tstress2) and Icpp3 (Stress, tstress3) of the core circuit under various stresses under various stress times through Icpp; (5) Calculate the CP current change of the core circuit under various stresses ΔIcpp1 (Stress) = Icpp1 (Stress, tstress1) - Icpp0, ΔIcpp2 (Stress) = Icpp2 (Stress, tstress2) - Icpp0, ΔIcpp3 (Stress) = Icpp3 ( Stress,tstress3)-Icpp0; 8. Measure the stress degradation steps of the CP current Icpn of the nMOSFETs in the inverter of the core circuit as follows: (1) Measure the CP current Icpn0 of the unstressed new circuit through the Icpn terminal; (2) Apply NBTI, PBTI, HHI, HEI or dynamic stress of Vstress on the core circuit; (3) After the stress time tstress1, the circuit configuration returns to the configuration of step (1), and the CP current Icpn1 (Stress, tstress1) is measured through the Icpn terminal; (4) Repeat steps (2) and (3), and measure the CP current Icpn2 (Stress, tstress2) and Icpn3 (Stress, tstress3) of the core circuit under various stresses under various stresses by Icpn after the time is tstress2 and tstress3 respectively; (5) Calculate the CP current change of the core circuit under various stresses ΔIcpn1 (Stress) = Icpn1 (Stress, tstress1) - Icpn0, ΔIcpn2 (Stress) = Icpn2 (Stress, tstress2) - Icpn0, ΔIcpn3 (Stress) = Icpn3 ( Stress,tstress3)-Icpn0.

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