JP3679992B2 - Semiconductor integrated circuit and test method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit configured by integrating a plurality of N-channel MOSFETs and a plurality of P-channel MOSFETs, and in particular, each of the plurality of channel-type MOSFETs includes MOSFETs having at least different threshold voltages. The present invention relates to a semiconductor integrated circuit and a test method thereof.
[0002]
[Prior art]
In recent years, portable information devices represented by PHS (Personal Handyphone System), PDA (Personal Digital Assistant) and the like have become widespread. One of the components of this portable information device is a semiconductor integrated circuit (hereinafter referred to as IC). In such an IC, there is a strong demand to reduce power consumption without reducing processing speed performance.
[0003]
ICs using CMOS technology are known to have lower power consumption than ICs using bipolar technology or EDMOS technology. However, in recent years, with the increase in operating frequency of ICs, the size of power consumption has become a problem even in ICs using CMOS technology.
[0004]
The power consumption of a CMOS logic gate circuit in an IC using CMOS technology is generally approximated by the following equation.
P∝K · C · Vdd2 · f + Ileak · Vdd (1) where K is the switching probability, C is the output load capacity of the CMOS logic gate circuit, Vdd is the power supply voltage, and f is the power supply voltage. The operating frequency, Ileak, is a subthreshold leakage current. The subthreshold leakage current will be described later. Note that “·” in the expression (1) is a multiplier, and the same applies to the expressions described later.
[0005]
When the IC is in an operation mode (for example, when a clock signal of a predetermined frequency is supplied to the CMOS logic gate circuit and the CMOS logic gate circuit is in an operating state), the first term of the equation (1) is dominant and consumed. The power is proportional to the square of the power supply voltage Vdd. Further, when the IC is in the standby mode (when the supply of the clock signal to the CMOS logic gate circuit is prohibited and the operation of the CMOS logic gate circuit is stopped), the operating frequency f becomes zero. The second term of the equation becomes dominant. As can be seen from the equation (1), by reducing the power supply voltage Vdd, the power consumption particularly in the operation mode can be significantly reduced. For this reason, there is a growing demand for ICs used in portable information devices to operate at a low power supply voltage.
[0006]
As described above, the power consumption in the IC can be reduced by reducing the power supply voltage Vdd. However, when the power supply voltage Vdd is lowered, the gate delay time tpd of the CMOS logic gate circuit constituting the IC is increased. The gate delay time tpd of the CMOS logic gate circuit is generally approximated by the following equation.
tpd = C · Vdd / (Vdd−Vt) α (2) In the equation (2), C is an output load capacitance of the CMOS logic gate circuit, Vdd is a power supply voltage, and Vt is a switching MOSFET. The threshold voltage α is a coefficient determined according to the device generation, and 1 ≦ α ≦ 2.
[0007]
As apparent from the equation (2), it can be seen that when the power supply voltage Vdd is lowered, the gate delay time tpd gradually increases. In particular, if the power supply voltage Vdd is reduced to near the threshold voltage Vt of the MOSFET, the denominator on the right side of the equation (2) becomes a small numerical value, and it can be seen that the gate delay time tpd significantly increases. Therefore, in order to lower the power supply voltage Vdd without increasing the gate delay time tpd, it is necessary to lower the threshold voltage Vt of the MOSFET in accordance with the lowering of the power supply voltage Vdd.
[0008]
On the other hand, the power consumption in the standby mode of the CMOS logic gate circuit (hereinafter referred to as standby power consumption) is leakage when the gate-source voltage of the MOSFET is 0 V as shown in the second term of the equation (1). The current is generally determined by Ileak (generally referred to as subthreshold leakage current). The subthreshold leakage current Ileak is generally approximated by the following equation.
Ileak'exp (-Vt (S / In10)) (3)
Here, in Equation (3), Vt is a threshold voltage of the MOSFET, and S is one of the numerical values indicating the MOSFET characteristics called a subthreshold coefficient. Specifically, the gate-source voltage of the MOSFET is a threshold. It is a value representing current-voltage characteristics in a region below the value voltage Vt. Generally, in a submicron MOSFET, the value is about 80 to 90 mV / decade.
[0009]
As apparent from the equation (3), it is shown that when the threshold voltage Vt is set low, the subthreshold leakage current Ileak increases exponentially. For example, when the threshold voltage of a MOSFET constituting an IC having a CMOS logic gate circuit is lowered by 0.3 V, the subthreshold leakage current Ileak in the standby mode of the IC increases by 3 to 4 digits. It becomes.
[0010]
As described above, the subthreshold leakage current Ileak and the gate delay time tpd when the threshold voltage Vt is changed are in a trade-off relationship. In general, in an IC having a CMOS logic gate circuit, a threshold value Vt is set so that a necessary gate delay time tpd can be obtained while satisfying standby power consumption permitted by a product specification or the like. Yes. However, it has become extremely difficult to satisfy both the satisfactory subthreshold leakage current Ileak and the gate delay time tpd in response to the recent demand for lowering the power supply voltage Vdd.
[0011]
In the CMOS technology, there is a technology disclosed in the following document as a technology capable of reducing standby power consumption without deteriorating operation speed characteristics (for example, gate delay time tpd).
Reference: “1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS.” IEEE Journal of Solid-State Circuits 30 [8], pp. 847-854, 1995
[0012]
The technique disclosed in the above document is called Multi-Threshold Voltage CMOS (hereinafter referred to as MTCMOS) technique. The MTCMOS technology disclosed in the above document will be briefly described below.
[0013]
In an IC using the MTCMOS technology, a power supply voltage is supplied to a logic gate circuit from a high potential side pseudo power supply voltage line and a low potential side pseudo power supply voltage line. The logic gate circuit is composed of a P-channel MOSFET and an N-channel MOSFET having a low threshold voltage. The high potential side pseudo power supply voltage line is supplied with the high potential side power supply voltage via a switch composed of a P channel MOSFET having a threshold voltage higher than that of the P channel MOSFET constituting the logic gate circuit. The The low-potential-side power supply voltage line is supplied with the low-potential-side power supply voltage via a switch made of an N-channel MOSFET having a threshold voltage higher than that of the N-channel MOSFET constituting the logic gate circuit. The
[0014]
When the N-channel MOSFET and the switch comprising the N-channel MOSFET constituting the IC are viewed as a four-terminal element having drain, source, gate, and substrate terminals, the substrate terminal of these N-channel MOSFETs is P The low-potential side power supply voltage is supplied through the well layer or the P-type semiconductor substrate (when the P-type semiconductor substrate is used). Further, when the switch comprising the P-channel MOSFET and the P-channel MOSFET constituting the IC is viewed as a four-terminal element having drain, source, gate, and substrate terminals, the substrate terminals of these P-channel MOSFETs Is supplied with a high-potential-side power supply voltage via an N well layer or an N type semiconductor substrate (when an N type semiconductor substrate is used).
[0015]
The IC using the MTCMOS technology configured as described above makes the N-channel MOSFET and the P-channel MOSFET serving as the switches conductive in the operation mode. For this reason, the high potential side pseudo power supply voltage line has a potential substantially equal to the high potential side power supply voltage due to the high potential side power supply voltage supplied via the P-channel MOSFET as a switch. Similarly, the low-potential-side pseudo power supply voltage line becomes substantially equal to the low-potential-side power supply voltage due to the low-potential-side power supply voltage supplied via the N-channel MOSFET as a switch. For this reason, since the high potential side power supply voltage and the low potential side power supply voltage are respectively supplied to the logic gate circuit, the logic gate circuit can perform a desired logic operation.
[0016]
Here, since the threshold voltages of the N-channel MOSFET and the P-channel MOSFET constituting the logic gate circuit are lowered, when the N-channel MOSFET and the P-channel MOSFET having a high threshold voltage are used, In comparison, it is possible to operate with the power supply voltage Vdd being lowered without increasing the gate delay time tpd. That is, it is possible to reduce the power consumption in the operation mode while maintaining the same speed performance as when the high threshold voltage N-channel MOSFET and P-channel MOSFET are used for the logic gate circuit.
[0017]
In the standby mode, the N-channel MOSFET and the P-channel MOSFET as the switches described above are brought into a non-conductive state. For this reason, the subthreshold leakage current Ileak flowing from the high potential side pseudo power supply voltage to the low potential side power supply voltage is a subthreshold current characteristic in the non-conduction state of the N-channel MOSFET and the P-channel MOSFET constituting the above-described switch. It will be decided. As described above, since the threshold voltage of the N-channel MOSFET and the P-channel MOSFET constituting the switch is increased, the subthreshold leakage current Ileak can be reduced. That is, the subthreshold leakage current Ileak should be equal to that when the logic gate circuit is configured with a high threshold voltage MOSFET, although the logic gate circuit is configured with a low threshold voltage MOSFET. it can.
[0018]
As described above, in an IC using the MTCMOS technology, the power supply voltage Vdd is reduced to reduce the power consumption in the operation mode, and the delay performance is maintained without increasing the gate delay time tpd of the logic gate circuit. In addition, standby power consumption due to the subthreshold leakage current in the standby mode can be reduced.
[0019]
[Problems to be solved by the invention]
As described above, although an IC using MTCMOS technology can provide excellent characteristics, there is a problem of concern during the test. This is in particular that the IDDQ test introduced at the time of mass-production shipment testing of products in recent years cannot be applied in order to improve the defect detection rate of large-scale logic ICs.
[0020]
The IDDQ test is a logic gate circuit configured using a MOSFET having a high threshold voltage. In a non-defective product, the power source current (high potential) is set when the MOSFET constituting the logic gate circuit is not switching. IDD (current flowing from the low-side power supply voltage to the low-potential side power supply voltage) has a characteristic that only a very small leakage current (for example, several nA to several tens μA in the whole IC) determined by the subthreshold leakage current of each MOSFET flows. It is used.
[0021]
That is, the current value of the power supply current IDD is measured in a stable state in several patterns in which the output voltage of each logic gate circuit in the IC is set to a high voltage level or a low voltage level. If the measured current value of the power supply current IDD is sufficiently larger than the predicted current value of the leakage current, some abnormality (such as a short circuit between wires or a broken wire) occurs within the IC. It can be judged that That is, by measuring the power supply current IDD in the standby mode, a physical defect inside the IC can be detected.
[0022]
Sub-threshold current when thresholds of N-channel MOSFET and P-channel MOSFET are set to 0.5 V and -0.5 V, respectively, in an IC based on CMOS technology in which 100,000 gates are integrated in a general 0.25 μm class The power supply current IDD is about 100 nA to 10 μA. On the other hand, the short-circuit current that flows when there is an abnormality inside the IC, for example, when there is a short circuit between wirings, is as large as about 100 μA to 10 mA. Since this short current is superimposed on the power supply current IDD, it is possible to easily detect whether or not an abnormality has occurred in the IC by measuring the current value of the power supply current IDD.
[0023]
Compared to conventional logical function tests and function tests that check the logic output value of an IC against the input of a logical test pattern string, the IDDQ test has a higher defect detection rate when detecting defects inside the IC. The time can be shortened and the test cost can be reduced. In particular, the effect of using the IDDQ test is tremendous in consideration of a significant increase in the integration scale of logic gate circuits in an IC accompanying the miniaturization of the IC manufacturing process.
[0024]
Here, the reason why the above IDDQ test cannot be applied to an IC using MTCMOS technology will be described.
[0025]
In the operation mode, the P-channel type MOSFET and the N-channel type MOSFET as switches are made conductive, and the high-potential side power supply voltage and the low-potential side power supply voltage are respectively applied to the high potential side pseudo power supply voltage line and the low potential side pseudo power supply voltage line Supply. For this reason, since the logic gate circuit in the IC is in a state in which logic operation is possible, the output voltage of each logic gate circuit can be set to a high voltage level or a low voltage level. However, since the logic gate circuit of the IC using the MTCMOS technology is configured using a MOSFET having a low threshold voltage, the subthreshold leakage current in each MOSFET becomes large. For this reason, even when the logic operation is not performed, the power supply current IDD in the entire IC becomes considerably large.
[0026]
For example, in an IC based on a CMOS technology in which 100,000 gates are integrated in a general 0.25 μm class, the threshold value of an N channel MOSFET and a P channel MOSFET is set to 0.2 V and −0.2 V, respectively. The power source current IDD due to the threshold current is about 100 μA to 10 mA. For this reason, even if some logic gate circuits have defects such as a short circuit between wirings, the short leakage current due to this is about 100 μA to 10 mA, and even if this short current is superimposed on the power supply current IDD, The short current is hidden behind the power supply current due to the subthreshold leakage current. For this reason, it is extremely difficult or impossible to detect a defect by measuring the power supply current IDD.
[0027]
In the standby mode, the P-channel MOSFET and the N-channel MOSFET serving as switches are brought into a non-conducting state. For this reason, since the high-potential-side power supply voltage and the low-potential-side power supply voltage are not supplied to the logic gate circuit in the IC, even if the logic gate circuit is defective, it cannot be detected from the power supply current IDD.
[0028]
As described above, for the IC using the MTCMOS technology, in the operation mode, the power supply current IDD based on the subthreshold leakage current is configured using a MOSFET having a general high threshold voltage. Compared with an IC having a logic gate circuit, it becomes larger and it becomes difficult or impossible to detect a defect in the logic gate circuit. In the standby mode, a failure of the logic gate circuit cannot be detected from the power supply current IDD.
[0029]
As described above, the IDDQ test cannot be applied to an IC using MTCMOS technology, particularly an IC having a large integration scale of logic gate circuits. As a result, it becomes necessary to add a huge amount of function tests in order to reduce the defect detection rate at the time of mass production and shipment test of the product or increase the defect detection rate, resulting in an increase in test time and test cost. It will be.
[0030]
In view of the above problems, an object of the present invention is to provide a semiconductor integrated circuit capable of improving a defect detection rate.
[0031]
Another object of the present invention is to provide a semiconductor integrated circuit capable of realizing the above object by minimizing an increase in the chip size of the semiconductor integrated circuit.
[0032]
Another object of the present invention is to provide a semiconductor integrated circuit testing method capable of improving the defect detection rate without increasing test time and test cost.
[0033]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor integrated circuit according to the present invention includes a first power supply line to which a first power supply voltage is supplied, a gate electrode, first and second electrodes, and the first electrode Is connected to the first power supply line and has a first conductivity type first MOS transistor having a first threshold value and a second MOS transistor connected to the second electrode of the first MOS transistor. One pseudo power supply line and at least one second conductivity type second MOS transistor having a second threshold lower than the first threshold, and the first pseudo power supply line Is supplied with one power supply voltage, an internal logic circuit to which a clock signal is input, a first terminal capable of receiving a test signal, and a logic level of the test signal received at the first terminal. At a predetermined logic level indicating a test, the second A voltage supply circuit for supplying a voltage for increasing a threshold value of the second MOS transistor to a substrate terminal of the OS transistor, and the logic level of the test signal is a predetermined logic level for instructing a test. In this case, the input of the clock signal to the internal logic circuit is prohibited.
[0034]
The semiconductor integrated circuit according to the present invention includes a first power supply line to which a first power supply voltage is supplied, and a second power supply line to which a second power supply voltage different from the first power supply voltage is supplied. , Having a first threshold value, and having a first threshold value, wherein the first electrode is connected to the first power supply line. A second conductivity type third transistor having a third threshold voltage and having a transistor, a gate electrode, first and second electrodes, and the first electrode connected to the second power supply line; A first pseudo power supply line connected to the second electrode of the first MOS transistor, and the second electrode of the third MOS transistor to the internal logic circuit. A second pseudo power supply line for supplying the other power supply voltage, and a second signal lower than the first threshold value. At least one first conductivity type second MOS transistor having a large value and at least one second conductivity type fourth MOS transistor having a fourth threshold value lower than the third threshold value. An internal logic circuit to which a clock signal is input, wherein one power supply voltage is supplied from the first pseudo power supply line and the other power supply voltage is supplied from the second pseudo power supply line. A first terminal capable of receiving a test signal, and a substrate terminal of the second MOS transistor when the logic level of the test signal received at the first terminal is a predetermined logic level for instructing a test. Is supplied with a first predetermined voltage for raising the threshold voltage of the second MOS transistor, and the fourth MOS transistor is connected to the substrate terminal of the fourth MOS transistor. And a voltage supply circuit for supplying a second predetermined voltage for increasing the threshold value of the data, and when the logic level of the test signal is a predetermined logic level for instructing a test, to the internal logic circuit The input of the clock signal is prohibited.
[0035]
In the semiconductor integrated circuit of the present invention, the second terminal and the fourth terminal may be electrically connected by wire bonding connection.
[0036]
In the semiconductor integrated circuit of the present invention, the first terminal and the third terminal may be electrically connected by wire bonding connection.
[0037]
The semiconductor integrated circuit of the present invention has a third terminal connected to the first power supply line and a fourth terminal connected to the second power supply line, and the semiconductor integrated circuit is made of resin. In the sealed state, the first terminal and the third terminal may be connected by wire bonding, and the second terminal and the fourth terminal may be connected by wire bonding.
[0038]
In the semiconductor integrated circuit test method of the present invention, the first power supply voltage is supplied to the first power supply line, the first MOS transistor is turned on, and the first terminal is used. After a voltage for increasing the threshold value of the second MOS transistor is supplied to the substrate terminal of the second MOS transistor, the current value flowing through the internal logic circuit is measured.
[0039]
In the semiconductor integrated circuit testing method of the present invention, the first power supply voltage is supplied to the first power supply line, and the second power supply voltage is supplied to the second power supply line. And a voltage for increasing the threshold value of the second MOS transistor, using the first terminal, with the third MOS transistor in a conductive state, to the substrate terminal of the second MOS transistor. The second terminal is used to supply a voltage for increasing the threshold value of the fourth MOS transistor to the substrate terminal of the fourth MOS transistor, and then the value of the current flowing through the internal logic circuit is determined. Measure.
[0040]
DETAILED DESCRIPTION OF THE INVENTION
A semiconductor integrated circuit and a test method thereof according to the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the main part of the semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 1 shows an IC to which an MTCMOS technology using two types of MOSFETs having different threshold voltages in a P-channel MOSFET (hereinafter referred to as PMOS) and an N-channel MOSFET (hereinafter referred to as NMOS) is applied. is there. In the following description, unless otherwise specified, the threshold voltage Vt of a MOSFET is a value when the substrate-source voltage Vbs of the MOSFET is 0V. In addition, the IC in each embodiment is formed on a silicon substrate.
[0041]
1 includes a high potential side power supply line (hereinafter referred to as VDD line) 101 supplied with a high potential side power supply voltage, and a low potential side power supply line (hereinafter referred to as VSS line) supplied with a low potential side power supply voltage. 102), a high potential side pseudo power supply line (hereinafter referred to as VDDV line) 103, and a low potential side pseudo power supply line (hereinafter referred to as VSSV line) 104. Further, as shown in FIG. 1, one electrode is connected to the VDD line 101, the other electrode is connected to the VDDV line 103, and one electrode is connected to the VSS line 102, and the VSSV line 104 is connected to It has an NMOS 121 to which the other electrode is connected.
[0042]
Here, the PMOS 111 and the NMOS 121 have high threshold voltages. The threshold voltage Vt of the PMOS 111 is, for example, −0.5V, and the threshold voltage Vt of the NMOS 121 is, for example, 0.5V.
[0043]
A control signal SL is input to the gate electrode of the PMOS 111, and an inverted logic signal SL having a voltage level complementary to the voltage level of the control signal SL is input to the gate electrode of the NMOS 121. That is, when the voltage level of the control signal SL is high (at least a voltage level exceeding the threshold voltage Vt), the PMOS 111 and the NMOS 121 are turned on. For this reason, the VDD line 101 and the VDDV line 103 are electrically connected, and the VSS line 102 and the VSSV line 104 are electrically connected. When the voltage level of the control signal SL is low (at least a voltage level that does not exceed the threshold voltage Vt), the PMOS 111 and the NMOS 121 are turned off. For this reason, the VDD line 101 and the VDDV line 103 are disconnected from each other, and the VSS line 102 and the VSSV line 104 are disconnected from each other. That is, the PMOS 111 functions as a switch on the high potential side, and the NMOS 121 functions as a switch on the low potential side.
[0044]
FIG. 1 shows a CMOS logic gate circuit (hereinafter referred to as a logic gate circuit) 105 connected to the VDDV line 103 and the VSSV line 104, respectively. The logic gate circuit 105 is supplied with the high potential side power supply voltage from the VDDV line 103 and is supplied with the low potential side power supply voltage from the VSSV line 104.
[0045]
The logic gate circuit 105 in FIG. 1 is configured by PMOSs 131 to 133 having a low threshold voltage and NMOSs 141 to 143 having a low threshold voltage. In FIG. 1, for example, PMOS 131 and 132 are connected in parallel, NMOS 141 and 142 are connected in cascade, and one electrode of each of PMOS 131 and 132 is connected to one electrode of NMOS 141, and PMOS 133 and NMOS 143 are connected in cascade. The circuit is shown. The other electrode of each of the PMOSs 131, 132, and 133 is connected to the VDDV line 103, and one electrode of each of the NMOSs 142 and 143 is connected to the VSSV line 104.
[0046]
Wiring of input signals to the gate electrodes of PMOS and NMOS constituting the logic gate circuit 105 is omitted. For example, output signal wirings of other logic gate circuits and signals from external input terminals are connected to these gate electrodes. Wiring is connected. For example, if the same input signal is input to the gate electrode of the PMOS 131 and the gate electrode of the NMOS 141 and the same input signal is input to the gate electrode of the PMOS 132 and the gate electrode of the NMOS 142, the PMOS 131, 132 and the NMOS 141, 142 can operate as a NAND gate. It becomes. The PMOS 133 and the NMOS 143 can operate as an inverter.
[0047]
The logic gate circuit 105 is not limited to this circuit configuration, and various changes can be made. In an actual IC, a large number of other logic gate circuits are arranged in the logic gate circuit 105. Here, for simplification of the drawings and description, the PMOSs 131 to 133 and the NMOSs 141 to 143 are arranged. Only the 6 elements are shown.
[0048]
Here, as described above, the PMOSs 131 to 133 and the NMOSs 141 to 143 have low threshold voltages. The threshold voltage Vt of the PMOSs 131 to 133 is, for example, −0.2V, and the threshold voltage Vt of the NMOSs 141 to 143 is, for example, 0.2V. In the PMOS, the threshold voltage Vt of the PMOS 111 is set to −0.5 V. Therefore, the threshold voltage Vt of the PMOSs 131 to 133 seems to be higher when compared with only the numerical value, but the threshold is high. As the width of the boundary value in which the value voltage means that the PMOS can be in a conductive state, the threshold voltage Vt of the PMOS 131 to 133 is lower when viewed as the absolute value of the numerical value.
[0049]
Capacitors 151 and 152 in FIG. 1 illustrate the capacitances that the VDDV line 103 and the VSSV line 104 have with other voltage terminals, wirings, and substrates, respectively. The capacitors 151 and 152 are used to stabilize the electrostatic capacitance added parasitically to the VDDV line 103 and the VSSV line 104 and the voltage values of the VDDV line 103 and the VSSV line 104, respectively, in the operation mode. The capacity of the capacitive element that is intentionally connected is included.
[0050]
Here, when each of the PMOS 111 and the PMOS 131 to 133 which are the high potential side switches is viewed as a four-terminal element having drain, gate, source and substrate terminals, the substrate terminals of these PMOSs are connected to the semiconductor substrate. It is connected to a high potential substrate power supply line (hereinafter referred to as VDDS line) 106 via the formed N-type well layer or N-type semiconductor substrate (in the case of an IC using the N-type semiconductor substrate). The VDDS line 106 is a power supply line independent of the VDD line 101 and the VDDV line 103 on the semiconductor substrate.
[0051]
Similarly, when the NMOS 121 and the NMOSs 141 to 143 that are low potential side switches are viewed as four-terminal elements having drain, gate, source, and substrate terminals, these NMOS substrate terminals are connected to the semiconductor substrate. It is connected to a low-potential-side substrate power supply line (hereinafter referred to as a VSSS line) 107 via the formed P-type well layer or P-type semiconductor substrate (in the case of an IC using a P-type semiconductor substrate). The VSSS line 107 is a power supply line independent of the VSS line 102 and the VSSV line 104 on the semiconductor substrate.
[0052]
The pad 161 shown in FIG. 1 is a terminal provided on the semiconductor substrate for supplying the high potential side power supply voltage VDD from the outside of the IC, and the pad 162 supplies the low potential side power supply voltage VSS from the outside of the IC. Therefore, it is a terminal provided on the semiconductor substrate. The pad 161 is connected to the VDD line 101, and the pad 162 is connected to the VSS line 102. These pads 161 and 162 are generally called power supply pads.
[0053]
The pad 163 shown in FIG. 1 is a terminal for supplying a substrate voltage to the substrate terminals of the PMOS 111 and 131 to 133 via the VDDS line 106, and the pad 164 is connected to the NMOS 121, via the VSSS line 107. It is a terminal for supplying a substrate voltage to each of the substrate terminals 141 to 143. Both pads 163 and 164 are provided on the semiconductor substrate.
[0054]
As described above, in the IC shown in FIG. 1, the PMOS substrate terminal constituting the IC is disconnected from the VDD line 101, and the voltage supplied to the substrate terminal can be supplied from the outside using the pad 163, for example. It is said. Similarly, the NMOS substrate terminal constituting the IC is disconnected from the VSS line 102, and the voltage supplied to the substrate terminal can be supplied from the outside using the pad 164, for example. Next, the operation of the IC in FIG. 1 will be described below.
[0055]
In the logical function test or function test at the time of mass-production shipping test of the product, and in actual use after the shipping test, the high-potential side power supply voltage VDD is applied to the pad 163 in the same manner as the pad 161, and the pad 164 Similarly to 162, the low potential side power supply voltage VSS is applied. Thereby, the IC of FIG. 1 can logically operate as a normal IC using the MTCMOS technology.
[0056]
That is, in the operation mode, the PMOS 111 and the NMOS 121 are both brought into conduction by setting the voltage level of the control signal SL to the low potential side power supply voltage VSS level. At this time, since the PMOS 111 and the NMOS 121 have an on-resistance in the conductive state, an internal voltage drop occurs due to the power supply current consumed by the logic gate circuit 105. Here, the gate widths of the PMOS 111 and the NMOS 121 are designed to be large so that their on-resistance can be ignored. For this reason, the VDDV line 103 can be set to substantially the same potential as the VDD line 101, and the VSSV line 104 can be set to substantially the same potential as the VSS line 102. As a result, a voltage corresponding to the high potential side power supply voltage VDD and a voltage corresponding to the low potential side power supply voltage VSS are supplied to the logic gate circuit 105 from the VDDV line 103 and the VSSV line 104, respectively.
[0057]
Further, since the high potential side power supply voltage VDD is supplied to the substrate terminals of the PMOSs 131 to 133 constituting the logic gate circuit 105, and the low potential side power supply voltage VSS is supplied to the substrate terminals of the NMOSs 141 to 143, The logic gate circuit 105 can perform a logic operation.
[0058]
Here, since the PMOSs 131 to 133 and the NMOSs 141 to 143 constituting the logic gate circuit 105 have a low threshold voltage Vt, the logic gate circuit is constituted by a PMOS or NMOS having a high threshold voltage. In comparison, it is possible to operate with the power supply voltage VDD lowered while keeping the gate delay time tpd equal to or higher. In other words, the operation and function of the IC of FIG. 1 in this state is not inferior to that of an IC using the conventional MTCMOS technology.
[0059]
In the standby mode, the PMOS 111 and the NMOS 121 are both turned off by setting the voltage level of the control signal SL to the high potential side power supply voltage VDD level. Therefore, the supply of the high-potential-side power supply voltage VDD and the low-potential-side power supply voltage VSS to the logic gate circuit 105 is stopped, so that the subthreshold leakage current Ileak at this time is the non-conduction of the NMOS 111 and the PMOS 121 that constitute the switch. It is determined by the subthreshold current characteristic in the state. As described above, since the threshold voltages of the NMOS 111 and the PMOS 121 constituting the switch are high, the sub-gate is formed by the PMOS and the NMOS having the low threshold voltage even though the logic gate circuit 105 is constituted by the sub-gate. The threshold leak current Ileak can be set to a small value. In other words, the operation and function of the IC of FIG. 1 in this state is not inferior to that of the IC using the conventional MTCMOS technology.
[0060]
Next, the operation when the IDDQ test is performed on the IC of FIG. 1 during the mass production shipment test of the product will be described below.
[0061]
When the IDDQ test is performed, a voltage higher than the high potential side power supply voltage VDD, for example, a voltage of VDD + 1.0 V is applied to the pad 163. For this reason, since a voltage of VDD + 1.0V is applied to the substrate terminals of the PMOSs 111 and 131 to 133, the substrate-source voltage Vbs of each PMOS is 1.0V. Further, a voltage lower than the low potential side power supply voltage VSS, for example, a voltage of VSS−2.0 V is applied to the pad 164. For this reason, since a voltage of VSS−2.0 V is applied to the substrate terminals of the NMOSs 121 and 141 to 143, the substrate-source voltage Vbs of each NMOS becomes −2.0V.
[0062]
Here, the change in the electrical characteristics of the PMOS and NMOS when the substrate voltage as described above is applied will be described. FIG. 2 shows the substrate-source voltage at the threshold voltage Vt of the submicron class MOSFET. It is a figure which shows the general characteristic depending on Vbs. FIG. 2A shows an example of a PMOS, and FIG. 2B shows an example of an NMOS.
[0063]
As shown in FIG. 2, it can be seen that the threshold voltage Vt of the MOSFET generally varies depending on the substrate-source voltage Vbs. This is an electrical characteristic of the MOSFET known as the substrate bias effect. As shown in FIG. 2A, in the case of a PMOS, when Vbs = 0V, the substrate terminal is in two PMOSs whose threshold voltages Vt are set to −0.5V and −0.2V, respectively. By setting the substrate voltage, which is a voltage applied to, to VDD + 1.0V, that is, Vbs = 1.0V, the threshold voltages become Vt of about −0.8V and −0.5V, respectively. That is, the threshold voltage increases in the negative direction.
[0064]
Similarly, as shown in FIG. 2B, in the case of NMOS, when Vbs = 0V, two NMOSs whose threshold voltages Vt are set to 0.5V and 0.2V, respectively, are substrates. By setting the substrate voltage, which is a voltage applied to the terminal, to VDD-2.0V, that is, Vbs = -2.0V, the threshold voltages become Vt of about 0.8V and 0.5V, respectively. That is, the threshold voltage increases in the positive direction.
[0065]
As described above, in FIG. 1, the threshold voltages Vt of the PMOSs 131 to 133 constituting the logic gate circuit 105 are set to −0.2 V (where Vbs = 0 V), and the threshold voltages Vt of the NMOSs 141 to 143 are set to 0. Although the voltage is .2V (however, Vbs = 0V), the threshold voltage Vt of each MOSFET can be changed by applying an arbitrary voltage value as a substrate voltage from the pads 163 and 164. . In this embodiment, VDD + 1.0V is applied to the pad 163, and VSS−2.0V is applied to the pad 164. Therefore, the threshold voltage Vt of the PMOSs 131 to 133 constituting the logic gate 105 is set. The threshold voltage Vt of the NMOSs 141 to 143 can be set to 0.5 V, which is comparable to the high threshold voltage.
[0066]
With this setting, for example, assuming an IC in which 100,000 gates are integrated in the 0.25 μm class, the voltage level of the control signal SL is set to the low potential side power supply voltage VSS level, and both the PMOS 111 and the NMOS 121 are made conductive. Even in the operation mode, the subthreshold leakage current Ileak in the entire IC can be suppressed to about 100 nA to 10 μA. For this reason, an IDDQ test becomes possible.
[0067]
That is, with the voltage applied from the pads 163 and 164, the threshold voltage of the MOSFET of the logic gate circuit 105 is set higher than the normal state, and the level of the output voltage of each logic gate circuit in the IC is set to the high voltage level or The current value of the power supply current IDD is measured in a stable state with several patterns set to a low voltage level. By measuring the measured current value of the power supply current IDD as a current value sufficiently larger than a leak current value predicted in advance (for example, 100 nA to 10 μA), it is possible to determine the occurrence of an abnormality in the IC. In this way, by measuring the power supply current IDD, if there is an abnormality due to a short circuit between wirings in the IC, a short current of 100 μA to 10 mA is superimposed on the power supply current IDD, so that the determination of abnormality is made. Can be done easily.
[0068]
As described above, in the semiconductor integrated circuit according to the first embodiment, a substrate voltage for each PMOS and each NMOS constituting the logic gate circuit 105 can be applied from the pad 163 and the pad 164 from the outside. It is said. For this reason, a voltage that increases the threshold voltage Vt of the PMOS and NMOS having the low threshold voltage Vt that constitutes the logic gate circuit is used as the substrate voltage during the IDDQ test at the time of mass production shipment test of the product. By applying this, it is possible to easily detect an abnormality inside the IC in the IDDQ test, and it is possible to improve the defect detection rate during the mass production shipment test of the product.
[0069]
In addition, according to the present embodiment, it is not necessary to add a huge function test in order to improve the defect detection rate, so that an increase in test time and an increase in test cost can be greatly reduced. Furthermore, according to the present embodiment, in order to obtain the above effect, the VDDS line 106, the VSSS line 107, and the pads 163 and 164 are particularly provided, and the chip size of the entire IC increases. Nor. These VDDS line 106, VSSS line 107, and pads 163 and 164 can be configured by using a normal semiconductor manufacturing technique, and the manufacturing process is hardly complicated or increased.
[0070]
Next, a second embodiment will be described with reference to the drawings. FIG. 3 is a circuit diagram showing the main part of the semiconductor integrated circuit according to the second embodiment. In FIG. 3, the same components as those in FIG. Further, in the description of the configuration of FIG. 3, only portions different from those in FIG. 1 will be described.
[0071]
In FIG. 3, the substrate terminal of the PMOS 111 that is the high potential side switch is connected to the VDD line 101, and the substrate terminal of the NMOS 121 that is the low potential side switch is connected to the VSS line 102. The operation of the IC in FIG. 4 will be described below.
[0072]
In the logical function test or function test at the time of mass-production shipping test of the product, and in actual use after the shipping test, the high-potential side power supply voltage VDD is applied to the pad 163 in the same manner as the pad 161, and the pad 164 Similarly to 162, the low potential side power supply voltage VSS is applied. Thereby, the high potential side power supply voltage VDD is supplied to the substrate terminals of the PMOSs 111 and 131 to 133, and the low potential side power supply voltage VSS is supplied to the substrate terminals of the NMOSs 121 and 141 to 143. . In this case, like the IC of FIG. 1, the IC of FIG. 3 can logically operate as a normal IC using MTCMOS technology. The operation in this state is the same as that in FIG.
[0073]
Next, the operation when the IDDQ test in the IC of FIG. 3 is performed in the mass production shipment test of the product will be described below.
[0074]
During the IDDQ test, for example, a voltage of VDD + 1.0 V is applied to the pad 163 as a voltage higher than the high potential side power supply voltage VDD. For this reason, a voltage of VDD + 1.0 V is applied to the substrate terminals of the PMOSs 131 to 133 constituting the logic gate circuit 105. Therefore, since the substrate-source voltage Vbs of the PMOSs 131 to 133 constituting the logic gate circuit 105 is 1.0 V, the threshold voltage Vt is set to -0.5 V.
[0075]
Further, for example, a voltage of VSS−2.0 V is applied to the pad 164 as a voltage lower than the low potential side power supply voltage VSS. For this reason, a voltage of VSS−2.0 V is applied to the substrate terminals of the NMOSs 141 to 143 constituting the logic gate circuit 105. Accordingly, the substrate-source voltage Vbs of the NMOSs 141 to 143 constituting the logic gate circuit 105 is −2.0 V, and the threshold voltage Vt is set to 0.5 V.
[0076]
Therefore, in the second embodiment, as in the first embodiment, the threshold voltage of each PMOS and each NMOS constituting the logic gate circuit 105 can be increased during the IDDQ test. The same effects as those of the first embodiment can be obtained.
[0077]
In the second embodiment, the following effects are further obtained.
[0078]
In the first embodiment, during the IDDQ test, a substrate voltage of VDD + 1.0V is applied from the VDDS line 106 to the PMOS 111 which is the high potential side switch, and the VSS voltage from the VSSS line 107 to the PMOS 121 which is the low potential side switch. A substrate voltage of VSS-2.0V is applied. For this reason, the threshold voltage of the PMOS 111 is about −0.8V, and the threshold voltage of the NMOS 121 is about 0.8V. As a result, the internal on-resistance becomes high when the PMOS 111 and the NMOS 121 which are the switches are in the conductive state during the IDDQ test. The drain current Id in the conductive state of the MOSFET can be expressed by the following equation, where the gate-source voltage is Vgs.
Id∝ (Vgs−Vt) 2 (5)
[0079]
Here, Vgs of the PMOS 111 and the NMOS 121 in the operation mode is Vgs = VDD. Therefore, the drain current Id in the operation mode can be expressed as follows based on the equation (5).
Id∝ (VDD−Vt) 2 (6)
[0080]
As can be seen from the equation (6), when the threshold voltage Vt increases, the drain current Id decreases, in other words, the on-resistance increases. Therefore, during the IDDQ test, when the logic gate circuit 105 in the IC is operated to set each output voltage of the logic gate circuit 105 to a predetermined voltage level (high voltage level or low voltage level), the PMOS 111 and NMOS 121 The possibility of a shortage of supply current is taken into account. In this case, the voltage levels of the VDDV line 103 and the VSSV line 104 greatly fluctuate, the operation of the logic gate circuit 105 is difficult to stabilize, and it takes time to set the voltage level of the output voltage of the logic gate circuit 105 accurately. It takes. This can be dealt with by designing the gate widths of the PMOS 111 and the NMOS 121 to be larger and increasing the current supply capability, but in this case, the chip area of the IC increases.
[0081]
In the second embodiment, the substrate terminal of the PMOS 111 is connected to the VDD line 101, and the substrate terminal of the NMOS 121 is connected to the VSS line 102. For this reason, the substrate voltages of the PMOS 111 and the NMOS 121 do not change even during the IDDQ test. As a result, the current supply capability of the PMOS 111 and the NMOS 121 does not become insufficient during the IDDQ test, so that the voltage level of the output voltage of the logic gate circuit 105 can be set easily.
[0082]
Here, the structure of the IC in the first embodiment and the second embodiment will be described. FIG. 4 is a principal part sectional view showing the structure of the IC in the first embodiment, and FIG. 5 is a principal part sectional view showing the structure of the IC in the second embodiment. 4 and 5, the PMOS 131 and 132 and the NMOS 141 and 142 in the logic gate circuit 105 are omitted in order to avoid complication of the drawing. 4, components corresponding to the components in FIG. 1 are given the same reference numerals as those in FIG. 1, and in FIG. 5, components corresponding to the components in FIG. Yes.
[0083]
In FIG. 4, an N well layer 203 and a P well layer 205 are formed on a P type silicon substrate 201. In the N well layer 203, a source electrode 211 and a drain electrode 213 of the PMOS 111, and a source electrode 221 and a drain electrode 223 of the PMOS 133 are formed, respectively. On the N well layer 203, a gate electrode 215 is formed between the source electrode 211 and the drain electrode 213 of the PMOS 111 via a gate oxide film, and a gate oxide is formed between the source electrode 221 and the drain electrode 223 of the PMOS 133. A gate electrode 225 is formed through the film.
[0084]
In the P well layer 205, a source electrode 241 and a drain electrode 243 of the NMOS 121 and a source electrode 231 and a drain electrode 233 of the NMOS 143 are formed, respectively. On the P well layer 205, a gate electrode 245 is formed between the source electrode 241 and the drain electrode 243 of the NMOS 121 via a gate oxide film, and the gate oxidation is performed between the source electrode 231 and the drain electrode 233 of the NMOS 143. A gate electrode 235 is formed through the film.
[0085]
The N well layer 203 is connected to the pad 163 through the VDDS line 106. The source electrode 211 of the PMOS 111 is connected to the pad 161 via the VDD line 101. The drain electrode 213 of the PMOS 111 is connected to the source electrode 221 of the PMOS 133 via the VDDV line 103. The drain electrode 223 of the PMOS 133 is connected to the drain electrode 233 of the NMOS 143 through the wiring 207.
[0086]
The P well layer 205 is connected to the pad 164 through the VSSS line 107. The source electrode 241 of the NMOS 121 is connected to the pad 162 via the VSS line 102. The drain electrode 243 of the NMOS 121 is connected to the source electrode 231 of the NMOS 143 through the VSSV line 104.
[0087]
In FIG. 4, an N well layer 203 and a P well layer 205 correspond to substrate terminals in the PMOS and NMOS, respectively. That is, each PMOS substrate terminal is connected to the VDDS line 106, and each NMOS substrate terminal is connected to the VSSS line 107. As described above, in the IC according to the first embodiment shown in FIG. 1, each MOSFET can be formed by one N well layer and one P well layer, and can be realized by a CMOS process technology having a double well structure. is there.
[0088]
In FIG. 4, the P-type silicon substrate has been described, but the same applies to the N-type silicon substrate. In this case, the P-type silicon substrate 201 may be replaced with an N-type silicon substrate, and other components may be considered as the same.
[0089]
FIG. 5A is a diagram in which the IC of the second embodiment is configured using a P-type silicon substrate. In FIG. 5A, three N well layers 302, 303, and 304 and a P well layer 306 are formed on a P type silicon substrate 301. A source electrode 211 and a drain electrode 213 of the PMOS 111 are formed in the N well layer 302, and a source electrode 221 and a drain electrode 223 of the PMOS 133 are formed in the N well layer 303. On the N well layer 302, a gate electrode 215 is formed between the source electrode 211 and the drain electrode 213 of the PMOS 111 via a gate oxide film. On the N well layer 303, the source electrode 221 and the drain electrode 223 of the PMOS 133 are formed. In between, a gate electrode 225 is formed via a gate oxide film.
[0090]
A P well layer 305 is formed in the N well layer 304. In the P well layer 305, a source electrode 231 and a drain electrode 233 of the NMOS 143 are formed. On the P well layer 305, a gate electrode 235 is formed between the source electrode 231 and the drain electrode 233 of the NMOS 143 via a gate oxide film.
[0091]
Further, the source electrode 241 and the drain electrode 243 of the NMOS 121 are formed in the P well layer 306, respectively. On the P well layer 306, a gate electrode 245 is formed between the source electrode 241 and the drain electrode 243 of the NMOS 121 via a gate oxide film.
[0092]
The N well layer 302 and the source electrode 211 of the PMOS 111 are connected to the pad 161 via the VDD line 101. N well layer 303 is connected to pad 163 via VDDS line 106. The drain electrode 213 of the PMOS 111 is connected to the source electrode 221 of the PMOS 133 via the VDDV line 103. The drain electrode 223 of the PMOS 133 is connected to the drain electrode 233 of the NMOS 143 through the wiring 207.
[0093]
The P well layer 305 is connected to the pad 164 through the VSSS line 107. The source electrode 241 of the NMOS 143 is connected to the drain electrode 243 of the NMOS 121 via the VSSV line 104. The P well layer 306 and the source electrode 241 of the NMOS 121 are connected to the pad 162 via the VSS line 102.
[0094]
In FIG. 5A, the N well layer 304 is provided to prevent the P well layer 305 and the P well layer 306 from being electrically connected to each other through the P type silicon substrate. It is to do. Therefore, the N well layer 304 is formed so as to surround the P well layer 305. The P well layer 305 and the P well layer 306 can be electrically separated by applying a high potential side power supply voltage such as the power supply voltage VDD to the N well layer 304.
[0095]
The N well layers 302 and 303 and the P well layers 305 and 306 correspond to the substrate terminals in the PMOS and NMOS formed in the respective well layers. Therefore, a voltage different from the substrate terminal of each MOSFET of the logic gate circuit 105 can be supplied to each substrate terminal of the PMOS 111 and the NMOS 121 which are switches of the IC in the second embodiment. Therefore, the IC of the second embodiment can be realized by adopting a well structure as shown in FIG. Such a well structure is called a triple well structure, and the IC of the second embodiment can be realized by the CMOS process technology of the triple well structure.
[0096]
FIG. 5B is a diagram in which the IC of the second embodiment is configured using an N-type silicon substrate. In FIG. 5B, three P well layers 404, 405, 406 and an N well layer 402 are formed on an N type silicon substrate 401. A source electrode 211 and a drain electrode 213 of the PMOS 111 are formed in the N well layer 402, and an N well layer 403 is formed in the P well layer 404. A source electrode 221 and a drain electrode 223 of the PMOS 133 are formed in the N well layer 403. On the N well layer 402, a gate electrode 215 is formed between the source electrode 211 and the drain electrode 213 of the PMOS 111 via a gate oxide film. On the N well layer 403, the source electrode 221 and the drain electrode 223 of the PMOS 133 are formed. In between, a gate electrode 225 is formed via a gate oxide film.
[0097]
In the P well layer 405, the source electrode 231 and the drain electrode 233 of the NMOS 143 are formed. On the P well layer 405, a gate electrode 235 is formed between the source electrode 231 and the drain electrode 233 of the NMOS 143 via a gate oxide film.
[0098]
Further, the source electrode 241 and the drain electrode 243 of the NMOS 121 are formed in the P well layer 406, respectively. On the P well layer 406, a gate electrode 245 is formed between the source electrode 241 and the drain electrode 243 of the NMOS 121 via a gate oxide film.
[0099]
The N well layer 402 and the source electrode 211 of the PMOS 111 are connected to the pad 161 through the VDD line 101. The N well layer 403 is connected to the pad 163 through the VDDS line 106. The drain electrode 213 of the PMOS 111 is connected to the source electrode 221 of the PMOS 133 via the VDDV line 103. The drain electrode 223 of the PMOS 133 is connected to the drain electrode 233 of the NMOS 143 through the wiring 207.
[0100]
The P well layer 405 is connected to the pad 164 through the VSSS line 107. The source electrode 231 of the NMOS 143 is connected to the drain electrode 243 of the NMOS 121 via the VSSV line 104. The P well layer 406 and the source electrode 241 of the NMOS 121 are connected to the pad 162 via the VSS line 102.
[0101]
In FIG. 5B, the P well layer 404 is provided because the N well layer 402 and the N well layer 403 are electrically connected to each other through the N type silicon substrate 401. This is to prevent it. Therefore, the P well layer 404 is formed so as to surround the N well layer 403. By applying a low-potential-side power supply voltage such as the power supply voltage VSS to the P well layer 404, the N well layer 402 and the N well layer 403 can be electrically separated.
[0102]
The N well layers 402 and 403 and the P well layers 405 and 406 correspond to substrate terminals in the PMOS and NMOS formed in the respective well layers. Therefore, a voltage different from the substrate terminal of each MOSFET of the logic gate circuit 105 can be supplied to each substrate terminal of the PMOS 111 and the NMOS 121 which are switches of the IC in the second embodiment. Therefore, the IC of the second embodiment can be realized by using a well structure as shown in FIG. 5B even if an N-type silicon substrate is used.
[0103]
Next, a third embodiment will be described with reference to the drawings. FIG. 6 is a circuit diagram showing the main part of the semiconductor integrated circuit according to the third embodiment. In FIG. 6, the same components as those in FIG. Further, in the description of the configuration of FIG. 6, only portions different from those in FIG. 1 will be described.
[0104]
In FIG. 6, a pad 165 for connection to the VDDS line 106 is provided on the VDD line 101 so that the VDDS line 106 and the VDD line 101 can be connected to the IC of FIG. In addition, a pad 166 for connection to the VSSSS line 107 is provided on the VSS line 102 so that the VSSSS line 107 and the VSS line 102 can be connected in a later process. The term “post-process” as used herein refers to a non-defective product obtained by performing a probing test or the like after completion of a manufacturing process step (generally referred to as a wafer process step) for forming an element on a silicon substrate. It refers to an assembly process (generally referred to as an assembly process) for scribing, wire bonding, and packaging the determined chip. FIG. 6 shows a state in which the pad 163 is wire-bonded to the pad 165 with a wire 167 and the pad 164 is wire-bonded to the pad 166 with a wire 168.
[0105]
Before the pad 163 and the pad 165 and the pad 164 and the pad 166 are connected by the wire 167 and the wire 168, respectively, the state is the same as in the first embodiment. For this reason, the same operation and effect as those of the first embodiment can be expected. That is, an IDDQ test or the like can be performed as in the first embodiment.
[0106]
After a mass production shipment test of a product such as an IDDQ test, the pads 163 and 165 and the pads 164 and 166 are wire-bonded by wires 167 and 168, respectively, in a later process. For this reason, as the external terminals as the IC, the pads 163 and 165 may be one external terminal that receives the power supply voltage VDD from the outside, and the pads 164 and 166 may be one external terminal that receives the ground voltage VSS from the outside. . Therefore, since external terminals as ICs are not added according to the addition of the pads 163 and 164, the number of external terminals as ICs can be the same as that to which the present invention is not applied.
[0107]
Therefore, according to the third embodiment, the same effects as those of the first embodiment can be obtained, and an increase in the number of IC terminals can be prevented, so that the ease of use as an IC product is impaired. In addition, there is no increase in package material costs. Further, the features of the third embodiment can be applied to the IC of the second embodiment.
[0108]
Next, a fourth embodiment will be described with reference to the drawings. FIG. 7 is a circuit diagram showing the main part of the semiconductor integrated circuit according to the fourth embodiment. In FIG. 7, the same components as those in FIG. 1 are denoted by the same reference numerals. Further, in the description of the configuration of FIG. 7, only portions different from those in FIG. 1 will be described.
[0109]
7, a voltage generation circuit 201 that generates a substrate voltage of each MOSFET constituting the logic gate circuit 105 is provided in place of the pads 163 and 164 in the circuit of FIG. 1. Along with the provision of the voltage generation circuit 201, a pad 205, an NMOS 203, and a PMOS 207 are also provided. The other components in FIG. 7 are the same as in FIG.
[0110]
A signal input to the pad 205, for example, a test signal instructing a test such as an IDDQ test is input to the voltage generation circuit 201 through the wiring 213. Further, the clock signal CK is input to the voltage generation circuit 201 through the NMOS 203 when the NMOS 203 is in a conductive state. The gate electrode of the NMOS 203 is connected to the pad 205. The PMOS 207 transmits the clock signal CK to the inside of the IC, for example, the logic gate circuit 105 when in the conductive state. The gate electrode of the PMOS 207 is connected to the pad 205.
[0111]
That is, when a test signal having a voltage of the high potential side power supply voltage VDD level is input from the pad 205, the PMOS 207 is turned off and the NMOS 203 is turned on. Therefore, since the clock signal CK is not transferred to the logic gate circuit 105, the level of the output voltage of the logic gate circuit 105 can be fixed. Further, the clock signal CK is supplied to the voltage generation circuit 201 to generate a substrate voltage for increasing the threshold voltage of each MOSFET constituting the logic gate circuit 105, and this is applied to the VDDS line 106 and the VSSS line 107. introduce. Therefore, the IDDQ test can be performed as in the first embodiment.
[0112]
When a test signal having a voltage of the low potential side power supply voltage VSS level is input from the pad 205, the PMOS 207 is turned on and the NMOS 203 is turned off. For this reason, the clock signal CK is transferred to the logic gate circuit 105. In addition, since the clock signal CK is not supplied to the voltage generation circuit 201, a substrate voltage is generated to keep the threshold voltage of each MOSFET constituting the logic gate circuit 105 in a low state, and this voltage is generated as the VDDS line 106, VSSS. Transmit to line 107. Therefore, as in the first embodiment, the logic gate circuit 105 can perform a logic operation, and the IC as a whole can perform a normal operation.
[0113]
Here, the configuration of the voltage generation circuit 201 will be described with reference to the drawings. FIG. 8 is a circuit diagram of the voltage generation circuit 201.
[0114]
As shown in FIG. 8, the voltage generation circuit 201 includes a 2-input / 1-output NAND gate 221, an inverter 221, capacitors 223 and 224, and NMOSs 225 to 228. A clock signal CK and a signal (for example, a test signal) input from the pad 205 are input to the two input terminals of the NAND gate 221 via the wiring 211 and the wiring 213. The output terminal of the NAND gate 221 is connected to the input terminal of the inverter 222. The output terminal of the inverter 222 is connected to one electrode of each of the capacitors 223 and 224. It is assumed that the NMOSs 225 to 228 constituting the voltage generation circuit 201 have a high threshold voltage like the NMOS 121, and the substrate terminals of the NMOSs 225 to 228 are connected to the VSS line 102.
[0115]
The other electrode of the capacitor 223 is connected to one electrode of each of the NMOSs 225 and 227. The high-potential-side power supply voltage VDD is supplied to the gate electrode and the other electrode of the NMOS 225. The gate electrode of the NMOS 227 is connected to the other electrode of the capacitor 223. The other electrode of the NMOS 227 is connected to the VDDS line 106.
[0116]
The other electrode of the capacitor 224 is connected to one electrode of each of the NMOSs 226 and 228. The gate electrode of the NMOS 226 is connected to the other electrode of the capacitor 223. The low potential side power supply voltage VSS is supplied to the other electrode of the NMOS 226. The gate electrode and the other electrode of the NMOS 228 are connected to the VSSS line 107.
[0117]
When the voltage generation circuit 201 connected in this way receives a test signal whose voltage level is the low potential side power supply voltage VSS level from the pad 205, the voltage level of the output signal of the NAND gate 221 is the high potential side power supply voltage. Fixed to the VDD level. Therefore, the high potential side power supply voltage VDD is supplied to the VDDS line 106 via the conductive NMOSs 225 and 227, and the low potential side power supply is supplied to the VSSS line 107 via the conductive NMOSs 226 and 228. The voltage VSS is supplied. For this reason, as described above, the threshold voltage of each MOSFET of the logic gate circuit 105 is maintained at a low state, the logic gate circuit 105 can perform a logic operation, and the IC as a whole can perform a normal operation.
[0118]
When a test signal whose voltage level is the high potential side power supply voltage VDD level is input from the pad 205, the voltage level of the output signal of the NAND gate 221 depends on the voltage level of the clock signal CK transmitted from the wiring 211. It will be. The output signal of the NAND gate 221 is shaped by the inverter 222 and transmitted to one electrode of the capacitors 223 and 224. Capacitors 223 and 224 repeatedly charge and discharge according to the output signal of the inverter 222. Based on the operation of this capacitor, the VDDS line 106 is supplied with a voltage higher than the high-potential-side power supply voltage VDD supplied through the NMOSs 225 and 227 in the conductive state, for example, VDD + 1.0V. A voltage lower than the low-potential-side power supply voltage VSS supplied through the NMOSs 226 and 228 in a conductive state, for example, VSS-2.0 V is supplied to 107. For this reason, as described above, the threshold voltage of each MOSFET of the logic gate circuit 105 can be increased, and the IDDQ test can be executed.
[0119]
As described above, according to the fourth embodiment, the effect of the first embodiment can be obtained, and a signal having a voltage level of the high potential side power supply voltage VDD level or the low potential side power supply voltage VSS level is padded. By inputting from 205, the substrate voltage of each MOSFET constituting the logic gate circuit 105 can be changed. As a result, it is necessary to input a substrate voltage that increases the threshold voltage of each MOSFET constituting the logic gate circuit 105 outside the IC, or such a substrate voltage is generated outside the IC. There is no need to provide a circuit.
[0120]
Further, when the IC of FIG. 7 is resin-sealed, if an external lead corresponding to the pad 205 and connected to the pad 205 so that a test signal from the outside can be input is provided, Even after the packaging, the IDDQ test can be performed as necessary, so that the usability becomes higher. If the IC has a circuit capable of generating a test signal as described above, the number of external terminals can be increased if the test signal output from the test signal generation circuit is input to the pad 205. It can be expected to disappear.
[0121]
If the VSS line 102 is provided with a pad 166 shown in FIG. 6, the number of external terminals can be increased by wire bonding the pad 166 and the pad 205 when the IC of FIG. 7 is sealed with resin. It is also possible to make it possible to operate only as a normal IC without increasing. Although the NMOS 203 is not necessarily provided, in this embodiment, the voltage generation circuit 201 can perform more reliable operation by not supplying the clock signal CK to the NAND gate 221 of the voltage generation circuit 201. , NMOS 203 is provided. Note that the features of the fourth embodiment can also be applied to the IC of the second embodiment.
[0122]
As described above, in the first, second, third, and fourth embodiments, the PMOS 111 having the high threshold voltage is provided between the VDD line 101 and the VDDV line 103, and the VSS line 102 and the VSSV line 104 are The case where the present invention is applied to an IC using the MTCMOS technology in which the NMOS 121 having a high threshold voltage between them and the logic gate circuit 105 is composed of a MOSFET having a low threshold voltage has been described. . However, in the MTCMOS technology, there is no problem even if the PMOS 111 or the NMOS 121 is omitted.
[0123]
For example, FIGS. 9 and 10 show modifications of the IC according to the second embodiment. In the IC of FIG. 9, the NMOS 121 and the VSSV line 104 are deleted from the IC of FIG. 3 which is the second embodiment. In addition, the VSS line 102 is directly connected to the logic gate circuit 105 instead of the VSSV line 104. In the MTCMOS technology, if a power switch of at least one MOSFET having a high threshold voltage corresponding to the PMOS 111 or the NMOS 121 is provided between the VDD line 101 and the VSS line 102, the sub-mode in the standby mode can be obtained. Since the threshold leakage current can be reduced, it can be understood that the configuration of FIG. 9 may be used. For this reason, even if there exists a structure like FIG. 9, the effect similar to 2nd Embodiment can be anticipated.
[0124]
Similarly, in the IC of FIG. 10, the PMOS 111 and the VDDV line 103 are deleted from the IC of FIG. 3 which is the second embodiment. Further, the VDD line 101 is directly connected to the logic gate circuit 105 instead of the VDDV line 103. Also in the configuration of FIG. 10, the same effect as that of the second embodiment can be expected.
[0125]
The configuration in which PMOS 111 or NMOS 121 is omitted as described in FIG. 9 or 10 is not limited to the second embodiment, but is combined with any of the first, third, or fourth embodiments. Applicable.
[0126]
As mentioned above, although each embodiment was described in detail, this invention is not limited to said structure.
[0127]
For example, the circuit configuration of the logic gate circuit 105 is not limited to that described in the above embodiments. That is, the logic gate circuit 105 may include not only a low threshold voltage MOSFET but also a high threshold voltage MOSFET. This is because the logic gate circuit 105 may include a MOSFET having a high threshold voltage, particularly in a circuit that does not require high speed by shortening the delay time. . Even in an IC having such a logic gate circuit 105, the effect of the present invention can be obtained by applying the configuration of the present invention so that the threshold voltage of a MOSFET having a low threshold voltage can be increased. Can be obtained.
[0128]
As described above, various modifications can be made without departing from the scope of the present invention.
[0129]
【The invention's effect】
As described above in detail, according to the present invention, a semiconductor integrated circuit capable of improving the defect detection rate can be provided.
[0130]
Further, according to the present invention, it is possible to provide a semiconductor integrated circuit capable of reducing the increase in chip size of the semiconductor integrated circuit as much as possible and improving the defect detection rate.
[0131]
Furthermore, according to the present invention, it is possible to provide a test method for a semiconductor integrated circuit capable of improving the defect detection rate without increasing the test time and test cost.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a main part of a semiconductor integrated circuit according to a first embodiment of the present invention.
FIG. 2 is a diagram showing general characteristics depending on a substrate-source voltage Vbs at a threshold voltage Vt of a MOSFET.
FIG. 3 is a circuit diagram showing a main part of a semiconductor integrated circuit according to a second embodiment of the present invention.
FIG. 4 is a fragmentary cross-sectional view showing the structure of the semiconductor integrated circuit according to the first embodiment;
FIG. 5 is a fragmentary cross-sectional view showing a structure of a semiconductor integrated circuit according to a second embodiment;
FIG. 6 is a circuit diagram showing a main part of a semiconductor integrated circuit according to a third embodiment of the present invention.
FIG. 7 is a circuit diagram showing a main part of a semiconductor integrated circuit according to a fourth embodiment of the present invention.
8 is a circuit diagram of the voltage generation circuit in FIG. 7. FIG.
FIG. 9 is a modification of the semiconductor integrated circuit according to the second embodiment.
FIG. 10 is a modification of the semiconductor integrated circuit according to the second embodiment.
[Explanation of symbols]
101 High-potential side power supply voltage line
102 Low-potential side power supply voltage line
103 High-potential side pseudo power supply voltage line
104 Low potential side pseudo power supply voltage line
105 logic gate circuit
106 High-potential side substrate power line
107 Low-potential side substrate power line
111 High-potential power switch
121 Low-potential power switch
151, 152 capacity
161, 162, 163, 164, 165, 166, 205 pads
131, 132, 133 P-channel MOSFET
141, 142, 143 N-channel MOSFET
201 Voltage generation circuit
203 N-channel MOSFET
207 P-channel MOSFET

Claims (10)

In a semiconductor integrated circuit configured by integrating a plurality of first conductivity type MOS transistors and a plurality of second conductivity type MOS transistors,
A first power supply line to which a first power supply voltage is supplied;
A first conductivity type first MOS transistor having a first threshold value, having a gate electrode, first and second electrodes, and the first electrode connected to the first power supply line When,
A first pseudo power supply line connected to the second electrode of the first MOS transistor;
A first MOS transistor having at least one first conductivity type second MOS transistor having a second threshold value lower than the first threshold value, and the first power supply voltage from the first pseudo power supply line; in which a voltage based on the supplied, and an internal logic circuit to which a clock signal is input,
A first terminal capable of receiving a test signal;
In the first MOS transistor is conductive, in response to the test signal of a predetermined logic level to indicate the test to the first terminal is input, the substrate terminal of the second MOS transistor A voltage supply circuit for supplying a voltage for increasing the threshold value of the second MOS transistor;
The a, according to the predetermined logic level of the test signal, the semiconductor integrated circuit, characterized in that the input of the clock signal to the internal logic circuit is disabled. In a semiconductor integrated circuit configured by integrating a plurality of first conductivity type MOS transistors and a plurality of second conductivity type MOS transistors,
A first power supply line to which a first power supply voltage is supplied;
A second power supply line to which a second power supply voltage different from the first power supply voltage is supplied;
A first MOS transistor of a first conductivity type having a gate electrode, a first electrode and a second electrode, the first electrode being connected to the first power supply line and having a first threshold value; ,
A second MOS transistor of the second conductivity type having a third threshold voltage, having a gate electrode, first and second electrodes, the first electrode being connected to the second power supply line When,
A first pseudo power supply line connected to the second electrode of the first MOS transistor;
A second pseudo power supply line connected to the second electrode of the third MOS transistor;
At least one second MOS transistor of the first conductivity type having a second threshold lower than the first threshold and at least one having a fourth threshold lower than the third threshold. One second power supply voltage based on the first power supply voltage is supplied from the first pseudo power supply line, and is supplied from the second pseudo power supply line. An internal logic circuit to which the other power supply voltage based on the second power supply voltage is supplied and to which a clock signal is input;
A first terminal capable of receiving a test signal;
The substrate of the second MOS transistor in response to the test signal having a predetermined logic level instructing the test being input to the first terminal while the first and third MOS transistors are in the conductive state. A first predetermined voltage for increasing the threshold value of the second MOS transistor is supplied to the terminal, and the threshold value of the fourth MOS transistor is increased to the substrate terminal of the fourth MOS transistor. A voltage supply circuit for supplying a second predetermined voltage;
A semiconductor integrated circuit, wherein input of the clock signal to the internal logic circuit is prohibited in accordance with the predetermined logic level of the test signal.   The first power supply voltage is supplied to the first power supply line, the first MOS transistor is turned on, and the threshold value of the second MOS transistor is increased using the first terminal. 2. The method for testing a semiconductor integrated circuit according to claim 1, wherein a voltage value is supplied to a substrate terminal of the second MOS transistor and then a value of a current flowing through the internal logic circuit is measured. The first power supply line is supplied to the first power supply line, the second power supply voltage is supplied to the second power supply line, and the first and third MOS transistors are turned on. Using the first terminal, a voltage for increasing the threshold value of the second MOS transistor is applied to the substrate terminal of the second MOS transistor, and the fourth MOS is used using the second terminal. 3. The semiconductor device according to claim 2 , wherein a voltage value for increasing a threshold value of the transistor is supplied to a substrate terminal of the fourth MOS transistor, and then a current value flowing through the internal logic circuit is measured. Integrated circuit testing method. The voltage supply circuit is supplied with the clock signal in response to the test signal having a predetermined logic level instructing the test being input to the first terminal, whereby the second MOS transistor 2. The semiconductor integrated circuit according to claim 1, wherein a voltage for increasing the threshold value is generated. The voltage supply circuit, by pre-Symbol the test signal with different logic level than the predetermined logic level to indicate the test to the first terminal in response to input, supply of the clock signal is stopped the semiconductor integrated circuit according to claim 1 or claim 5, wherein the outputting the voltage to maintain a threshold of the second MOS transistor. The voltage supply circuit is supplied with the clock signal in response to the test signal having a predetermined logic level for instructing the test being input to the first terminal, whereby the first predetermined voltage is supplied. 3. The semiconductor integrated circuit according to claim 2, wherein the second predetermined voltage is generated. The voltage supply circuit, by pre-Symbol the test signal with different logic level than the predetermined logic level to indicate the test to the first terminal in response to input, supply of the clock signal is stopped 8. The semiconductor integrated circuit according to claim 2, wherein a voltage that maintains a threshold value of each of the second and fourth MOS transistors is output. The semiconductor integrated circuit is intended to be sealed with a resin including the first terminal, the first terminal is an external lead electrically connected to externally et the test signal is input 9. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is any one of claims 1, 2, 5, 6, 7, and 8. The semiconductor integrated circuit according to claim 1, further comprising a test signal generation circuit that generates the test signal.

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