DE2758218B2 - Electronic cash register - Google Patents

Description

The present invention relates to an electronic cash register according to the preamble of Claim 1.

In general, in an electronic cash register, an amount is entered for each commodity via an input keyboard is entered, and then a department key corresponding to the department to which the sold goods heard, operated. The entered data are processed, sorted and accumulative in Storage devices stored for adding up the sales amounts and the item quantities are trained for each department, as well as for the total amount for the day and the day in question Total sales for each employee. At the end of the working day, the register will go into a reset mode offset to successively the different ones stored in the corresponding memories Print out data, and then these memories will be cleared. These sorted Sales data are used for management purposes.

A cash register of the type mentioned at the beginning is already from the company copy: The National Cash Register Company, Dayton, Ohio, USA, Class 230-101 Electronic Cash Register, 1972 known. With the known cash register, special data can be evaluated, for example information about the Sales in certain departments, etc. However, the known cash register does not offer the possibility of provide time-dependent sales data, so that a differentiated analysis of this data is possible. It is desirable to have data available that provide precise information, for example about those who sell well Times within a given sales period. It is not with the conventional registers possible to collect such data.

The invention is based on the object of specifying a cash register of the type mentioned above, which provides more detailed sales data.

This object is achieved by the invention specified in claim 1.

In the cash register according to the invention, a sales period, for example a sales day, is in divided into several time intervals or time zones. If a registration is made, the Comparator, in which time zone the registration process

falls, and depending on this result, the registered amount is stored in such a memory location saved, which is assigned to the respective time zone. In this way, the collected data at a later date under business administration Evaluate points of view extremely efficiently. For example, the stored data provide information Sales peaks, extremely quiet business hours, etc. Such data are important for running a business extremely valuable, because decisions can be made on the basis of personal deployment certain times.

If the time function is also extended to years, months, weeks and days, a Operator pre-setting the time period for the entire amount formation, e.g. to a week, a month, or a period of two days, or the like. Accordingly, the aggregation for a period longer than a day, resulting in a substantial Improvement of the total amount of the cash register leads

Advantageous further developments of the invention emerge from the subclaims.

In the following an embodiment of the invention is explained in more detail with reference to the drawing. It shows

1 shows a keyboard of an electronic cash register,

F i g. 2A and 2B collectively show a block diagram of the entire cash register;

Fig. 3A is a circuit diagram of the circuit diagram according to FIG. 2 central unit used,

F i g. 3B is a circuit diagram showing a memory and a timer shown in FIG. 2 shows F i g. 4 a memory overview of the memory,

5A and 5B memory overviews of the time memory in the time clock,

F i g. 6A and 6B are an illustrative flow chart the mode of operation of the circuit for time counting,

F i g. 7 a data overview of the data stored in the time memory of the time clock,

F i g. 8A to 8C, data stored in the time memory and the register in time counting, and

F i g. 9A and 9B are a schematic diagram for illustrating the printing process of successive ones Numbers and dates.

Fig. 1 shows the arrangement of a keyboard 10 of an electronic cash register (ECR). The reference numeral 11 denotes amount keys for entering numerical values, such as. B. Price and quantity of goods, 12 denotes a department key for registering goods by group, 13 denotes a clear key for clearing numerical data entered through the amount key 11. A function keyboard provided with the reference number 14 consists of individual keys that represent a non-addition (#) to provide the preselected time, as well as a space key (Vo), a multiplication key (©), & °, a percent key (%), and (+) - and (-) buttons, which are used to display the increase or decrease in the percentage. Numeral 15 denotes an employee key for inputting the responsible person. A sales keyboard 16 comprises individual keys, b5 each representing receipt (Rc), payment (Pd), total net (Nt), balance sheet (Bl), no sale (NS), credit (Cr) and debit (Ch). Numeral 17 denotes a subtotal key (ST) for obtaining intermediate results in a calculation process. A balance key 18 (Ca / AMT) is used to issue a receipt in order to receive the total amount and / or the change amount. A time key 19 is used for providing the time. 19a denotes an operation key for providing an operation time segment. 19Z) provides a time range of totalization 19c designates an alarm key (AL) for providing an alarm time- The x keys 19, i to 19c represent the time keypad 19. A control lock 20 can be switched over to the operating states (OFF), (Pr ), (REG), (X) and (Z). The OFF state is used when the electronic cash register is out of order; the operating state (Pr) is used to preset data, the state (REG) is used in normal registration, the operating state (X.) is used in read operations without losing stored data; the operating state (Z) is used for resetting in order to delete data after the stored data have been read out.

The following description refers to the internal layout of the electronic cash register according to the present invention. Numeral 31 denotes an input / output controller (I / O), the the keyboard 10 and a printer part 33 controls. The I / O controller 31 supplies the keyboard 10 with a scanning signal to. When a key on the keyboard 10 is operated, the scanning signal is generated in response to the key operation is selected and supplied to the I / O controller 31 as a key input signal. After receiving the key input signal from the keyboard, the I / O controller 31 loads the key input signal into an input buffer register (not shown) to be temporarily stored herein. The printer part 33 comprises a receipt printer 36 and a single strip printer 37. Printers 36 and 37 are provided with platen 38 and 39 equipped, which are arranged coaxially and have numerical characters on their surfaces. A receipt slip 41 and a single strip 42 are densely arranged on the pressure rollers 38 and 39, respectively. Opposite to the printing rollers 38 and 39 with the receipt strip 41 and the individual strip 42 are printing hammers arranged, in front of which there are ribbons (not shown). A print position detection circuit 44 is located at one end of the platen 38 and sets the printing position of the platen 38 and 39 at certain angles of rotation of the rollers to emit detector signals. The detector signals are The I / O controller 31 is supplied through an amplifier 45 when the printing position detection signal falls and the print data together, the I / O controller 31 supplies a drive signal via a driver 35 to the Print hammer that the print type is facing at this time to drive the hammer. if the printing rollers 38 and 39 complete one revolution, the printing of one line is completed, and the Receipt strip 41 and the individual strip 42 are advanced by one line. When advancing Printing, the receipt strip 41 is fed to the outside so that the printed section is torn off after printing is finished. For example, on the receipt slip 41 »your Receipt - Thank you «. The same print data that is printed on the receipt slip 41 are on the Llinzelstreifen 42, which is from a

Wave 46 is recorded, recorded to obtain the net total. A memory 47 and a timer 38 are connected to a central processing unit (hereinafter central unit) 34. An energy source 49 is connected to both the memory 47 and the timer 48 in order to keep them always ready for use. The timer 48 is also connected to a reference frequency oscillator, which can be a crystal oscillator 50, for example. The memory 47 and the timer 48 are formed on a single chip. The central processing unit 34 generates a chip enable signal CfI to specify the memory circuit 47 and another chip select signal CE2 to specify the timer 48. A read-write sign! R / W from the memory 47 indicates the reading or writing of the memory. The time clock supplies current time data and daily data, which are read out by the central unit 34, if necessary. When a receipt is issued, the central unit reads the day information from the timer 48 in order to cause the printer section to print out the day on the receipt issued. The time data is used as time stamp data when totalizing is performed at a given point in time. The central processing unit 34 performs the receipt slip output in response to a key input signal from the keyboard. The processing data at this time are supplied as print data to the I / O controller 31 and, via a display driver 51, to a display section 24, where they are made visible.

3A and 3B together show the details of the CPU 34, the memory 47 and the timer 48. First, the CPU 34 will be explained Circuit parts controls the microprogram is stored in a read-only memory (ROM). The control section comprises output lines 63 to 66. B. a register specification signal, a transfer command, a digit shift command, and the output line 66 provides the next address itself. A timing signal from output line 64 is provided to timing circuit 68. The commands from the output line 65 are transmitted to a command decoder 69. The next address output on line 66 is transmitted to an address circuit 61 to set the next address. A timing signal from a timer signal generator 80 provided in the CPU 34 is given to the code generator circuit 67, the timer circuit 68 and the command decoder 69. The code generator circuit 67 converts, given the timing, four-bit parallel data output from the control section 62, for example, into a serial code. The output of the code generator circuit 67 is fed via a gate circuit 70 to an adder / subtracter 71.The timer circuit 68 defines the timing of the operation of the registers and their digit handling in accordance with the timer signal which is fed via the output line 64 from the control section 62. The output signals are passed as enable or disable signals to the corresponding gate circuits within the central unit 34, such. B. to the gate circuit 70 and the AND gates 72 and 75. The outputs of the AND gates 72 and 75 are passed via OR gates 76 to an input-output register 78a within the register group 77. The instruction decoder 69 decodes one of the Control part 62 issued command to control the activities in the corresponding parts of the central unit 34, such. B. the determination of the registers within the register group 77, and he gives a read / write command to the memory 47 and the timer 48. The outputs of the timer circuit 68 and the command encoder 69 are used as control signals to the display driver 51 and to the I / A control 31 routed The register group Ti comprises the X register as input / output registers 78a, as well as other registers 786 to 78n, which are labeled Y to N. The output of the register group 77 is connected to the adder / subtracter 71 via an OR element 70. The output of the X register 78i is fed to an AND gate 72 via a circuit 79i, the circuit 79a being a memory with the capacity of one digit. The output signal de; The adder / subtracter 71 is fed to the AND gate 74. The key input signal from the keyboard 10 is fed to the AND gate 74 via the I / O controller 31. The decoded data coming from the memory 47 and the timer 4f are passed to the AND gate 75. The output signals from the registers X to N 786 to 78n are introduced through registers 79f to Tin to gate circuits 816bis, if the registers 79b to 79 / j each have a storage capacity of one digit. The output signal of the adder / subtracter 71 is also fed to the gate circuits 81b to 81n. The outputs of the gate circuits 816 to 81π are fed to the X to N registers 786 to 78n 51 and the I / O controller 31 and a chip selection circuit 82. In accordance with a command issued by the control section 62, the chip selection circuit 82 reads the chip selection data in the X register 78a and generates the chip enable signals CE1 and CE2gemäE the contents of the register in order to control the saliva 47 or the timer 48. The outputs of the adder / subtracter 71 are given in da; A register 83 loaded for addressing. The through there; A register 83 data is given to the adder / subtracter 71 through the gate circuit 70 and divided into two addresses; an address RA represents a row address and an address CA eim column address. These addresses are fed to the memory 47 and the timer 48. Data and carry signals output from the adder / subtracter 71 are fed to a judging circuit 84. The judging circuit 8 < judges whether the data or the carry from the circuit 71 is present or not and forwards the result of the judgment to the address circuit 61. At this point in time, the successor address is output via the output line 66, and the detector signal is logically summed up so that the next address <is changed.

The memory 47 comprises a memory unit 91 to an address determination circuit 92 in which the

Read / write command R / W from command decoder 69 and the row and column addresses from A register 83 are loaded. The address determination circuit 92 and the gate circuit 93 are enabled by the chip enable signal CE 1 output by the chip select circuit 82. The data read out from the memory unit 91 via the gate circuit 93 are fed to the AND element 75 of the central unit 34, as has already been mentioned above. The output signal of the X register 78a ¹ in the m central unit 34 is passed as write data j: u to the memory unit 91 via a gate circuit 93. The storage unit 91 has a capacity of nx 8, as shown in FIG. 4 is shown. The columns B 1 to B 8 are defined by the column address CA , while the rows 1 to η are defined by the row address RA . The memory unit 91 is divided into three sections: a first section 91Λ comprises the columns Bi to B 4, a second portion 91 B includes the columns of B 5 and B 6, and a third section 91C comprises the columns Bl to Bi in the first. Section 91Λ, the first to sixteenth addresses store the total department amount corresponding to the department key 12. The seventeenth address stores the total sales between times Ti and T 2. The eighteenth address stores the total sales in the specified time range between Tl and T3. The nineteenth address stores the total sales in the time range between times Γ3 and Γ4. The total amount received is stored under the twentieth address. This memory area is thus referred to as the time-related total sales memory area. In the second area, the item or article count is stored under addresses 1 to 16. The r> sales counts between the specified times Ti and Γ2, Γ2 and Γ3, and Γ3 and Γ4 are stored in the memory area at addresses 17-19. The reception count is stored in the twentieth address

3B, the timer 48 is equipped with a time memory 100 which is used to store the day data, the current time data and preselected time data and the like. The time memory 100 is addressed by the addresses RA and CA of the rows and columns in the address determination circuit 101 via the A register 83 in the central unit 34, and the read and write operations are effected by R / W commands, which are supplied by the command decoder 69. A control part 110 of the timer 48 supplies an address code signal and the R / W command to the address determination circuit 101 for addressing the timer 100. The data output from the timer 100 is sent to a buffer register 103 and via a gate circuit 102 a gate circuit 104 is given. The output of the buffer register 103 and a one-second clock pulse from a frequency divider 105 are fed to the gate circuit 104. The frequency divider 105 works as a function of a crystal oscillator 50 and, in addition to the one-second pulse, generates a timer signal that shows the timing of the operation of the controls corresponding parts in the control part 110. The gate circuit 104 selects an input signal in accordance with a control signal from the control part HO and feeds this to an arithmetic circuit 106 designed as an adder / subtracter. The arithmetic circuit 106 performs in accordance with an output from the control part 110 command, an addition or subtraction and feeds the result of the calculation as the write data via the gate circuit 107 to the timing memory 100. The data and the transfer of the calculation result outputted from the arithmetic circuit 106 , are fed to the judging circuit 108 to judge the memory status of, for example, 60 or 24 size and timer matches. The result of the judgment by the judging circuit 108 is sent to the control part 110 , which in turn generates a control signal for the next processing on the basis of the judgment result. The data read out from the time memory 100 are passed via a gate circuit 109 to the AND gate 75 in the central unit. The gate circuits 107 and 109 and the address determination circuit 101 are enabled by the chip enable signal CE 2 from the chip selection circuit 82. The gate circuits 102, 104, 107 and the arithmetic circuit 106 as well as the assessment circuit 108 are controlled by a signal output by the control part. The gate circuit 107 is controlled by the chip enable signal CE2 and the signal from the control part 110 . The time memory 100 has a storage capacity of four rows by eight columns, which can be seen, for example, in FIG. 5A. The corresponding columns JS1 to B8 are identified by the column address CA , while the corresponding rows are identified by the row address signal RA . Rows 1 to 3 store time data such as B. Hours and minutes for every two columns, ie B 8- B 7, B 6- B 5, B 4- B 3, and B 2-BX. In addition, time data for clearly defined total sums TO 1 to TO 4 are stored in the first row. Time data AL 1 to AL 4 are stored in the second row, and time data for an operation time 5V1 to 5V4 define the total time range; the time data AL 1 to AL 4 define an alarm time, and the time data SVi through SV 4 define the operation time of a price reduction u. like. The columns BS Add the fourth row to 67 flag I and FLAG 2, the correspondence between the current time and the specified time to display; columns B 6 to B 4 store the year, month and day of the relevant date; the columns B 3 to B 1 the hour, the minute and the second of the current time In the memory location of the fourth row under column B 7 of the time memory 100 for storing the flag 2, a binary "1" is stored in the first bit b 1, if the running time is between Π and TI , while a "1" is stored in the second bit b 2, if the running time is between T2 and T3 ; A "1" is stored in the third bit b3 if the current time is between Γ3 and 7 * 4

In operation, the timer 48 operates in accordance with a reference signal supplied by the crystal oscillator 50. The reference signal output by the crystal oscillator 50 is applied to the frequency divider 105, the one-second pulse and various timing pulses generated by the A-Senkunden-pulse of the frequency divider 105 is the arithmetic circuit via the gating circuit 104 fed to the control part 110 provides the row address RA = 4 to the fourth row of the time memory 100

and reads out the contents of the memory location addressed in the time memory 100 via a gate circuit 102 in order to then load it into the buffer register 103. The gate 104 selects the output of the buffer register 103 and the one-second pulse from the frequency divider 105 and supplies them to the arithmetic circuit 106, thereby adding the one-second pulse to the second data of the column Bi. The output signal of the computing circuit 106 is fed to the time memory 100 κ> via the gate 107 and is written into the fourth row. In this way, the content of the fourth row of the memory 100 is always "refreshed". The output of the arithmetic circuit 106 is fed to the judging circuit 104, where it is judged whether or not the result of the addition reaches a predetermined value, and the judgment result determines the control operation in the control part. In particular, when the addition of the second pulse reaches row B 1 of the fourth column, that is, when the second amount reaches the value 60, this condition is determined by the judging circuit 108, and the control section adds a "1" to the content of column B2 of the fourth row, ie on the minute amount, while at the same time the seconds amount is deleted. 2> Next, a similar operation of the transmission control is repeated to suit the setting for minutes, hours, months and years.

When initially setting timer 48, the date and time must be set correctly. When so set, the control switch 20 in FIG. 1 is set to Pr, and the amount key 11 is pressed accordingly to indicate the sizes for the year, month, day, hour, minute and second. In this case, the "#" key is depressed every time data is entered into the electronic cash register. The input data entered via the keyboard 10 through the corresponding key operations are passed via the I / O control 31 to the central unit 34, where they are transmitted via the AND gate 74 and the FIG. The OR gate 76 shown in FIG. 3 can be input into the X register 78a. The input data stored in the X register 78a is transferred to the timer 48 where it is loaded into the intermediate sections of the fourth row of columns B 6 to B 1 via a gate circuit 107. In this way, the data and time data are loaded into the time memory 100 of the timer 48, and after the seconds amount loading is finally completed, the above-mentioned timing operation is carried out.

When the time data for the temporal totalization, the time data for the service time and the time data for the alarm time are written into the time memory 100, this is done by using π the amount key 11, the Γο key 196, the SV key 19a and the / 4L button 19c accomplished. Is z. If, for example, the time date for the hour is entered using the amount key 11, the minute amount is entered using the Γο key 196. After pressing the mi Γο key 196, the time sequence specifying the date "1" is entered through the amount key 11 to address the area of the first row in columns B 7 and BS , so that the hour and minute of the time date Γ1 can be loaded here. If the above operation is performed using the SV keys 19a in place of the Γο key 196, the time data for the service time is loaded into the memory 100 in sections of the third row under the columns B1 and BS. The actuation of the AL key 19c writes the time data for an alarm in the sections of the second row under the columns B 7 and β8.

The amount key 11 and the department key 12 are used to load the predetermined department data printed with the control switch 20 switched to the position Pr. The key input data brought into the memory unit 47 via the X register 78a. In the memory 47, the key input data written at the first to sixteenth addresses in the third area of the memory unit 91, which takes place via the gate circuit 93.

When processing the sales of goods, the control switch 20 is set to REG, and the article prices of the sales goods are entered using the amount key 11. Then that department key becomes 12 actuated, which by the printer part 33 on the receipt strip 41 or the individual strip 42 is printed out. At the same time, the input data are shown on the display 24 to which the Input data are brought through the central processing unit 34 and the display driver 51, and the data are accumulated in the central unit 34. Furthermore, from the memory 47 data that the Department key 12 correspond to the specified address, read out by the central unit 36, where they are to the Input data will be added, and the result of the addition will be at the specified address in the Memory 47 written. Now the price is added to a certain series of the first range 91Λ, and the item or article count is added to a specific row of the second area 915. In this way, the operation becomes similar to that described above by operating the amount key 11 and the department key 12 is repeated for each item sold. Are the prices of all goods sold is entered and the department is specified, the balance key 18 is actuated to include a receipt the total amount and / or the change amount. The thus by the central unit 34 Total amount received is made visible in the display part 24 and via the I / O controller 31 to the printer part 33 is supplied, where it is printed out on the individual strip 42 and the receipt strip 43. If the Editing using the department preset key for each department in the above If the price of the goods is not entered, the above is done Operation carried out in a similar way, with the input data of the preset data of those Address which corresponds to the department key 12 by simply pressing the department key 12.

The operation of the temporally predetermined total sum formation is described below with reference to FIG. 1 to 8 will be described. If data relating to goods sold are entered, this will be Key input signal passed through the I / O controller 31 to the central processing unit .34 and in the register 78a is set Then the balance key 18 is operated so that the data from the X register 78a into the Y registers 786 are transferred as shown in FIG. 6A is shown at step a. The data flow takes place at this point in time such that the data from the X register 78a flowing data through gate 70, adder / subtracter 71 and gate 816 into the Y register 786 arrive. In the next step 6 the reads

Control section 62 reads out the chip designating data to set the time memory 100 in the timer 48 and loads this value into given digits of the X register 78a. The control section 62 issues an operation command to the chip selection circuit 82. · -, Upon receipt of the operation command, the chip selection circuit 82 reads out the chip designating data from a given digit of the X register 78a and generates the chip enable signal CE 2 to convert the To specify time memory 100. Thereafter, the w control section 62 generates addresses RA = 4 and CA = BT to set the intermediate section of the fourth row among the columns BT of the time memory 100. The addresses are converted into serial codes by the code generator circuit 67, and then the ij converted code is supplied to the adder / subtracter 71 through the gaiter 70. The addresses RA and CA output from the adder / subtracter 71 are input to the A register 83, where they are converted into parallel data, which in turn are supplied to the addressing circuit 101 within the timer 48. A read command from the control section 62 is set via the command decoder 69 therein. This means that the chip enable signal CE2 specifies the timer 48, and the flag 2 addresses the time memory 100. By addressing in step b , the flag 2, which is in the memory location of the fourth row and the column BT (4, BT) des Time memory 100 is stored, read out, and the read-out signal is transmitted via the AND gate 75 and the OR gate 76 to the X register 78a. When the current time is read out of the time memory 100 into the buffer register 103, the time clock 48 successively reads the time data of the temporal totaling T1 to T4 from the time memory 100 from js and feeds them via the gate 104 to the arithmetic circuit 106 to generate these data with the current time stored in the buffer register 103. The comparison result is fed to the judgment circuit 108. In the evaluation circuit 108 the service time, ie T1 to T2, T2 to T3 or T3 to T4, to which the current time belongs, is looked up, and the binary number "1" is stored in the corresponding bit of the Flag2 memory location b \ to b3 des Time memory 100 loaded.

Assume that the time T1 is preset to 10:00 a.m., T2 to 12:00 p.m., T3 to 2:00 p.m. and T4 to 5:00 p.m. As described above, the memory location M (4, B 7) time memory 100 is addressed and the content of flag 2 is read from the time memory 100 into the output register 78a. The current time 10:30 am falls within the time range T1 to T2, ie 10:00 am to 12:00 pm, and the binary "1" is written to the first bit b 1 of flag 2, so that flag 2 has the value "0001" . As can be seen in step c of FIG the judgment circuit determines whether any of the bits of the flag 2 contains a "1" or not, as shown in step d if the result of judgment is nO, d. In other words, if the current time does not fall within the time ranges, the temporal totaling is not carried out and the acknowledgment is issued immediately. If the assessment is YES, i. If the current time falls within one of the time ranges, the process continues at step e in FIG. 6 continued. In this step, the control section 62 causes the chip determination circuit 82 to generate a chip enable signal CEX and addresses the memory unit 47 to address one of the addresses 17 to 19 according to the contents of the flag 2. In this case, the current time falls within the time range T1 to T2, so that the seventeenth address of the memory 47 is determined. This is followed by the transition to step / "in FIG. 6A. Then the contents of M (RA, CA), for example the article number" 20 "in the time range between T1 and T2 and the intermediate amount" ^ 13.200 " in the same area into the X register 78a. The content of "^ 13,200" in the X-register 78a and the sales data, e.g. "^ 700", which are stored in the Y register 7Sb , are transferred via the The gate circuit 70 is fed to the adder / subtracter 71. These values are added in the circuit 71. Furthermore, the article number "20" in the time range T1 to T2 is fed to the adder / subtracter 71, where it is subjected to a "+!" Operation. The total amount “£ 13,900” is then stored in the time range T1 to T2 and the number of articles “21” in the same time range at the seventeenth address of the memory 47.

The sequence of step e according to FIG. 6A is shown in detail in FIG. 6B. In step e 1 it is determined whether there is a "1" in the first bit b 1 or not, ie whether the content of flag 2 has the value 0001 or not. If the bit b \ has a “1”, step e2 loads the chip enable signal into the X register 78 and, in addition, the row address RA = 17 and the column address CA = B \ are loaded into the A register 83 . If no “1” is set in bit b 1 in step e 1, step e 3 is carried out to see whether the binary “1” is set in the second bit b 2 or not. If the "1" is set in the bit b2 , a step e4 loads the chip enable signal CEi into the X register 78a and sets the row address RA = 18 and the column address CA = B 1 in the A register 83. If no “1” is stored in bit b 2 in step e3, a next step e5 is carried out. This step loads the chip enable signal CEX into the X register 78a and the row address RA = 19 and the column address CA = BHn the A -Address register 83.

F i g. Fig. 8B shows the case when the sales processing occurs at 11:50 AM.

If the conversion processing after 12.00 happens, for example at 12.10 am, as shown in Fig. & C is shown wherein a total summation is performed and a receipt is issued, the memory locations in the eighteenth row under the column B 6 to B 1 of the memory 100 specified, since at this point in time the second bit b 2 of flag 2 is set to "1" and therefore its content is "0010". If this sale is the first one after 12 noon, the contents of the eighteenth row under columns 56 to ß 1 are all "0". Accordingly, the number of articles in the time range T2 to T3 is loaded into the memory locations of columns B 6 to B 1 and the eighteenth row with the total amount within the same time range, for example "ji.450", of the sales amount at this point in time. Thereafter, the data aggregation with respect to the storage locations of the eighteenth row under columns B 5 to Bi of the memory 100 is continued up to time T3, ie 2:00 p.m.

After 2 p.m., the data relating to the storage locations in the nineteenth row under columns 56 to B 1 S: s at time Γ4, that is, until 5 p.m. in this case, are totaled.In this case, the amount of money and the number of items are added together, and the operation go to step g . In this step, this sales data (the aforementioned total amount) stored in the Y register 786 of the register group 77 is transferred to the X register 78a and then to the I / O controller 31, where the data in the output Buffer registers (not shown) are stored. The I / O controller controls the printer section 33 based on the data stored in the output buffer register, and prints out the data, as in step h of FIG. 6 is shown. In step h , the one shown in FIGS. 9A and 9B are completed in addition to printing out the data. At the end of the data printout, the following number is printed out, as in step h 1 of FIG. 9 can be seen. At this time, the microprogram read out from the control section 62 sets the chip designation data to specify the memory 47 and the X register 78a. Then, the microprogram of the control section 62 transmits an operation command to the chip designation circuit 82. After 2 =, receipt of the operation program, the chip designation circuit 82 reads out the chip designating data from the X register 78a to generate a chip enable signal CFl and the Memory 47. Thereafter, the control section generates an address code to specify the memory locations of the seventeenth row and columns B 7 and BS of the memory unit 91. Thereafter, the address code is converted into a serial code by the code generator 67. The converted serial code is then passed through gate 70 to adder / subtracter 71 via Ji. The data output from the adder / subtracter 71 is loaded into the A register 83, where it is converted into parallel data to be supplied to the addressing circuit 92. A read command fetched from the control section 62 by the w command decoder 69 is provided in the addressing circuit 92. As a result, the content of the memory locations of the seventeenth row and the columns B% and BT, ie the successor number, e.g. B. "3400", read out from the memory unit 91, and thereupon the successor number is sent via the AND gate 75 and the OR gate 76 to the X register 78a. The sequence number read from the X register 78a is transferred to the output check register in the I / O controller 31, together with "NO", as shown in FIG. 9A is shown. The data in the output buffer register control the operation of the printer part 33 so that it prints the subsequent number "NO 3400" on the receipt. The successor number "3400", which was read from the X register 78a, is passed to the adder / subtracter, where it is increased by one. As a result of this addition, the successor number receives the value "3401", which in turn is loaded into the memory locations of the seventeenth row and columns ß8 and B7 within the memory unit 91.

When the printing operation of the sequential number is completed, the CPU 34 gives a paper feed command to the I / O controller 31. Accordingly, the paper is fed by N columns on the receipt <ή as in step h 2 in FIG. 9A is shown.

Thereafter, the central processing unit 34 transmits a stamp imprint to the I / O controller 31 so that, as can be seen in step Λ3 in Fig. 9A, “Your Receipt slip - Thank you «is printed out.

When the stamp printing is complete, the operation changes to the "data printout" state, so that the central unit 34 determines the chip for the timer 48 and addresses the date for the time memory 100. That is, the central unit 34 transmits a code which determines the chip of the timer 48, d. h, the value "0010", to the X register 78a, while at the same time issuing an operation command to the chip designation circuit 82 through the control part 62. After receiving the operation command, the chip designation circuit 82 reads the chip designation code from the X register 78a "0010" and generates the chip selection signal CE 2 in order to determine the chip of the timer 48.

Thereafter, the control section 62 transfers the address data through the gate circuit 70 to the address register 83 and to the adder / subtracter 71. The address data specifies the storage locations in the fourth row of the columns S 6, B 5 and BA. The address data is transferred from the address register 83 to the addressing circuit 101 in the timer 48. In the address determination circuit 101 , a read command is set, which is supplied from the control part via the command decoder 69. Accordingly, the date on November 20, 1976 becomes e.g. B. "76 11 20", read from the memory locations of the fourth row of columns S 6, B 5 and B 4 of the memory 100 , as can be seen at step Λ5 in FIG. 9B. The data read out are transferred to the X register 78a via the gate 109, the AND gate 75 and the OR gate 76. The read out from the X register 78a date is transmitted to the output buffer register in the I / O control, together with the segment code as h in step 6 in F i g. 9B can be seen. The I / O controller 31 controls the printer section 33 in accordance with the data stored in the output buffer register to print out the data as shown in step Λ7 in Fig. 9B. The receipt output operation is as described above. The stamp “Your receipt - thank you” and the printing of Dater are carried out for the subsequent receipt. According to FIG. 9B, the document is torn off between the successor number and the stamp print with an N-row spacing. Therefore, stamp printing and data printing are in the upper part of the issued receipt! arranged.

In the embodiment explained above, the time and the data are set by setting the control switch: 20 to Pr and alternatively pressing the amount key 11 and the non-adding key “£”. However, year, month, day, hour, minute and second can be entered one after the other by pressing the amount key 11 and then the non-addition key for the same pulse. If the time for totaling the total is set, hours and minutes can be entered consecutively using the amount key 11 by then pressing the 7b total key 196 , deviating from the example described above. Since the total key 196 is provided separately, it can always be set, regardless of the state set by the control switch 20. If you want the Γο-grand total key 196 to be replaced by another key, the ST key V or another can be used under de

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the state Pr is switched.

In the above embodiment, the sales amount and sales count are within a predetermined Time added up each time the balance key 18 is pressed. However, if the space is left to the Saving the total amount and the count provided for each department so that they can be added up be carried out for each department. In this case, the totaling is performed each time the Department key carried out. In addition, there are storage spaces to save the total amount and the counts are provided for each deal, the total amount and the count amount be added together for each transaction. In this case, the Sales key 16 a totaling carried out. There is also space to save the Total amount and counts for each employee

tentaste provided, so for each employee the total turnover and the count within one given time are added together. In this case, an aggregation is made every time performed when the registration key such. B. the completion key 16, the department key 12 or the Intermediate amount key 17 can be operated.

The amounts and the counts can not only be within a certain time, but also within of the date can be added together. In this case, storage spaces are provided for Saving the total and counts of the predetermined date, and each time a Registration is done, the preset date is compared with the date of registration at the Store the total amount and the count accumulatively in a given memory location.

In addition 12 sheets of drawings

Claims (10)

1 claims: 1. Electronic cash register, with an input keyboard, a memory having several memory locations for storing accumulated sales amounts, and a central processing unit for processing data entered via the keyboard, characterized by a time-data-counting timer (48), a time memory {100B) for storing the Time data, a time memory (100A) for storing predetermined time interval data entered using the input keyboard (10), a comparator (108) for comparing the counted time data with the time interval data stored in the time memory (10OA ^, the central processing unit (34) having a device which, as a function of the comparison result, writes data inputted after completion of a data input into those storage locations of the memory (47) which are determined by the comparison result 2. Electronic cash register according to claim 1, characterized in that the storage locations of the Memory include a memory area assigned to the time interval, which is used to store the Total sales amount depending on the comparison result, which is used at the conclusion of the Registration was obtained by pressing a balance key (18). 3. Electronic cash register according to claim 1, characterized in that the storage locations of the Memory include memory areas assigned to the time intervals that are used to store Total sales amounts of the corresponding departments depending on the comparison results which are obtained by the comparator when the registration is made by pressing Department buttons (12) takes place. 4. Electronic cash register according to claim 1, characterized in that the storage locations of the Memory include memory areas assigned to the time intervals that are used to store Total sales amounts of corresponding business transactions depending on the comparison results serve which are obtained from the comparator when the cash register is operated by from sales keys (16). 5. Electronic cash register according to claim 1, characterized in that the timer (48) with a pulse generating circuit (105), a computing circuit (106), a control part (110) and the time memory (100), the memory (47) for storing total sales amounts, and the central processing unit (34) for adding up sales amounts on a single chip are trained. 6. Electronic cash register according to claim 1, characterized in that the timer (48, 50) a frequency divider circuit (105) comprises a computing circuit for dividing frequency reference signals (106) for successively adding timing pulse signals from the frequency divider circuit (105), the time memory (100) for storing time data of the arithmetic circuit (106) and a Control part (110) for controlling the time counting operation of the arithmetic circuit (106). 7. Electronic cash register according to claim 5, characterized in that the time memory (100) has a memory area for storing time data for time intervals within which sales amounts are added up. 8. An electronic cash register according to claim 5, characterized in that the period memory (100) includes a storage area for storing an A larmzeit 9. Electronic cash register according to claim 5, characterized in that the time memory (100) has a memory area for storing a “flag”, which is indicated by the comparator shows the delivered result with regard to the current time and the time data 10. Electronic cash register according to claim 1, 2, 3, 4 or 6, characterized in that the Time memory (100) has memory areas for storing the sales start time and sales end time