JP2004241959A - Instantaneous interruption reconfiguration processing method and apparatus - Google Patents

Abstract

When receiving an input packet from a communication network, performing predetermined processing, and transmitting the output packet as an output packet, a non-interruptible power supply that reconfigures a packet processing circuit while maintaining a communication connection by a single configuration. A configuration processing method and apparatus are provided.
A reconfiguration instruction signal (S1) transmitted from a system processor (3) is held in a reception queue (22), an accumulation instruction signal (S6) is output, and a time required for an input packet to pass through a packet processing circuit (1) is represented by T1. When the time T1 or more has elapsed since the output of the accumulation instruction signal S6, the reconfiguration instruction signal S1 held in the reception queue 22 is output to the packet processing circuit 1, and the reconfiguration is performed. When the reconfiguration is completed, the stored packets are read and transmitted as output packets.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method and an apparatus for reconfiguring a packet processing circuit provided in a communication network device, and in particular, a communication table (for example, a session state table, a communication protocol state table, etc.) required for end-to-end communication by reconfiguration. When the communication table is not changed, or when the communication table is not held, reconfiguration is enabled while maintaining a communication link session.
[0002]
[Prior art]
Conventionally, reconfiguration of a network device having a packet processing circuit capable of partially reconfiguring an internal circuit has been performed by making the network device have a redundant configuration. In this case, the network devices are configured by making the programmable devices in the interface board redundant for the active system and the standby system, and when reconfiguration work occurs in the active system, the network device switches from the active programmable device to the standby programmable system. By switching to the device, reconfiguration was realized without any interruption.
[0003]
In a processing method using such a redundant configuration, for example, a cell switch for receiving the same cell input and a read control unit corresponding to the cell switch are provided in two systems, an active system and a standby system. In a system in which a cell stored in a buffer memory in a cell switch is read-controlled, one of cell outputs is selected and output is performed without an instantaneous interruption, a read control signal is transmitted even when a write signal storage memory is empty. In some cases, cells stored in the buffer memory are discarded due to malfunction due to noise or the like, and the working system and the standby system are reliably synchronized (see Patent Document 1).
[0004]
In a redundant configuration of an ATM switch having an active switch unit and a standby switch unit, the cell accumulation states of the queues of the same delay priority class in each switch unit are adjusted in ascending order of delay priority class. Performing redundant switching from the working system to the standby system according to the detection of the switching control cell of the lowest delay priority class, even when having a delay priority control function, without causing a cell delay There is also one that performs redundancy switching without momentary interruption (see Patent Document 2).
[0005]
On the other hand, the configuration processing method includes, for example, detecting that the programmable device is being configured from the connection state of the configuration cable and turning off the connection between the programmable device and the circuit, thereby causing the circuit to malfunction. (See Patent Document 3).
[0006]
[Patent Document 1]
JP-A-7-30545 (paragraphs [0025] [0026] [0040] [0041], FIGS. 1 and 2)
[Patent Document 2]
JP-A-10-190683 (paragraphs [0034] and [0035], FIG. 1)
[Patent Document 3]
JP-A-11-298549 (paragraphs [0029] and [0030])
[0007]
[Problems to be solved by the invention]
However, in the conventional reconfiguration processing method using a redundant configuration, it is necessary to mount a plurality of programmable devices on the interface board, and thus there is a problem that the mounting area increases and the cost increases. Also, when this interface board is recognized as a single cluster system, although the interface board has a plurality of programmable devices, it has only the performance of one of the programmable devices, and is not There was a problem of economy.
[0008]
For this reason, a reconfiguration technology that can perform reconfiguration without interruption by maintaining a communication link session of end-to-end communication by using a single interface board of non-redundant configuration without using such a redundant configuration Requested.
[0009]
The present invention has been made in view of such circumstances, and an object of the present invention is to provide an uninterruptible reconfiguration processing method for reconfiguring a packet processing circuit while maintaining a communication connection by a single configuration. And a device.
[0010]
[Means for Solving the Problems]
The present invention will be described with reference to the principle diagrams shown in FIGS.
The packet processing circuit 1 has a function of inputting a packet, performing predetermined processing on the input packet and outputting the output packet as an output packet, and a memory for reconfiguration. When the reconfiguration instruction signal S1 is input and reconfiguration is performed when the session state table, the communication protocol table, and the like are not changed or the communication table is not held, when the reconfiguration is completed, the reconfiguration is performed. A function of outputting a completion signal S2. The system processor 3 has a function of transmitting a reconfiguration instruction signal S1 and causing the packet processing circuit 1 to perform reconfiguration.
[0011]
The hitless reconfiguration processing device 5 has a process management control unit 2 and an input packet buffer unit 4. The process management control unit 2 includes a reception queue 22 that holds a reconfiguration instruction signal S1 received from the system processor, an input packet control unit 21 that outputs a storage instruction signal S6 and a read instruction signal S7, and a reconfiguration execution instruction. A reconfiguration signal processing unit 23 that receives the timing signals S3 and S4 and the reconfiguration completion signal S2 and outputs a reconfiguration instruction signal S1.
[0012]
The input packet buffer unit 4 outputs a reconfiguration execution instruction timing signal S4, a buffer control unit 41 that inputs an accumulation instruction signal S6 and an input packet empty signal S5, and an accumulation instruction signal S6, and executes reconfiguration execution. It has an input packet monitoring unit 42 that outputs an instruction timing signal S3, and an input packet storage unit 43 that receives the accumulation instruction signal S6 and the read instruction signal S7, and accumulates and reads an externally received input packet. Further, the buffer control unit 41 and the input packet monitoring unit 42 output an instruction to store the input packet and an instruction to read the stored packet to the input packet storage unit 43, and the input packet storage unit 43 inputs these instructions. Under the above configuration, the present invention will be described below.
[0013]
According to the first aspect of the present invention, the reconfiguration processing device 5 having the process management control unit 2 and the input packet buffer unit 4 reconfigures the packet processing circuit 1 without interruption while receiving an input packet from the communication network. And transmitting the reconfiguration instruction signal S1 as an output packet, wherein the process management control unit 2 receives a reconfiguration instruction signal S1 from the outside and stores the reconfiguration instruction signal S1 in the reception queue 22; Outputting to the input packet buffer unit 4, the input packet buffer unit 4 receiving the accumulation instruction signal S6 and accumulating the input packet, and the process management control unit 2 determines that the input packet is a packet. If the time required to pass through the processing circuit 1 is T1, Outputting a reconfiguration instruction signal S1 held in the reception queue 22 to the packet processing circuit 1 when a time equal to or longer than T1 has elapsed since the output of the accumulation instruction signal S6; Performing the reconfiguration by inputting the reconfiguration instruction signal S1, and, when the reconfiguration is completed, the input packet buffer unit 4 reads the stored packet and processes the packet as an output packet. Transmitting via the circuit 1. Thereby, the reconfiguration can be performed while maintaining the end-to-end communication link in the communication network. In addition, when the packet processing circuit 1 does not hold a communication table such as a session state table necessary for end-to-end communication of the IP packet communication processing while maintaining the communication connection, or does not change by reconfiguration, reconfiguration is performed. be able to.
[0014]
According to a second aspect of the present invention, a reconfiguration processing device having a process management control unit and an input packet buffer unit allows a reconfiguration of a packet processing circuit to be performed without interruption while receiving an input packet from a communication network. The process management control unit 2 receives a reconfiguration instruction signal S1 from outside and stores it in the reception queue 22, and the input packet buffer unit 4 However, when the time required for the input packet to pass through the packet processing circuit 1 is T1, the timing at which the input packet is not continuously received for a time equal to or longer than T1 from the communication network is extracted. Store the input packet and reconfigure Outputting a row instruction timing signal S3 to the process management control unit 2; and inputting the reconfiguration execution instruction timing signal S3 to the process management control unit 2 to input the reconfiguration execution instruction timing signal S3. Outputting the configuration instruction signal S1 to the packet processing circuit 1; the packet processing circuit 1 receiving the reconfiguration instruction signal S1 to perform reconfiguration; and the input packet buffer unit 4 Upon completion of reconfiguration, reading out the stored packets and transmitting them as output packets via the packet processing circuit 1. As a result, the reconfiguration instruction signal S1 held in the reception queue 22 can be pruned at a timing when there is no input packet, and the reconfiguration can be performed while maintaining the end-to-end communication link session. Further, the input packet buffer unit 4 can determine the reconfiguration execution instruction timing and notify the process management control unit 2 of the timing. By performing the reconfiguration at a timing when there is no continuous input packet, the input packet The buffer amount of the buffer unit 4 can be reduced.
[0015]
According to a third aspect of the present invention, the reconfiguration processing device 5 having the process management control unit 2 and the input packet buffer unit 4 reconfigures the packet processing circuit 1 without interruption while receiving an input packet from the communication network. The process management control unit 2 receives a reconfiguration instruction signal S1 from outside and stores it in the reception queue 22, and the input packet buffer unit 4 Monitoring the buffer size, which is the amount of buffer used to store the input packet, and when the buffer size is zero, starts storing the input packet and starts counting the elapsed time; The time required for an input packet to pass through the packet processing circuit 1 When the count value is set to 1, if the count value is smaller than T1 and the buffer size is smaller than a preset upper limit value of the buffer size, accumulation of the input packet is continued, and the count value is set to T1. If the buffer size is smaller than and the buffer size is equal to the upper limit value, the stored packet is read and transmitted as an output packet through the packet processing circuit 1, and when the buffer size becomes zero, the count value is reduced. When the count value is equal to T1 and the buffer size is smaller than the upper limit value, a reconfiguration execution instruction timing signal S4 is output to the process management control unit 2 and the count value is reset. The process management control unit 2 executes the reconfiguration Receiving the configuration execution instruction timing signal S4 and outputting the reconfiguration instruction signal S1 held in the reception queue 22 to the packet processing circuit 1; And performing a reconfiguration by inputting S1. As a result, even when the upper limit value of the buffer size is relatively small, reconfiguration can be forcibly performed at a timing when there is no continuous input packet, and desired reconfiguration execution instruction timing can be generated. .
[0016]
According to a fourth aspect of the present invention, in the reconfiguration processing method according to the third aspect, the input packet buffer unit 4 outputs a reconfiguration execution instruction timing signal S4 to the process management control unit 2 by the packet processing circuit. When the size of an input packet that is continuously received from the communication network and stored is set to Q within a time period from the start of reconfiguration of 1 to the completion thereof, the count value is set to T1. And the buffer size is smaller than a value obtained by subtracting Q from the upper limit value. As a result, the buffer size does not reach the upper limit before the reconfiguration is completed, and the input packet is not lost. Therefore, the reconfiguration is performed while maintaining the end-to-end communication link in the communication network. be able to.
[0017]
According to a fifth aspect of the present invention, the reconfiguration processing device having the process management control unit and the input packet buffer unit receives the input packet from the communication network and instantaneously interrupts the reconfiguration of the packet processing circuit. The process management control unit 2 receives a reconfiguration instruction signal S1 from the outside and holds the reconfiguration instruction signal S1 in a reception queue 22, and the packet processing circuit 1 Outputting an input packet empty signal S5 to the input packet buffer unit 4 when there is no input packet to be processed in the packet processing circuit 1; To start storing the input packets and reconfigure Outputting the reconfiguration execution instruction timing signal S4 to the process management control unit 2, and the process management control unit 2 receiving the reconfiguration execution instruction timing signal S4 and receiving the reconfiguration execution instruction timing signal S4. A step of outputting a configuration instruction signal S1 to the packet processing circuit 1, a step of the packet processing circuit 1 performing the reconfiguration by inputting the reconfiguration instruction signal S1, and a step of: Upon completion of the reconfiguration, reading the stored packet and transmitting the read packet as an output packet through the packet processing circuit 1. As a result, the desired reconfiguration execution instruction timing can be generated also by the input packet empty signal S5 that notifies that the input packet from the packet processing circuit 1 is empty.
[0018]
According to a sixth aspect of the present invention, in the reconfiguration processing method according to any one of the first to second aspects, the process management control unit 2 starts reconfiguration of the packet processing circuit 1. When the time from completion to T2 is T2, when the reconfiguration instruction signal S1 is output to the packet processing circuit 1 and the time T2 or more elapses, the read instruction signal S7 is input to the input packet buffer unit 4. And the packet buffer unit 4 receives the read instruction signal S7, reads the stored packets, and transmits the read packets as output packets via the packet processing circuit 1. It is characterized by the following. Thereby, the reconfiguration can be performed while maintaining the end-to-end communication link in the communication network by the time control based on the arbitrary set time (T2).
[0019]
According to a seventh aspect of the present invention, in the reconfiguration processing method according to any one of the first, second, and fifth aspects, when the packet processing circuit 1 completes a reconfiguration, the packet processing circuit 1 outputs a reconfiguration completion signal S2. Outputting to the process management control unit 2, the process management control unit 2 receiving the reconfiguration completion signal S2 and outputting a read instruction signal S7 to the input packet buffer unit 4, Buffer unit 4 receiving the read instruction signal S7, reading the stored packets, and transmitting the read packets as output packets via the packet processing circuit 1. . As a result, the process management control unit 2 does not perform time control based on an arbitrary set time (T2), but issues an instruction to read out the packets stored in the input packet buffer unit 4 after the reconfiguration is actually completed. Therefore, it is possible to reliably perform the reconfiguration while maintaining the end-to-end communication link in the communication network.
[0020]
The invention of claim 8 is a reconfiguration process in which the packet processing circuit 1 is reconfigured without an instantaneous interruption while receiving an input packet from a communication network, and is transmitted as an output packet via the packet processing circuit 1. In the device 5, the reconfiguration processing device 5 includes a process management control unit 2 and an input packet buffer unit 4. The process management control unit 2 includes a reception queue 22 for holding a reconfiguration instruction signal S1. , An input packet control unit 21 for outputting a storage instruction signal S6 to the input packet buffer unit 4, and receiving the reconfiguration instruction signal S1 from the outside and holding it in a reception queue 22. When the time required to pass through the input packet is T1, When a time equal to or longer than T1 has elapsed since the output of the accumulation instruction signal S6 by the control unit 22, the reconfiguration instruction signal S1 held in the reception queue 22 is output to the packet processing circuit 1 to perform the reconfiguration. The input packet buffer unit 4 receives the accumulation instruction signal S6, accumulates the input packets, and when the reconfiguration is completed, the input packet buffer unit 4 stores the input packet. An input packet storage unit 43 for reading a packet and transmitting the read packet as an output packet via the packet processing circuit 1 is provided. The same effect as that of the first aspect is obtained.
[0021]
The invention of claim 9 is a reconfiguration process of reconfiguring the packet processing circuit 1 without interruption while receiving an input packet from a communication network, and transmitting the output packet as an output packet via the packet processing circuit 1. In the device 5, the reconfiguration processing device 5 includes a process management control unit 2 and an input packet buffer unit 4. The process management control unit 2 includes a reception queue 22 for holding a reconfiguration instruction signal S1. The reconfiguration instruction signal S1 received from the outside is received and held in the reception queue 22, and when the reconfiguration execution instruction timing signal S3 is input, the reconfiguration instruction signal S1 held in the reception queue 22 is received. Output to packet processing circuit 1 for reconfiguration The input packet buffer unit 4 stores an input packet when receiving an instruction to store the input packet, and stores the input packet when the reconfiguration is completed. An input packet storage unit 43 for reading out the received packet and transmitting it as an output packet via the packet processing circuit 1; and, when the time required for the input packet to pass through the packet processing circuit 1 is T1, the communication A timing at which an input packet is not received continuously from the network for a time equal to or longer than T1 is extracted. At this timing, an instruction to store the input packet is output to the input packet storage unit 43, and a reconfiguration execution instruction timing signal is output. An input path for outputting S3 to the process management control unit 2. It is characterized in that it has a Tsu preparative monitoring unit 42. The same effect as that of the second aspect is obtained.
[0022]
A reconfiguration process for reconfiguring the packet processing circuit 1 without interruption while receiving an input packet from a communication network and transmitting the output packet as an output packet via the packet processing circuit 1. In the device 5, the reconfiguration processing device 5 includes a process management control unit 2 and an input packet buffer unit 4. The process management control unit 2 includes a reception queue 22 for holding a reconfiguration instruction signal S1. When the reconfiguration instruction signal S1 is received from the outside and held in the reception queue 22 and the reconfiguration execution instruction timing signal S4 is input, the reconfiguration instruction signal S1 held in the reception queue 22 is received. Output to packet processing circuit 1 for reconfiguration The input packet buffer unit 21 receives an instruction to store the input packet, stores the input packet, and issues an instruction to read the stored packet. An input packet storage unit 43 for inputting and reading the stored packets and transmitting the read packets as output packets to the communication network via the packet processing circuit 1, and a buffer size which is a used amount of a buffer for storing the input packets. When the buffer size is zero, an instruction to accumulate the input packet is output to the input packet accumulating unit 43, and the counting of the elapsed time is started, so that the input packet passes through the packet processing circuit. When the time required for the count is T1, the count value is smaller than T1 and the If the buffer size is smaller than a preset upper limit value of the buffer size, the accumulation of the input packet is continued, and if the count value is smaller than T1 and the buffer size is equal to the upper limit value, the accumulation is continued. An instruction to read the received packet is output to the input packet storage unit 43, and when the buffer size becomes zero, the count value is reset, and the count value is equal to T1, and the buffer size is smaller than the upper limit value. In this case, a buffer control unit 41 that outputs the reconfiguration execution instruction timing signal S4 to the process management control unit 2 and resets the count value is provided. The same effect as the third aspect of the invention is achieved.
[0023]
According to an eleventh aspect of the present invention, in the reconfiguration processing device 5 according to the tenth aspect, the buffer control unit 41 of the input packet buffer unit 4 outputs a reconfiguration execution instruction timing signal S4 to the process management control unit 2. The size of an input packet that is continuously received and stored from the communication network within the time from when the packet processing circuit 1 starts reconfiguration to when the packet processing circuit 1 completes is set to Q. In this case, the count value is equal to T1, and the buffer size is smaller than a value obtained by subtracting Q from an upper limit value. The same effect as that of the fourth aspect is obtained.
[0024]
A reconfiguration process for reconfiguring the packet processing circuit 1 without interruption while receiving an input packet from a communication network and transmitting the output packet as an output packet via the packet processing circuit 1. In the device 5, the reconfiguration processing device 5 includes a process management control unit 2 and an input packet buffer unit 4. The process management control unit 2 includes a reception queue 22 for holding a reconfiguration instruction signal S1. When the reconfiguration instruction signal S1 is received from the outside and held in the reception queue 22 and the reconfiguration execution instruction timing signal S4 is input, the reconfiguration instruction signal S1 held in the reception queue 22 is received. Output to packet processing circuit 1 for reconfiguration The input packet buffer unit 4 stores an input packet when receiving an instruction to store an input packet, and stores the input packet when the reconfiguration is completed. An input packet storage unit 43 for reading the stored packets and transmitting them as output packets to the communication network via the packet processing circuit 1; and transmitting when there is no input packet to be subjected to packet processing from the packet processing circuit 1. When the input packet empty signal S5 is input, a buffer control that outputs a signal for storing the input packet to the input packet storage unit 43 and outputs a reconfiguration execution instruction timing signal S4 to the process management control unit 2 And a portion 41. The same effect as that of the fifth aspect is obtained.
[0025]
According to a thirteenth aspect, in the reconfiguration processing device 5 according to any one of the eighth to ninth aspects, the process management control unit 2 starts reconfiguration of the packet processing circuit 1. When the time from completion to completion is T2, when the reconfiguration instruction signal S1 is output to the packet processing circuit 1 and a time equal to or longer than T2 has elapsed, the read instruction signal S7 is input to the input packet buffer unit. 4, the input packet buffer unit 4 receives the read instruction signal S7, reads the stored packets, and outputs the read packets as output packets via the packet processing circuit 1. It has an input packet storage unit 43 for transmission. The same effect as that of the sixth aspect is obtained.
[0026]
According to a fourteenth aspect of the present invention, in the reconfiguration processing device 5 according to any one of the eighth to ninth aspects, the process management control unit 2 completes the reconfiguration from the packet processing circuit 1. An input packet control unit 21 that receives a reconfiguration completion signal S2 that is output at the time and outputs a read instruction signal S7 to the input packet buffer unit 4; It has an input packet storage unit 43 that receives the signal S7, reads out the stored packets, and transmits them as output packets via the packet processing circuit 1. An effect similar to that of the seventh aspect is obtained.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 3 is a schematic diagram of an exchange system using the non-interruptible reconfiguration processing device according to the embodiment of the present invention. The switching device system includes terminals 100A and 100B, a switching device 103, and an operation terminal 104. The switching device 103 is, for example, an IP router or an ATM switch, has interface control circuits 101A and 101B, and a switch 102, and communicates with the terminals 100A and 100B via a network. The operation terminal 104 communicates with the switching device 103 and instructs the interface circuits 101A and 101B to perform reconfiguration.
[0028]
The interface control circuit 101A has a function of a communication interface between the switch 102 and the terminal 100A, and the interface control circuit 101B has a function of a communication interface between the switch 102 and the terminal 100B. The interface control circuits 101A and 101B are equipped with a hardware routing engine, a hardware policy control engine, and the like, and are configured by devices that can reconfigure a part of the internal circuit. The switch 102 is also capable of reconfiguring a part of the internal circuit, similarly to the interface control circuit.
[0029]
The interface control circuits 101A and 101B and the switch 102 are respectively formed on a printed circuit board, and as shown in FIG. 1, a packet processing circuit 1 having a configuration memory, a configuration control circuit, and a programmable device. It has a disconnection reconfiguration processing device 5. Here, the configuration memory stores data necessary for the configuration. When the configuration control circuit receives the reconfiguration instruction signal S1, it reads data from the configuration memory in accordance with the instruction of the reconfiguration instruction signal S1 and resets the programmable device. It has a function to perform configuration. Further, the programmable device has a function of performing a predetermined process on an input packet and outputting it to a communication network as an output packet.
[0030]
Hereinafter, one embodiment of the sequence operation at the time of reconfiguration will be described with reference to FIG.
As shown in FIG. 3, a description will be given of a case where the search bit width and the search field of the hardware policy control engine are additionally changed in the switching system in which the interface control circuits 101A and 101B are mounted on the switching device 103. For example, as a search field, data of an application layer such as a URL (Uniform Resource Locator) in an IP packet transmitted and received between the terminals 100A and 100B is added so that the interface control circuits 101A and 101B can search.
[0031]
First, the maintenance person specifies the interface control circuits 101A and 101B using the operation terminal 104, and writes reconfiguration data to the configuration memory so that the URL as a search field can be searched from the interface control circuits 101A and 101B. . Then, the reconfiguration instruction signal S1 is output from the operation terminal 104 at an arbitrary timing by the operation of the operation terminal 104 by the maintenance person (step S201).
[0032]
Upon receiving the reconfiguration instruction signal S1 output from the operation terminal 104, the reconfiguration processing device 5 of the interface control circuits 101A and 101B holds the reconfiguration instruction signal S1 in the reception queue 22 (step S202). The input packet control unit 21 in the process management control unit 2 of the hitless reconfiguration processing device 5 outputs an input packet accumulation instruction signal S6 to the input packet buffer unit 4. Upon input of the accumulation instruction signal S6, the input packet accumulation unit 43 of the input packet buffer unit 4 accumulates the received input packets by the FIFO method (Step S203).
[0033]
After a lapse of time (T1 time) required for the input packet to pass through the packet processing circuit 1, the reconfiguration signal processing unit 23 of the process management control unit 2 outputs the reconfiguration instruction signal S1 held in the reception queue. Pruning (step S204), and a reconfiguration instruction signal S1 is output to the packet processing circuit 1 (S205).
[0034]
Upon receiving the reconfiguration instruction signal S1, the packet processing circuit 1 sets the reconfiguration data stored in the configuration memory in the programmable device by the reconfiguration control process, and reconfigures the packet processing circuit 1. Perform (Step S206).
[0035]
The input packet control unit 21 of the process management control unit 2 calculates the time (T2 time) from when the reconfiguration signal processing unit 23 outputs the reconfiguration instruction signal S1 to when the reconfiguration of the packet processing circuit 1 is completed. After the elapse, the reading instruction signal S7 of the stored packet is output to the input packet buffer unit 4 (step S207).
[0036]
As a result, in the interface control circuits 101A and 101B, URL (Uniform Resource Locator) data in the IP packet transmitted and received between the terminals 100A and 100B is added to the search field, so that the URL data can be searched. .
[0037]
Next, a sequence operation at the time of reconfiguration when the input packet monitoring unit 42 is provided in the non-instantaneous interruption reconfiguration processing device 5 will be described with reference to FIG.
[0038]
Similar to step 201 shown in FIG. 4, after the maintenance person writes the reconfiguration data to the configuration memories of the interface control circuits 101A and 101B using the operation terminal 104, the operation terminal 104 follows the operation of the maintenance person. The reconfiguration instruction signal S1 is output from the operation terminal 104 at an arbitrary timing (step S301).
[0039]
Upon receiving the reconfiguration instruction signal S1 output from the operation terminal 104, the non-instantaneous interruption reconfiguration processing device 5 of the interface control circuits 101A and 101B holds the reconfiguration instruction signal S1 in the reception queue 22 (step S302). The input packet control unit 21 of the process management control unit 2 outputs an input packet accumulation instruction signal S6 to the input packet buffer unit 4. Upon input of the accumulation instruction signal S6, the input packet monitoring unit 42 of the input packet buffer unit 4 monitors the input packet (Step S30).
[0040]
The input packet monitoring unit 42 extracts a timing at which there is no input packet that is continuous for the time T1 or more, and sets the timing as a reconfiguration execution instruction timing. Then, the input packet storage unit 43 of the input packet buffer unit stores the input packet (Step S304).
[0041]
The input packet monitoring unit 42 of the input packet buffer unit 4 transmits the reconfiguration execution instruction timing signal S3 to the process management control unit 2 in order to notify the process management control unit 2 of the timing of cutting the reconfiguration instruction signal S1 held in the reception queue 22. Output. The reconfiguration signal processing unit 23 of the process management control unit 2 receives the reconfiguration execution instruction timing signal S3, cuts the reconfiguration instruction signal S1 held in the reception queue 22 (step S305), and performs the reconfiguration. The instruction signal S1 is output to the packet processing circuit 1 (S306).
[0042]
Upon receiving the reconfiguration instruction signal S1, the packet processing circuit 1 reconfigures the packet processing circuit 1 as in step 206 shown in FIG. 4 (step S307).
[0043]
The input packet control unit 21 of the process management control unit 2 outputs the stored packet read instruction signal S7 to the input packet buffer unit 4 after the lapse of time T2 or more, similarly to Step 207 shown in FIG. 4 (Step S308). .
[0044]
Next, with reference to FIG. 6, a sequence operation at the time of reconfiguration when the buffer control unit 41 is provided in the non-instantaneous interruption reconfiguration processing device 5 will be described.
[0045]
This sequence operation is started from a state where the input packet buffer unit 4 is in the input packet reading non-stop state (step S400).
The buffer control unit 41 of the input packet buffer unit 4 proceeds to the step of determining the start of accumulation when the accumulation instruction signal S6 is input from the process management control unit 2, and when the signal is not input, Wait for input (step S401).
[0046]
Here, the buffer control unit 41 includes a counter for counting an elapsed time of T1 time which is a time period required for the input packet to pass through the packet processing circuit 1, a buffer size for storing the input packet (buffer usage amount). ) For determining the buffer size. When the buffer size determination means of the buffer control unit 41 determines that the buffer size is zero (buffer is empty), it determines the start of accumulation and proceeds to the next step. On the other hand, if it is determined that the buffer size is not zero (the buffer is not empty), it is determined that the accumulation cannot be started, and the above accumulation start determination is repeated until the buffer size becomes zero (step S402).
[0047]
If it is determined based on the storage start determination in step 402 that the storage has started, the input packet storage unit 43 of the input packet buffer unit 4 stops buffer reading and starts storing the input packets. Further, the counter of the time period T1 is started (step S403).
[0048]
If the buffer control unit determines that count value <T1 time and buffer size <upper limit of the buffer size, the input packet storage unit 43 continues to store the received input packet. If it is determined that the count value is equal to the time T1 and the buffer size is smaller than the upper limit of the buffer size, the process proceeds to the next step 405 as reconfigurable. If it is determined that the count value is smaller than the time T1 and the buffer size is equal to the upper limit of the buffer size, it is determined that accumulation cannot be continued, and the process proceeds to step 406 (step S404).
[0049]
If the size of the input packets to be continuously received from the communication network and stored is set to Q within the time from when the packet processing circuit 1 starts the reconfiguration to when the reconfiguration is completed, the counting is performed. If it is determined that the value = T1 time and the buffer size <(upper limit value of the buffer size) −Q, reconfiguration is possible and the process may proceed to the next step 405.
[0050]
When the buffer control unit 41 determines in step 404 that reconfiguration is possible, the buffer management unit 41 executes the reconfiguration to notify the process management control unit 2 of the timing of cutting the reconfiguration instruction signal S1 held in the reception queue 22. An instruction timing signal S3 is output (step S405).
[0051]
On the other hand, when the buffer control unit 41 determines in step 404 that the accumulation cannot be continued, the input packet accumulation unit 43 stops the accumulation of the input packet and performs the read processing of the input packet. When the buffer control unit 41 determines that the buffer size is zero (the buffer is empty), the buffer control unit 41 resets the counter, returns to step 402, and again determines the start of accumulation (step S406).
[0052]
Next, a sequence operation of the reconfiguration completion when the process management control unit 2 receives the reconfiguration completion signal S2 from the packet processing circuit 1 will be described with reference to FIG.
[0053]
The reconfiguration signal processing unit 23 of the process management control unit 2 cuts the reconfiguration instruction signal S1 held in the reception queue 22, and outputs the reconfiguration instruction signal S1 to the packet processing circuit 1 (Step S501).
[0054]
Upon receiving the reconfiguration instruction signal S1, the packet processing circuit 1 reconfigures the packet processing circuit 1 as in step 206 shown in FIG. 4 (step S502).
[0055]
Upon completing the reconfiguration, the packet processing circuit 1 outputs a reconfiguration completion signal S2 to the operation terminal 104 via the non-interruptible reconfiguration processing device 5 (step S503). The reconfiguration signal processing unit 23 in the process management control unit 2 of the hitless reconfiguration processing device 5 receives the reconfiguration completion signal S2, outputs completion to the input packet control unit 21, and outputs the completion to the input packet control unit 21. 21 outputs a stored packet read instruction signal S7 to the input packet buffer unit 4 (step S504).
[0056]
Next, a sequence operation in a case where reconfiguration is performed based on the input packet empty signal S5 output from the packet processing circuit 1 will be described with reference to FIG.
[0057]
Similar to step 201 shown in FIG. 4, after the maintenance person writes the reconfiguration data to the configuration memories of the interface control circuits 101A and 101B using the operation terminal 104, the operation terminal 104 follows the operation of the maintenance person. The reconfiguration instruction signal S1 is output from the operation terminal 104 at an arbitrary timing (step S601).
[0058]
Upon receiving the reconfiguration instruction signal S1 output from the operation terminal 104, the uninterruptible reconfiguration processing device 5 holds the signal in the reception queue 22. The input packet control unit 21 of the process management control unit 2 outputs an input packet accumulation instruction signal S6 to the input packet buffer unit 4. Upon receiving the accumulation instruction signal S6, the buffer control unit 41 of the input packet buffer unit 4 monitors the input of the input packet empty signal S5 from the packet processing circuit 1 (step S602).
[0059]
The packet processing circuit 1 outputs an input packet empty signal S5 notifying that the input packet is empty to the buffer control unit 41 (step S603). Then, when the input packet empty signal S5 is input, the buffer controller 41 accumulates the input packets (step S604).
[0060]
The buffer control unit 41 outputs a reconfiguration execution instruction timing signal S3 to the process management control unit 2 in order to notify a timing at which the reconfiguration instruction signal S1 held in the reception queue 22 is cut. The reconfiguration signal processing unit 23 of the process management control unit 2 receives the reconfiguration execution instruction timing signal S3, cuts the reconfiguration instruction signal S1 held in the reception queue 22 (step S605), and executes the reconfiguration. The instruction signal S1 is output to the packet processing circuit 1 (Step S606).
[0061]
Upon receiving the reconfiguration instruction signal S1, the packet processing circuit 1 performs reconfiguration in the same manner as step 206 in FIG. 4 (step S607).
[0062]
The input packet control unit 21 of the process management control unit 2 outputs the stored packet read instruction signal S7 to the input packet buffer unit 4 after the elapse of T2 or more, similarly to Step 207 in FIG. 4 (Step S608).
[0063]
As described above, according to the instantaneous interruption-free reconfiguration processing method and apparatus according to the embodiment of the present invention, for example, when the switching apparatus 103 is operating, the hardware of the interface control circuits 101A and 101B is used. When the search bit width and search field of the policy control engine are additionally changed, reconfiguration is performed in a state where there is no input packet in the packet processing circuit 1, and the stored packet is read after the reconfiguration is completed. Thus, the desired interface control circuits 101A and 101B can be reconfigured while the terminals 100A and 100B maintain the communication connection. In addition, since the packet is not discarded in the switching device 103, it is possible to prevent a session disconnection between the terminal 100A and the terminal 100B.
[0064]
As described above, the embodiments of the present invention have been described, but the present invention is not limited to the above embodiments, and various modifications are possible. For example, in the above-described embodiment, the configuration of the IP router is described as an example of the switching device system, but another switching device system may be used. In the above embodiment, the maintenance person writes the reconfiguration data from the operation terminal 104 to the configuration memory of the packet processing circuit 1. The data may be written once and then loaded into the configuration memory.
[0065]
【The invention's effect】
As described above, according to the hitless reconfiguration processing method and apparatus of the present invention, the start and the completion of reconfiguration are recognized and controlled, and the packet processing circuit stores the input packets during the reconfiguration. When the reconfiguration is completed, the stored packets are read out, and the reconfiguration can be performed while maintaining the communication connection.Therefore, there is no need to use a redundant configuration of the interface board, resulting in cost reduction in mounting. It becomes possible. Further, the cost burden on the introduction user can be reduced as compared with the act standby node method.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating the principle of the present invention.
FIG. 2 is a diagram illustrating the principle of the present invention when the packet processing circuit outputs a reconfiguration completion signal.
FIG. 3 is a schematic diagram of a switching device system using a hitless reconfiguration processing device according to an embodiment of the present invention.
FIG. 4 is a sequence chart illustrating an input / output procedure of a reconfiguration instruction signal.
FIG. 5 is a sequence chart illustrating a processing procedure of an input packet monitoring unit.
FIG. 6 is a flowchart illustrating a processing procedure of a buffer control unit.
FIG. 7 is a sequence chart illustrating an input / output procedure of a reconfiguration completion signal.
FIG. 8 is a sequence chart illustrating an input / output procedure of an input packet empty signal.
[Explanation of symbols]
1 Packet processing circuit
2 Process management control unit
3 System processor
4 Input packet buffer
5 Instantaneous interruption reconfiguration processor
21 Input packet control unit
22 Receive queue
23 Reconfiguration signal processing unit
41 Buffer control unit
42 Input packet monitoring unit
43 Input packet storage
100A, 100B terminal
101A, 101B interface circuit
102 switch
103 exchange equipment
104 Operation terminal
S1 reconfiguration instruction signal
S2 Reconfiguration complete signal
S3, S4 Reconfiguration execution instruction timing signal
S5 Input packet empty signal
S6 accumulation instruction signal
S7 Read instruction signal

Claims (14)

A reconfiguration processing device having a process management control unit and an input packet buffer unit performs reconfiguration of a packet processing circuit without an instantaneous interruption while receiving an input packet from a communication network, and transmits it as an output packet. A processing method, wherein a process management control unit receives a reconfiguration instruction signal from the outside and holds it in a reception queue, outputting a storage instruction signal to an input packet buffer unit, the input packet buffer unit Inputting the accumulation instruction signal and accumulating the input packet, wherein the process management control unit determines that the time required for the input packet to pass through a packet processing circuit is T1, Time T1 or more has passed since the signal was output Outputting a reconfiguration instruction signal held in the reception queue to a packet processing circuit, the packet processing circuit receiving the reconfiguration instruction signal and performing reconfiguration, An input packet buffer unit, upon completion of the reconfiguration, reading out the stored packet and transmitting it as an output packet via the packet processing circuit. . A reconfiguration processing device having a process management control unit and an input packet buffer unit performs reconfiguration of a packet processing circuit without an instantaneous interruption while receiving an input packet from a communication network, and transmits it as an output packet. A processing method, wherein a process management control unit receives a reconfiguration instruction signal from the outside and holds it in a reception queue, and an input packet buffer unit is required for the input packet to pass through a packet processing circuit. When the time is T1, a timing at which an input packet is not received continuously for a time equal to or longer than T1 from the communication network is extracted, and at that timing, the input packet is accumulated and a reconfiguration execution instruction timing signal is output. The process management Outputting the reconfiguration execution instruction timing signal to the process management control unit, and outputting the reconfiguration instruction signal held in the reception queue to a packet processing circuit. A step in which the packet processing circuit performs the reconfiguration by inputting the reconfiguration instruction signal; and, when the reconfiguration is completed, the input packet buffer unit reads out the stored packet and outputs the packet as an output packet. Transmitting the data via the packet processing circuit. A reconfiguration processing device having a process management control unit and an input packet buffer unit performs reconfiguration of a packet processing circuit without an instantaneous interruption while receiving an input packet from a communication network, and transmits it as an output packet. A processing method, wherein a process management control unit receives a reconfiguration instruction signal from the outside and holds the signal in a reception queue; and an input packet buffer unit stores a buffer used to store the input packet. Monitoring the size; if the buffer size is zero, start accumulating the input packet and start counting the elapsed time; and set the time required for the input packet to pass through the packet processing circuit to T1. When the count value is higher than T1 Is smaller and the buffer size is smaller than a preset upper limit value of the buffer size, the accumulation of the input packets is continued, the count value is smaller than T1, and the buffer size becomes the upper limit value. If they are equal, the stored packet is read and transmitted as an output packet through the packet processing circuit, and when the buffer size becomes zero, the count value is reset, the count value is equal to T1, and When the buffer size is smaller than the upper limit value, outputting a reconfiguration execution instruction timing signal to a process management control unit and resetting the count value; and Input an execution instruction timing signal and Outputting the reconfiguration instruction signal held in the storage device to the packet processing circuit; and inputting the reconfiguration instruction signal and performing reconfiguration. Reconfiguration processing method. 4. The reconfiguration processing method according to claim 3, wherein the input packet buffer unit outputs a reconfiguration execution instruction timing signal to a process management control unit, and is completed after the packet processing circuit starts reconfiguration. If the size of the input packets received and stored continuously from the communication network is Q within the time required to perform the operation, the count value is equal to T1, and the buffer size is increased from the upper limit value. A reconfiguration processing method, wherein the value is smaller than a value obtained by subtracting Q. A reconfiguration processing device having a process management control unit and an input packet buffer unit performs reconfiguration of a packet processing circuit without an instantaneous interruption while receiving an input packet from a communication network, and transmits it as an output packet. A processing method, wherein the process management control unit receives a reconfiguration instruction signal from the outside and holds the signal in a reception queue, and the packet processing circuit does not have an input packet to be processed in the packet processing circuit. Outputting an input packet empty signal to the input packet buffer unit, the input packet buffer unit inputs the input packet empty signal to start accumulating the input packet, and executes a reconfiguration execution instruction timing. Signal the process management Outputting the reconfiguration execution instruction timing signal to the process management control unit, and outputting the reconfiguration instruction signal held in the reception queue to a packet processing circuit. A step in which the packet processing circuit performs the reconfiguration by inputting the reconfiguration instruction signal; and, when the reconfiguration is completed, the input packet buffer unit reads out the stored packet and outputs the packet as an output packet. Transmitting the data via the packet processing circuit. 6. The reconfiguration processing method according to claim 1, wherein the time from when the process management control unit starts reconfiguration of the packet processing circuit to when the process management control unit completes reconfiguration is defined as T <b> 2. Outputting a read instruction signal to an input packet buffer unit when a time equal to or longer than T2 has elapsed after outputting the reconfiguration instruction signal to the packet processing circuit; and Receiving a read instruction signal, reading the stored packet, and transmitting the read packet as an output packet via the packet processing circuit. 6. The reconfiguration processing method according to claim 1, wherein the packet processing circuit outputs a reconfiguration completion signal to the process management control unit when reconfiguration is completed. Wherein the process management control unit inputs the reconfiguration completion signal and outputs a read instruction signal to the input packet buffer unit, and the input packet buffer unit inputs the read instruction signal, Reading out the stored packet and transmitting it as an output packet through the packet processing circuit. A reconfiguration processing device that performs reconfiguration of a packet processing circuit without instantaneous interruption while receiving an input packet from a communication network and transmits the reconfigured packet processing circuit as an output packet through the packet processing circuit. Has a process management control unit and an input packet buffer unit, the process management control unit includes a reception queue for holding a reconfiguration instruction signal, and an input packet control unit for outputting a storage instruction signal to the input packet buffer unit. And receiving the reconfiguration instruction signal from the outside and holding it in a reception queue. When the time required for the input packet to pass through the packet processing circuit is T1, the input packet control unit When the time of T1 or more has passed since the signal was output A reconfiguration signal processing unit that outputs a reconfiguration instruction signal held in the reception queue to a packet processing circuit to perform reconfiguration, and the input packet buffer unit includes the accumulation instruction signal And an input packet storage unit for storing the input packet, reading the stored packet when the reconfiguration is completed, and transmitting the read packet as an output packet through the packet processing circuit. Reconfiguration processing device. A reconfiguration processing device that performs reconfiguration of a packet processing circuit without instantaneous interruption while receiving an input packet from a communication network and transmits the reconfigured packet processing circuit as an output packet through the packet processing circuit. Has a process management control unit and an input packet buffer unit, and the process management control unit receives the reconfiguration instruction signal from the outside and stores the reconfiguration instruction signal in the reception queue. And a reconfiguration signal processing unit that, when receiving the reconfiguration execution instruction timing signal, outputs the reconfiguration instruction signal held in the reception queue to the packet processing circuit to perform the reconfiguration. Have The packet buffer unit stores the input packet when receiving an instruction to store the input packet, reads out the stored packet when the reconfiguration is completed, and transmits the read packet as an output packet via the packet processing circuit. When the time required for the input packet to pass through the packet processing circuit is defined as T1, a timing at which the input packet is not continuously received from the communication network for a time equal to or longer than T1 is extracted. An input packet monitoring unit that outputs an instruction to store the input packet to the input packet storage unit and outputs a reconfiguration execution instruction timing signal to the process management control unit. Processing unit. A reconfiguration processing device that performs reconfiguration of a packet processing circuit without instantaneous interruption while receiving an input packet from a communication network and transmits the reconfigured packet processing circuit as an output packet through the packet processing circuit. Has a process management control unit and an input packet buffer unit, and the process management control unit receives the reconfiguration instruction signal from the outside and stores the reconfiguration instruction signal in the reception queue. And a reconfiguration signal processing unit that, when receiving the reconfiguration execution instruction timing signal, outputs the reconfiguration instruction signal held in the reception queue to the packet processing circuit to perform the reconfiguration. Have The packet buffer unit inputs an instruction to accumulate the input packet, accumulates the input packet, inputs an instruction to read the accumulated packet, reads the accumulated packet, and executes the packet processing circuit as an output packet. An input packet accumulating unit for transmitting to the communication network via the communication network, and monitoring a buffer size, which is a used amount of a buffer for accumulating the input packet; The output value is output to the packet storage unit, and counting of the elapsed time is started. When the time required for the input packet to pass through the packet processing circuit is T1, the count value is smaller than T1 and the buffer size is smaller than T1. Is smaller than a preset upper limit value of the buffer size, the input packet If the count value is smaller than T1 and the buffer size is equal to the upper limit value, an instruction to read the stored packets is output to the input packet storage unit, and the buffer size is output. Becomes zero, resets the count value, and outputs a reconfiguration execution instruction timing signal to the process management control unit when the count value is equal to T1 and the buffer size is smaller than the upper limit value, A reconfiguration processing device comprising: a buffer control unit that resets the count value. 11. The reconfiguration processing device according to claim 10, wherein the buffer control unit of the input packet buffer unit outputs a reconfiguration execution instruction timing signal to a process management control unit, when the packet processing circuit performs the reconfiguration. The count value is equal to T1 when the size of the input packet continuously received and stored from the communication network is set to Q within the time from the start to completion of the communication network, and A reconfiguration processing device, wherein the buffer size is smaller than a value obtained by subtracting Q from an upper limit value. A reconfiguration processing device that reconfigures a packet processing circuit without interruption while receiving an input packet from a communication network and transmits the reconfigured packet processing circuit as an output packet via the packet processing circuit. Has a process management control unit and an input packet buffer unit, and the process management control unit receives the reconfiguration instruction signal from the outside and stores the reconfiguration instruction signal in the reception queue. And a reconfiguration signal processing unit that, when receiving the reconfiguration execution instruction timing signal, outputs the reconfiguration instruction signal held in the reception queue to the packet processing circuit to perform the reconfiguration. Have The packet buffer unit stores the input packet when receiving an instruction to store the input packet, reads out the stored packet when the reconfiguration is completed, and outputs the read packet as an output packet to the communication network via the packet processing circuit. An input packet storage unit for transmitting, and a signal for storing the input packet when the input packet empty signal transmitted when there is no input packet to be subjected to packet processing is received from the packet processing circuit. And a buffer control unit for outputting a reconfiguration execution instruction timing signal to the process management control unit. 13. The reconfiguration processing device according to claim 8, wherein the process management control unit defines a time period from the start of reconfiguration of the packet processing circuit to the completion thereof as T2. The input packet control unit that outputs a read instruction signal to an input packet buffer unit when a time equal to or longer than T2 has elapsed after outputting the reconfiguration instruction signal to the packet processing circuit; A reconfiguration processing device comprising: an input packet storage unit that receives the read instruction signal, reads the stored packet, and transmits the read packet as an output packet via the packet processing circuit. . 13. The reconfiguration processing device according to claim 8, wherein the process management control unit outputs a reconfiguration completion signal output from the packet processing circuit when the reconfiguration is completed. And an input packet control unit that outputs a read instruction signal to the input packet buffer unit. The input packet buffer unit receives the read instruction signal, reads the stored packets, and outputs A reconfiguration processing device, comprising: an input packet storage unit that transmits a packet via the packet processing circuit.

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