JP3801994B2 - Non-instantaneous reconfiguration processing method and apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a reconfiguration processing method and apparatus for a packet processing circuit provided in a communication network device, and in particular, a communication table (for example, a session state table, a communication protocol state table, etc.) required for end-end communication by reconfiguration. When the communication table is not changed or when the communication table is not held, the reconfiguration is possible while maintaining the communication link session.
[0002]
[Prior art]
Conventionally, reconfiguration of a network device having a packet processing circuit capable of reconfiguring a part of an internal circuit has been performed by making the network device a redundant configuration. In this case, the network equipment is configured by making the programmable devices in the interface board redundant to the active system and the standby system. When reconfiguration work occurs in the active system, the programmable device from the active system to the standby system is programmable. By switching to the device, reconfiguration was realized without interruption.
[0003]
In such a processing system with a redundant configuration, for example, a cell switch for receiving the same cell input and a read control unit corresponding to the cell switch are provided in two systems, an active system and a standby system. In a system in which a cell stored in a buffer memory in a cell switch is read out and one of the cell outputs is selected and switched without interruption, a read control signal is sent even when the write signal storage memory is empty As a result, some cells accumulated in the buffer memory due to malfunctions due to noise or the like are discarded, and the active system and the standby system are reliably synchronized (see Patent Document 1).
[0004]
In addition, in the redundant configuration system of ATM switches including an active system switch unit and a standby system switch unit, the cell storage states are combined in order of increasing delay priority class between the queues of the same delay priority class of each switch unit. Even if it has a delay priority control function by performing redundant switching from the active system to the standby system in response to detection of the switching control cell of the lowest delay priority class, no cell delay occurs. Some switches perform redundancy switching without interruption (see Patent Document 2).
[0005]
On the other hand, in the configuration processing method, for example, by recognizing that the programmable device is being configured from the connection state of the configuration cable and turning off the connection between the programmable device and the circuit, the circuit malfunctions. (See Patent Document 3).
[0006]
[Patent Document 1]
JP 7-30545 A (paragraphs [0025] [0026] [0040] [0041], FIG. 1 and FIG. 2)
[Patent Document 2]
JP-A-10-190683 (paragraphs [0034] [0035], FIG. 1)
[Patent Document 3]
JP 11-298549 A (paragraphs [0029] [0030])
[0007]
[Problems to be solved by the invention]
However, in the conventional reconfiguration processing method using a redundant configuration, it is necessary to mount a plurality of programmable devices on the interface board, which increases the mounting area and increases the cost. In addition, when this interface board is recognized as a single cluster system, the interface board is equipped with a plurality of programmable devices, but has only the performance of a single-system programmable device. There was a problem of economy.
[0008]
For this reason, there is a reconfiguration technology that can perform reconfiguration without interruption without maintaining a communication link session for end-end communication by using a single interface board with a non-redundant configuration without using such a redundant configuration. It is requested.
[0009]
The present invention has been made in consideration of such circumstances, and an object of the present invention is to provide an uninterruptible reconfiguration processing method for reconfiguring a packet processing circuit while maintaining a communication connection by a single configuration. And providing an apparatus.
[0010]
[Means for Solving the Problems]
The present invention will be described with reference to the principle diagrams shown in FIGS.
The packet processing circuit 1 has a function of inputting a packet, performing a predetermined process on the input packet and outputting the packet as an output packet, and a memory for reconfiguration. If the session state table, communication protocol table, etc.) are not changed or the communication table is not retained, the reconfiguration is performed by inputting the reconfiguration instruction signal S1 and the reconfiguration is completed. And a function of outputting a completion signal S2. The system processor 3 has a function of transmitting a reconfiguration instruction signal S1 and causing the packet processing circuit 1 to perform reconfiguration.
[0011]
The uninterruptible reconfiguration processing device 5 includes a process management control unit 2 and an input packet buffer unit 4. The process management control unit 2 includes a reception queue 22 that holds a reconfiguration instruction signal S1 received from the system processor, an input packet control unit 21 that outputs an accumulation instruction signal S6 and a read instruction signal S7, and a reconfiguration execution instruction. And a reconfiguration signal processing unit 23 for inputting timing signals S3 and S4 and a reconfiguration completion signal S2 and outputting a reconfiguration instruction signal S1.
[0012]
The input packet buffer unit 4 outputs the reconfiguration execution instruction timing signal S4, receives the accumulation instruction signal S6 and the input packet empty signal S5, and the accumulation instruction signal S6, and executes the reconfiguration execution. An input packet monitoring unit 42 that outputs an instruction timing signal S3 and an input packet storage unit 43 that inputs an accumulation instruction signal S6 and a read instruction signal S7, accumulates and reads input packets received from the outside, and the like. Further, the buffer control unit 41 and the input packet monitoring unit 42 output an instruction to store the input packet and an instruction to read out the stored packet to the input packet storage unit 43, and the input packet storage unit 43 inputs these instructions. Under the above configuration, the present invention will be described below.
[0013]
In the first aspect of the present invention, the reconfiguration processing device 5 having the process management control unit 2 and the input packet buffer unit 4 reconfigures the packet processing circuit 1 without interruption while receiving the input packet from the communication network. The process management control unit 2 receives the reconfiguration instruction signal S1 from the outside and holds it in the reception queue 22, and the accumulation instruction signal S6. A step of outputting to the input packet buffer unit 4; a step of the input packet buffer unit 4 receiving the storage instruction signal S6 to store the input packet; and the process management control unit 2 When the time required to pass through the processing circuit 1 is T1, A step of outputting the reconfiguration instruction signal S1 held in the reception queue 22 to the packet processing circuit 1 when a time equal to or greater than T1 has elapsed since the output of the accumulation instruction signal S6; and the packet processing circuit 1 The reconfiguration instruction signal S1 is input to perform reconfiguration, and when the reconfiguration is completed, the input packet buffer unit 4 reads the accumulated packet and outputs the packet as an output packet. And a step of transmitting via the circuit 1. Thereby, reconfiguration can be performed while maintaining the end-to-end communication link in the communication network. Also, reconfiguration is performed when the packet processing circuit 1 does not hold a communication table such as a session state table necessary for the end-to-end communication of the IP packet communication process while maintaining the communication connection, or is not changed by reconfiguration. be able to.
[0014]
In the invention of claim 2, the reconfiguration processing device 5 having the process management control unit 2 and the input packet buffer unit 4 reconfigures the packet processing circuit 1 without interruption while receiving the input packet from the communication network. The process management control unit 2 receives the reconfiguration instruction signal S1 from the outside and holds it in the reception queue 22, and the input packet buffer unit 4 However, when the time required for the input packet to pass through the packet processing circuit 1 is T1, the timing at which the input packet is not continuously received from the communication network for a time equal to or longer than T1 is extracted. Accumulate the input packets and reconfigure A step of outputting a row instruction timing signal S3 to the process management control unit 2, and the process management control unit 2 inputs the reconfiguration execution instruction timing signal S3 and holds the reconfiguration held in the reception queue 22 The packet processing circuit 1 outputs the configuration instruction signal S1 to the packet processing circuit 1, the packet processing circuit 1 inputs the reconfiguration instruction signal S1 and performs reconfiguration, and the input packet buffer unit 4 When the reconfiguration is completed, the stored packet is read out and transmitted as an output packet via the packet processing circuit 1. As a result, the reconfiguration instruction signal S1 held in the reception queue 22 can be pruned at a timing when there is no input packet, and reconfiguration can be performed while maintaining the end-to-end communication link session. Further, the input packet buffer unit 4 can determine the reconfiguration execution instruction timing and notify it to the process management control unit 2, and perform reconfiguration at a timing when there is no continuous input packet. The buffer amount of the buffer unit 4 can be reduced.
[0015]
According to the invention of claim 3, the reconfiguration processing device 5 having the process management control unit 2 and the input packet buffer unit 4 reconfigures the packet processing circuit 1 without interruption while receiving the input packet from the communication network. The process management control unit 2 receives the reconfiguration instruction signal S1 from the outside and holds it in the reception queue 22, and the input packet buffer unit 4 Monitoring the buffer size, which is the amount of buffer used to store the input packet, and when the buffer size is zero, starting to store the input packet and starting counting elapsed time; The time required for an input packet to pass through the packet processing circuit 1 If the count value is smaller than T1 and the buffer size is smaller than a preset upper limit value of the buffer size, the input packet is continuously accumulated, and the count value is equal to T1. And when the buffer size is equal to the upper limit value, the accumulated packet is read out and transmitted as an output packet through the packet processing circuit 1, and when the buffer size becomes zero, the count value When the count value is equal to T1 and the buffer size is smaller than the upper limit value, a reconfiguration execution instruction timing signal S4 is output to the process management control unit 2 and the count value is reset. And the process management control unit 2 performs the reconfiguration Receiving a reconfiguration instruction timing signal S4 and outputting the reconfiguration instruction signal S1 held in the reception queue 22 to the packet processing circuit 1, and the packet processing circuit 1 including the reconfiguration instruction signal S1. And a step of performing reconfiguration by inputting S1. As a result, even if the upper limit value of the buffer size is relatively small, it is possible to forcibly perform reconfiguration at a timing when there is no continuous input packet, and to generate a desired reconfiguration execution instruction timing. .
[0016]
According to a fourth aspect of the present invention, in the reconfiguration processing method according to the third aspect, the input packet buffer unit 4 outputs a reconfiguration execution instruction timing signal S4 to the process management control unit 2 in the packet processing circuit. When the size of the input packet accumulated by receiving input packets continuously from the communication network within the time from the start of reconfiguration to the completion of 1 is Q, the count value is T1. And the buffer size is smaller than the value obtained by subtracting Q from the upper limit value. As a result, the buffer size does not reach its upper limit before reconfiguration is completed, and there is no loss of input packets. Therefore, the end-to-end communication link in the communication network is reliably maintained for reconfiguration. be able to.
[0017]
In the invention of claim 5, the reconfiguration processing device 5 having the process management control unit 2 and the input packet buffer unit 4 reconfigures the packet processing circuit 1 without interruption while receiving the input packet from the communication network. The process management control unit 2 receives the reconfiguration instruction signal S1 from the outside and holds it in the reception queue 22, and the packet processing circuit 1 When there is no input packet to be processed in the packet processing circuit 1, the step of outputting the input packet empty signal S5 to the input packet buffer unit 4; and the input packet buffer unit 4 includes the input packet empty signal S5. To start storing the input packet and Output the configuration execution instruction timing signal S4 to the process management control unit 2, and the process management control unit 2 inputs the reconfiguration execution instruction timing signal S4 and receives the reconfiguration held in the reception queue 22 A step of outputting a configuration instruction signal S1 to the packet processing circuit 1, a step in which the packet processing circuit 1 inputs the reconfiguration instruction signal S1 to perform reconfiguration, and the input packet buffer unit 4 includes: When the reconfiguration is completed, the stored packet is read out and transmitted as an output packet through the packet processing circuit 1. Thereby, the desired reconfiguration execution instruction timing can be generated also by the input packet empty signal S5 notifying that the input packet from the packet processing circuit 1 is empty.
[0018]
A sixth aspect of the present invention is the reconfiguration processing method according to any one of the first, second, and fifth aspects, wherein the process management control unit 2 starts reconfiguration of the packet processing circuit 1. When the time from completion to completion is T2, when the time equal to or greater than T2 has elapsed since the reconfiguration instruction signal S1 was output to the packet processing circuit 1, the read instruction signal S7 is input to the input packet buffer unit 4 And the packet buffer unit 4 receives the read instruction signal S7, reads the accumulated packet, and transmits the packet as an output packet via the packet processing circuit 1. It is characterized by this. Thereby, it is possible to perform reconfiguration while maintaining the end-to-end communication link in the communication network by time control based on an arbitrary set time (T2).
[0019]
A seventh aspect of the present invention is the reconfiguration processing method according to any one of the first, second, and fifth aspects, wherein when the packet processing circuit 1 completes the reconfiguration, the reconfiguration completion signal S2 is transmitted. A step of outputting to the process management control unit 2, a step of the process management control unit 2 inputting the reconfiguration completion signal S2 and outputting a read instruction signal S7 to the input packet buffer unit 4, and the input packet The buffer unit 4 includes the step of inputting the read instruction signal S7, reading the accumulated packet, and transmitting the packet as an output packet via the packet processing circuit 1. . Thereby, the process management control unit 2 does not perform time control based on an arbitrary set time (T2), but instructs the reading of the packets stored in the input packet buffer unit 4 after the actual reconfiguration is completed. Therefore, it is possible to reliably perform reconfiguration while maintaining the end-to-end communication link in the communication network.
[0020]
The invention according to claim 8 is a reconfiguration process in which the packet processing circuit 1 is reconfigured without interruption while receiving an input packet from a communication network, and is transmitted as an output packet through the packet processing circuit 1. In the device 5, the reconfiguration processing device 5 includes a process management control unit 2 and an input packet buffer unit 4. The process management control unit 2 includes a reception queue 22 that holds a reconfiguration instruction signal S1. The input packet control unit 21 that outputs the accumulation instruction signal S6 to the input packet buffer unit 4, and the reconfiguration instruction signal S1 received from the outside and held in the reception queue 22, and the input packet is transmitted to the packet processing circuit 1 When the time required to pass through is T1, the input packet When a time equal to or longer than T1 has elapsed after the control unit 22 outputs the accumulation instruction signal S6, the reconfiguration instruction signal S1 held in the reception queue 22 is output to the packet processing circuit 1 to perform reconfiguration. A reconfiguration signal processing unit 23 to perform, the input packet buffer unit 4 receives the accumulation instruction signal S6, accumulates the input packet, and when the reconfiguration is completed, the accumulated packet is stored. It has an input packet storage unit 43 that reads out a packet and transmits it as an output packet via the packet processing circuit 1. The same effect as that of the first aspect of the invention can be obtained.
[0021]
The invention according to claim 9 is a reconfiguration process in which the packet processing circuit 1 is reconfigured without interruption while receiving an input packet from the communication network, and is transmitted as an output packet through the packet processing circuit 1. In the device 5, the reconfiguration processing device 5 includes a process management control unit 2 and an input packet buffer unit 4. The process management control unit 2 includes a reception queue 22 that holds a reconfiguration instruction signal S1. The reconfiguration instruction signal S1 received from the outside is held in the reception queue 22, and when the reconfiguration execution instruction timing signal S3 is input, the reconfiguration instruction signal S1 held in the reception queue 22 is received. Output to packet processing circuit 1 for reconfiguration The input packet buffer unit 4 stores the input packet when receiving an instruction to store the input packet, and stores the input packet when the reconfiguration is completed. The packet is read out and transmitted as an output packet via the packet processing circuit 1, and when the time required for the input packet to pass through the packet processing circuit 1 is T1, the communication A timing at which the input packet is not received continuously for a time equal to or longer than T1 from the network is extracted, and at this timing, an instruction to store the input packet is output to the input packet storage unit 43, and a reconfiguration execution instruction timing signal The input parameter for outputting S3 to the process management control unit 2 It is characterized in that it has a Tsu preparative monitoring unit 42. The same effects as those of the invention of claim 2 are obtained.
[0022]
The invention according to claim 10 is a reconfiguration process in which the packet processing circuit 1 is reconfigured without interruption while receiving an input packet from a communication network, and is transmitted as an output packet through the packet processing circuit 1. In the device 5, the reconfiguration processing device 5 includes a process management control unit 2 and an input packet buffer unit 4. The process management control unit 2 includes a reception queue 22 that holds a reconfiguration instruction signal S1. The reconfiguration instruction signal S1 received from the outside is held in the reception queue 22, and when the reconfiguration execution instruction timing signal S4 is input, the reconfiguration instruction signal S1 held in the reception queue 22 is received. Output to packet processing circuit 1 for reconfiguration A reconfiguration signal processing unit 23 for performing the configuration, and the input packet buffer unit 21 inputs an instruction to store the input packet, stores an input packet, and instructs to read the stored packet An input packet storage unit 43 that reads out the stored packet and transmits it as an output packet to the communication network via the packet processing circuit 1, and a buffer size that is a usage amount of the buffer that stores the input packet. When the buffer size is zero, an instruction to store the input packet is output to the input packet storage unit 43, and counting of elapsed time is started, and the input packet passes through the packet processing circuit. When the time required for T is T1, the count value is smaller than T1 and the battery is When the buffer size is smaller than the preset upper limit value of the buffer size, the input packet is continuously accumulated. When the count value is smaller than T1 and the buffer size is equal to the upper limit value, the accumulation is continued. An instruction to read the received packet is output to the input packet storage unit 43, and when the buffer size becomes zero, the count value is reset, the count value is equal to T1, and the buffer size is smaller than the upper limit value. In this case, the reconfiguration execution instruction timing signal S4 is output to the process management control unit 2 and the buffer control unit 41 resets the count value. The same effect as that of the third aspect of the invention can be attained.
[0023]
According to an eleventh aspect of the present invention, in the reconfiguration processing device 5 according to the tenth aspect, the buffer control unit 41 of the input packet buffer unit 4 outputs a reconfiguration execution instruction timing signal S4 to the process management control unit 2. This is because Q is the size of the input packet that is continuously received and stored from the communication network within the time from when the packet processing circuit 1 starts reconfiguration to when it is completed. In this case, the count value is equal to T1, and the buffer size is smaller than the value obtained by subtracting Q from the upper limit value. The same effect as that of the fourth aspect of the invention can be attained.
[0024]
The invention of claim 12 is a reconfiguration process in which the packet processing circuit 1 is reconfigured without interruption while receiving an input packet from a communication network, and is transmitted as an output packet through the packet processing circuit 1. In the device 5, the reconfiguration processing device 5 includes a process management control unit 2 and an input packet buffer unit 4. The process management control unit 2 includes a reception queue 22 that holds a reconfiguration instruction signal S1. The reconfiguration instruction signal S1 received from the outside is held in the reception queue 22, and when the reconfiguration execution instruction timing signal S4 is input, the reconfiguration instruction signal S1 held in the reception queue 22 is received. Output to packet processing circuit 1 for reconfiguration A reconfiguration signal processing unit 23 for performing reconfiguration, and the input packet buffer unit 4 stores an input packet when an instruction to store the input packet is input, and when the reconfiguration is completed, An input packet storage unit 43 that reads the stored packet and transmits it as an output packet to the communication network via the packet processing circuit 1; and when there is no input packet to be subjected to packet processing from the packet processing circuit 1 When an input packet empty signal S5 is input, a buffer control for outputting a signal for accumulating the input packet to the input packet accumulating unit 43 and outputting a reconfiguration execution instruction timing signal S4 to the process management control unit 2 It has the part 41 and is characterized by having The same effect as that of the fifth aspect of the invention can be attained.
[0025]
According to a thirteenth aspect of the present invention, in the reconfiguration processing device 5 according to any one of the eighth, ninth, and twelfth aspects, the process management control unit 2 starts reconfiguration of the packet processing circuit 1. When the time from completion to completion is T2, when the time equal to or greater than T2 has elapsed since the reconfiguration instruction signal S1 was output to the packet processing circuit 1, the input instruction buffer S7 4, and the input packet buffer unit 4 inputs the read instruction signal S 7, reads the accumulated packet, and outputs it as an output packet via the packet processing circuit 1. It has an input packet storage unit 43 for transmission. The same effect as that of the sixth aspect of the invention can be attained.
[0026]
According to a fourteenth aspect of the present invention, in the reconfiguration processing device 5 according to any one of the eighth, ninth, and twelfth aspects, the process management control unit 2 has completed the reconfiguration from the packet processing circuit 1 A reconfiguration completion signal S2 that is output from time to time, and an input packet control unit 21 that outputs a read instruction signal S7 to the input packet buffer unit 4. The input packet buffer unit 4 includes the read instruction It has an input packet storage unit 43 that receives the signal S7, reads the stored packet, and transmits it as an output packet via the packet processing circuit 1. The same effect as that of the seventh aspect of the invention can be attained.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 3 is a schematic diagram of an exchange system using the non-instantaneous reconfiguration processing device according to the embodiment of the present invention. The exchange apparatus system includes terminals 100A and 100B, an exchange apparatus 103, and an operation terminal 104. The exchange device 103 is, for example, an IP router or an ATM exchange, has interface control circuits 101A and 101B, and a switch 102, and communicates with the terminals 100A and 100B via a network. The operation terminal 104 communicates with the switching apparatus 103 and instructs the interface circuits 101A and 101B to perform reconfiguration.
[0028]
The interface control circuit 101A has a communication interface function between the switch 102 and the terminal 100A, and the interface control circuit 101B has a communication interface function between the switch 102 and the terminal 100B. The interface control circuits 101A and 101B include a hardware routing engine, a hardware policy control engine, and the like, and are configured by devices capable of reconfiguring a part of the internal circuit. Note that the switch 102 can also reconfigure a part of the internal circuit, like the interface control circuit.
[0029]
The interface control circuits 101A and 101B and the switch 102 are formed on a printed circuit board, respectively. As shown in FIG. 1, the packet processing circuit 1 and the non-instantaneous device including the configuration memory, the configuration control circuit, and the programmable device are provided. The reconfiguration processing device 5 is included. Here, the configuration memory stores data necessary for the configuration. When the configuration control circuit receives the reconfiguration instruction signal S1, the configuration memory reads out the data from the configuration memory according to the instruction of the signal and resets the programmable device. Has a function to perform configuration. The programmable device also has a function of performing predetermined processing on the input packet and outputting the output packet to the communication network.
[0030]
Hereinafter, an example of a sequence operation during reconfiguration will be described with reference to FIG.
A case where the search bit width and the search field of the hardware policy control engine are additionally changed in the switching apparatus system in which the interface control circuits 101A and 101B are mounted in the switching apparatus 103 as shown in FIG. 3 will be described. For example, application layer data such as a URL (Uniform Resource Locator) in an IP packet transmitted and received between the terminals 100A and 100B is added as a search field so that the interface control circuits 101A and 101B can search.
[0031]
First, the maintenance person designates the interface control circuits 101A and 101B using the operation terminal 104, and writes reconfiguration data in the configuration memory so that a URL as a search field can be searched from the interface control circuits 101A and 101B. . Then, the reconfiguration instruction signal S1 is output from the operation terminal 104 at an arbitrary timing by the operation of the operation terminal 104 by the maintenance person (step S201).
[0032]
Upon receiving the reconfiguration instruction signal S1 output from the operation terminal 104, the uninterruptible reconfiguration processing device 5 of the interface control circuits 101A and 101B holds it in the reception queue 22 (step S202). The input packet control unit 21 in the process management control unit 2 of the uninterruptible reconfiguration processing device 5 outputs an input packet accumulation instruction signal S 6 to the input packet buffer unit 4. When receiving the accumulation instruction signal S6, the input packet accumulation unit 43 of the input packet buffer unit 4 accumulates the received input packet by the FIFO method (step S203).
[0033]
After elapse of time (T1 time) required for the input packet to pass through the packet processing circuit 1, the reconfiguration signal processing unit 23 of the process management control unit 2 receives the reconfiguration instruction signal S1 held in the reception queue. Cutting (step S204), a reconfiguration instruction signal S1 is output to the packet processing circuit 1 (S205).
[0034]
When the packet processing circuit 1 inputs the reconfiguration instruction signal S1, the reconfiguration data stored in the configuration memory is set in the programmable device by the reconfiguration control process, and the reconfiguration of the packet processing circuit 1 is performed. This is performed (step S206).
[0035]
The input packet control unit 21 of the process management control unit 2 takes a time (T2 time) required for the reconfiguration of the packet processing circuit 1 to be completed after the reconfiguration signal processing unit 23 outputs the reconfiguration instruction signal S1. After the above, the stored packet read instruction signal S7 is output to the input packet buffer unit 4 (step S207).
[0036]
As a result, in the interface control circuits 101A and 101B, URL (Uniform Resource Locator) data in the IP packet transmitted and received between the terminals 100A and 100B is added to the search field, and the URL data can be searched. .
[0037]
Next, with reference to FIG. 5, the sequence operation at the time of reconfiguration when the input packet monitoring unit 42 is provided in the uninterruptible reconfiguration processing device 5 will be described.
[0038]
Similar to step 201 shown in FIG. 4, after the maintenance person writes the reconfiguration data into the configuration memory of the interface control circuits 101A and 101B using the operation terminal 104, the operation terminal 104 follows the operation of the maintenance person. The reconfiguration instruction signal S1 is output from the operation terminal 104 at an arbitrary timing (step S301).
[0039]
Upon receiving the reconfiguration instruction signal S1 output from the operation terminal 104, the uninterruptible reconfiguration processing device 5 of the interface control circuits 101A and 101B holds it in the reception queue 22 (step S302). The input packet control unit 21 of the process management control unit 2 outputs an input packet accumulation instruction signal S 6 to the input packet buffer unit 4. When receiving the accumulation instruction signal S6, the input packet monitoring unit 42 of the input packet buffer unit 4 monitors the input packet (step S30).
[0040]
The input packet monitoring unit 42 extracts the timing when there is no input packet continuous for T1 time or longer, and sets the timing as the reconfiguration execution instruction timing. Then, the input packet storage unit 43 of the input packet buffer unit stores the input packet (step S304).
[0041]
The input packet monitoring unit 42 of the input packet buffer unit 4 notifies the process management control unit 2 of the reconfiguration execution instruction timing signal S3 in order to notify the timing to reap the reconfiguration instruction signal S1 held in the reception queue 22. Output. The reconfiguration signal processing unit 23 of the process management control unit 2 receives the reconfiguration execution instruction timing signal S3, cuts the reconfiguration instruction signal S1 held in the reception queue 22 (step S305), and performs reconfiguration. The instruction signal S1 is output to the packet processing circuit 1 (S306).
[0042]
When the packet processing circuit 1 receives the reconfiguration instruction signal S1, the packet processing circuit 1 performs reconfiguration of the packet processing circuit 1 as in step 206 shown in FIG. 4 (step S307).
[0043]
The input packet control unit 21 of the process management control unit 2 outputs the stored packet read instruction signal S7 to the input packet buffer unit 4 after the elapse of T2 time or more, similarly to step 207 shown in FIG. 4 (step S308). .
[0044]
Next, with reference to FIG. 6, the sequence operation at the time of reconfiguration in the case where the buffer control unit 41 is provided in the uninterruptible reconfiguration processing device 5 will be described.
[0045]
This sequence operation starts when the input packet buffer unit 4 is in the input packet reading non-stop state (step S400).
The buffer control unit 41 of the input packet buffer unit 4 proceeds to the accumulation start determination step when the accumulation instruction signal S6 is input from the process management control unit 2, and when the signal is not input, Wait for input (step S401).
[0046]
Here, the buffer control unit 41 includes a counter that counts an elapsed time period T1 that is a time period necessary for an input packet to pass through the packet processing circuit 1, and a buffer size (buffer usage amount) for storing the input packet. And buffer size determining means. When the buffer size determining means of the buffer control unit 41 determines that the buffer size is zero (buffer is empty), it determines the start of accumulation and proceeds to the next step. On the other hand, if it is determined that the buffer size is not zero (the buffer is not empty), the accumulation start cannot be started, and the above accumulation start determination is repeated until the buffer size becomes zero (step S402).
[0047]
If it is determined that the accumulation is started based on the accumulation start determination in step 402, the input packet accumulation unit 43 of the input packet buffer unit 4 is set to the buffer reading stop state and accumulation of the input packet is started. Also, a counter with a T1 time period is started (step S403).
[0048]
When determining that the count value <T1 time and the buffer size <the upper limit value of the buffer size, the buffer control unit causes the input packet storage unit 43 to continue storing the received input packets. If it is determined that the count value = T1 time and the buffer size <the upper limit value of the buffer size, the reconfiguration is possible, and the process proceeds to the next step 405. If it is determined that the count value <T1 time and the buffer size = the upper limit value of the buffer size, it is determined that the accumulation cannot be continued, and the process proceeds to step 406 (step S404).
[0049]
In addition, it is counted when the size of the input packet that is continuously received from the communication network and stored in the time from when the packet processing circuit 1 starts reconfiguration until it is completed is Q. If it is determined that value = T1 time and buffer size <(upper limit value of buffer size) −Q, reconfiguration is possible and the process may proceed to the next step 405.
[0050]
When the buffer control unit 41 determines in step 404 that reconfiguration is possible, the buffer control unit 41 notifies the process management control unit 2 of the timing to reap the reconfiguration instruction signal S1 held in the reception queue 22, so that reconfiguration execution is performed. The instruction timing signal S3 is output (step S405).
[0051]
On the other hand, when the buffer control unit 41 determines in step 404 that the accumulation cannot be continued, the input packet accumulation unit 43 stops the accumulation of the input packet and performs the input packet reading process. If the buffer control unit 41 determines that the buffer size is zero (the buffer is empty), the buffer control unit 41 resets the counter, returns to step 402, and re-determines the accumulation start (step S406).
[0052]
Next, with reference to FIG. 7, a sequence operation of completion of reconfiguration when the process management control unit 2 inputs the reconfiguration completion signal S2 from the packet processing circuit 1 will be described.
[0053]
The reconfiguration signal processing unit 23 of the process management control unit 2 cuts the reconfiguration instruction signal S1 held in the reception queue 22 and outputs the reconfiguration instruction signal S1 to the packet processing circuit 1 (step S501).
[0054]
When the packet processing circuit 1 receives the reconfiguration instruction signal S1, the packet processing circuit 1 performs reconfiguration of the packet processing circuit 1 similarly to step 206 shown in FIG. 4 (step S502).
[0055]
When completing the reconfiguration, the packet processing circuit 1 outputs a reconfiguration completion signal S2 to the operation terminal 104 via the non-instantaneous reconfiguration processing device 5 (step S503). The reconfiguration signal processing unit 23 in the process management control unit 2 of the uninterruptible reconfiguration processing device 5 inputs the reconfiguration completion signal S2 and outputs completion to the input packet control unit 21, and the input packet control unit 21 outputs a stored packet read instruction signal S7 to the input packet buffer unit 4 (step S504).
[0056]
Next, with reference to FIG. 8, a sequence operation in the case of performing reconfiguration based on the input packet null signal S5 output from the packet processing circuit 1 will be described.
[0057]
Similar to step 201 shown in FIG. 4, after the maintenance person writes the reconfiguration data into the configuration memory of the interface control circuits 101A and 101B using the operation terminal 104, the operation terminal 104 follows the operation of the maintenance person. Then, the reconfiguration instruction signal S1 is output from the operation terminal 104 at an arbitrary timing (step S601).
[0058]
When receiving the reconfiguration instruction signal S1 output from the operation terminal 104, the uninterruptible reconfiguration processing device 5 holds the signal in the reception queue 22. The input packet control unit 21 of the process management control unit 2 outputs an input packet accumulation instruction signal S 6 to the input packet buffer unit 4. When receiving the accumulation instruction signal S6, the buffer control unit 41 of the input packet buffer unit 4 monitors the input of the input packet null signal S5 from the packet processing circuit 1 (step S602).
[0059]
The packet processing circuit 1 outputs an input packet empty signal S5 notifying that the input packet is empty to the buffer control unit 41 (step S603). When the buffer control unit 41 receives the input packet null signal S5, the buffer control unit 41 accumulates the input packet (step S604).
[0060]
The buffer control unit 41 outputs a reconfiguration execution instruction timing signal S3 to notify the process management control unit 2 of the timing to reap the reconfiguration instruction signal S1 held in the reception queue 22. The reconfiguration signal processing unit 23 of the process management control unit 2 receives the reconfiguration execution instruction timing signal S3, cuts the reconfiguration instruction signal S1 held in the reception queue 22 (step S605), and performs reconfiguration. The instruction signal S1 is output to the packet processing circuit 1 (step S606).
[0061]
When receiving the reconfiguration instruction signal S1, the packet processing circuit 1 performs reconfiguration as in step 206 in FIG. 4 (step S607).
[0062]
The input packet control unit 21 of the process management control unit 2 outputs a stored packet read instruction signal S7 to the input packet buffer unit 4 after the elapse of T2 time or more, similarly to step 207 in FIG. 4 (step S608).
[0063]
As described above, according to the non-instantaneous reconfiguration processing method and apparatus according to the embodiment of the present invention, for example, when the switching apparatus 103 is operated, the hardware of the interface control circuits 101A and 101B When the search bit width and search field of the policy control engine are added or changed, reconfiguration is performed in the absence of an input packet in the packet processing circuit 1, and the accumulated packet is read after the reconfiguration is completed. Thus, the desired interface control circuits 101A and 101B can be reconfigured while the terminals 100A and 100B maintain the communication connection. In addition, since the packet is not discarded in the switching apparatus 103, session disconnection between the terminal 100A and the terminal 100B can be prevented.
[0064]
Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made. For example, in the above embodiment, the switching device system is taken as an example and the configuration of the IP router is taken as an example, but other switching device systems may be used. Further, in the above embodiment, the maintenance person writes the reconfiguration data from the operation terminal 104 to the configuration memory of the packet processing circuit 1, but from the operation terminal 104 to a memory such as a FROM on the switching apparatus 103. It may be written once and then loaded into the configuration memory.
[0065]
【The invention's effect】
As described above, according to the non-instantaneous reconfiguration processing method and apparatus of the present invention, the start and completion of reconfiguration are recognized and controlled, and the packet processing circuit accumulates input packets during reconfiguration. When the reconfiguration is completed, it is possible to perform reconfiguration while maintaining the communication connection by reading the accumulated packets, so there is no need to take a redundant configuration of the interface board, and the cost can be reduced in terms of mounting. It becomes possible. Moreover, the cost burden to the introduction user can be reduced as compared with the act standby node method.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating the principle of the present invention.
FIG. 2 is a diagram illustrating the principle of the present invention when a packet processing circuit outputs a reconfiguration completion signal.
FIG. 3 is a schematic diagram of an exchange apparatus system using a non-instantaneous reconfiguration processing apparatus according to an embodiment of the present invention.
FIG. 4 is a sequence chart illustrating an input / output procedure of a reconfiguration instruction signal.
FIG. 5 is a sequence chart illustrating a processing procedure of an input packet monitoring unit.
FIG. 6 is a flowchart illustrating a processing procedure of a buffer control unit.
FIG. 7 is a sequence chart for explaining an input / output procedure of a reconfiguration completion signal.
FIG. 8 is a sequence chart illustrating an input / output procedure of an input packet null signal.
[Explanation of symbols]
1 Packet processing circuit
2 Process management control unit
3 System processor
4 Input packet buffer
5 Non-instantaneous reconfiguration processor
21 Input packet controller
22 Receive queue
23 Reconfiguration signal processor
41 Buffer control unit
42 Input packet monitoring unit
43 Input packet storage
100A, 100B terminal
101A, 101B interface circuit
102 switch
103 Exchange device
104 Operation terminal
S1 Reconfiguration instruction signal
S2 Reconfiguration completion signal
S3, S4 Reconfiguration execution instruction timing signal
S5 Input packet empty signal
S6 Accumulation instruction signal
S7 Read instruction signal

Claims (14)

Reconfiguration in which a reconfiguration processing device having a process management control unit and an input packet buffer unit reconfigures a packet processing circuit without interruption while receiving an input packet from a communication network and transmits it as an output packet A processing method in which a process management control unit receives a reconfiguration instruction signal from the outside and holds it in a reception queue, a step of outputting an accumulation instruction signal to an input packet buffer unit, and the input packet buffer unit The step of storing the input packet by inputting the storage instruction signal, and when the process management control unit sets the time required for the input packet to pass through the packet processing circuit to T1, the storage instruction More than T1 has elapsed since the signal was output The step of outputting a reconfiguration instruction signal held in the reception queue to a packet processing circuit, the packet processing circuit inputting the reconfiguration instruction signal and performing reconfiguration, and A reconfiguration processing method comprising: an input packet buffer unit that reads out the accumulated packet when the reconfiguration is completed and transmits the packet as an output packet through the packet processing circuit. . Reconfiguration in which a reconfiguration processing device having a process management control unit and an input packet buffer unit reconfigures a packet processing circuit without interruption while receiving an input packet from a communication network and transmits it as an output packet A processing method in which a process management control unit receives a reconfiguration instruction signal from the outside and holds it in a reception queue, and an input packet buffer unit requires the input packet to pass through a packet processing circuit When the time is T1, the timing at which the input packet is not continuously received from the communication network for the time equal to or longer than T1 is extracted, and at the timing, the input packet is accumulated and the reconfiguration execution instruction timing signal is Process management A step of outputting to the control unit, the process management control unit receiving the reconfiguration execution instruction timing signal, and outputting the reconfiguration instruction signal held in the reception queue to a packet processing circuit; The packet processing circuit inputs the reconfiguration instruction signal to perform reconfiguration, and the input packet buffer unit reads the accumulated packet and outputs it as an output packet when the reconfiguration is completed. And a step of transmitting via the packet processing circuit. Reconfiguration in which a reconfiguration processing device having a process management control unit and an input packet buffer unit reconfigures a packet processing circuit without interruption while receiving an input packet from a communication network and transmits it as an output packet A processing method in which a process management control unit receives a reconfiguration instruction signal from the outside and holds it in a reception queue, and an input packet buffer unit is a buffer that is a usage amount of a buffer for storing the input packet The size is monitored, and when the buffer size is zero, the accumulation of the input packet is started and the counting of elapsed time is started, and the time required for the input packet to pass through the packet processing circuit is expressed as T1 If the count value is T1, And the buffer size is smaller than a preset upper limit value of the buffer size, the input packet accumulation is continued, the count value is smaller than T1, and the buffer size reaches the upper limit value. If equal, read the accumulated packet and send it as an output packet through the packet processing circuit, reset the count value when the buffer size becomes zero, the count value equals T1, and When the buffer size is smaller than the upper limit value, a reconfiguration execution instruction timing signal is output to the process management control unit, the step of resetting the count value, and the process management control unit includes the reconfiguration The execution instruction timing signal is input to receive the reception key. And a step of outputting the reconfiguration instruction signal held in the packet processing circuit to the packet processing circuit, and the packet processing circuit receiving the reconfiguration instruction signal and performing reconfiguration. Reconfiguration processing method. 4. The reconfiguration processing method according to claim 3, wherein the input packet buffer unit outputs the reconfiguration execution instruction timing signal to the process management control unit after the packet processing circuit starts reconfiguration. When the size of the input packet that is continuously received and accumulated from the communication network within the time period until the time Q is assumed to be Q, the count value is equal to T1, and the buffer size is from the upper limit value. A reconfiguration processing method, wherein the reconfiguration processing method is characterized by being smaller than a value obtained by subtracting Q. Reconfiguration in which a reconfiguration processing device having a process management control unit and an input packet buffer unit reconfigures a packet processing circuit without interruption while receiving an input packet from a communication network and transmits it as an output packet When the process management control unit receives a reconfiguration instruction signal from the outside and holds it in the reception queue, and the packet processing circuit has no input packet to be processed in the packet processing circuit. The step of outputting an input packet empty signal to the input packet buffer unit, and the input packet buffer unit inputs the input packet empty signal and starts accumulating the input packet. Signal management process A step of outputting to the control unit, the process management control unit receiving the reconfiguration execution instruction timing signal, and outputting the reconfiguration instruction signal held in the reception queue to a packet processing circuit; The packet processing circuit inputs the reconfiguration instruction signal to perform reconfiguration, and the input packet buffer unit reads the accumulated packet and outputs it as an output packet when the reconfiguration is completed. And a step of transmitting via the packet processing circuit. The reconfiguration processing method according to any one of claims 1, 2, and 5, wherein the time from when the process management control unit starts reconfiguration of the packet processing circuit to completion thereof is T2. The step of outputting a read instruction signal to the input packet buffer unit when a time equal to or greater than T2 has elapsed since the reconfiguration instruction signal was output to the packet processing circuit; and A reconfiguration processing method comprising: inputting a read instruction signal, reading the accumulated packet, and transmitting the packet as an output packet via the packet processing circuit. 6. The reconfiguration processing method according to claim 1, wherein the packet processing circuit outputs a reconfiguration completion signal to the process management control unit when the reconfiguration is completed. The process management control unit inputs the reconfiguration completion signal and outputs a read instruction signal to the input packet buffer unit; and the input packet buffer unit inputs the read instruction signal; A reconfiguration processing method comprising: reading out the accumulated packets and transmitting the packets as output packets via the packet processing circuit. In a reconfiguration processing device that reconfigures a packet processing circuit without interruption while receiving an input packet from a communication network and transmits the packet as an output packet through the packet processing circuit, the reconfiguration processing device Includes a process management control unit and an input packet buffer unit, the process management control unit receiving queue for holding a reconfiguration instruction signal, and input packet control for outputting a storage instruction signal to the input packet buffer unit The input packet control unit receives the reconfiguration instruction signal from the outside and holds it in the reception queue, and when the time required for the input packet to pass through the packet processing circuit is T1 When a time longer than T1 has passed since the signal was output A reconfiguration signal processing unit that outputs a reconfiguration instruction signal held in the reception queue to a packet processing circuit to perform reconfiguration, and the input packet buffer unit includes the accumulation instruction signal The input packet is stored, and when the reconfiguration is completed, the stored packet is read out and transmitted as an output packet via the packet processing circuit. Reconfiguration processing device. In a reconfiguration processing device that reconfigures a packet processing circuit without interruption while receiving an input packet from a communication network and transmits the packet as an output packet through the packet processing circuit, the reconfiguration processing device Has a process management control unit and an input packet buffer unit, and the process management control unit receives a reconfiguration instruction signal from the outside, and receives the reconfiguration instruction signal from the outside to receive queue. A reconfiguration signal processing unit that outputs a reconfiguration instruction signal held in the reception queue to the packet processing circuit and performs reconfiguration when a reconfiguration execution instruction timing signal is input. Have The packet buffer unit inputs the instruction to store the input packet, stores the input packet, and when the reconfiguration is completed, reads the stored packet and transmits it as an output packet through the packet processing circuit. When the time required for the packet storage unit and the input packet to pass through the packet processing circuit is T1, a timing at which the input packet is not continuously received from the communication network for a time equal to or longer than T1 is extracted. And an input packet monitoring unit that outputs an instruction to store the input packet to the input packet storage unit and outputs a reconfiguration execution instruction timing signal to the process management control unit. Equipment. In a reconfiguration processing device that reconfigures a packet processing circuit without interruption while receiving an input packet from a communication network and transmits the packet as an output packet through the packet processing circuit, the reconfiguration processing device Has a process management control unit and an input packet buffer unit, and the process management control unit receives a reconfiguration instruction signal from the outside, and receives the reconfiguration instruction signal from the outside to receive queue. A reconfiguration signal processing unit that outputs a reconfiguration instruction signal held in the reception queue to the packet processing circuit and performs reconfiguration when a reconfiguration execution instruction timing signal is input. Have The packet buffer unit inputs an instruction to store an input packet, stores an input packet, inputs an instruction to read out the stored packet, reads out the stored packet, and outputs the packet processing circuit as an output packet. Monitoring the buffer size, which is the amount of use of the input packet storage unit to be transmitted to the communication network and the buffer for storing the input packet, and if the buffer size is zero, the instruction to store the input packet is Output to the packet storage unit, start counting elapsed time, and when the time required for the input packet to pass through the packet processing circuit is T1, the count value is smaller than T1 and the buffer size Is smaller than the preset upper limit of the buffer size, the input packet When the count value is smaller than T1 and the buffer size is equal to the upper limit value, an instruction to read the accumulated packet is output to the input packet accumulation unit, and the buffer size When the count value becomes zero, the count value is reset, and when the count value is equal to T1 and the buffer size is smaller than the upper limit value, a reconfiguration execution instruction timing signal is output to the process management control unit, and A reconfiguration processing apparatus comprising: a buffer control unit that resets the count value. The reconfiguration processing device according to claim 10, wherein the buffer control unit of the input packet buffer unit outputs a reconfiguration execution instruction timing signal to the process management control unit because the packet processing circuit performs reconfiguration. The count value is equal to T1, and the size of the input packets accumulated by continuously receiving input packets from the communication network within the time from the start to the completion is Q1, and A reconfiguration processing apparatus characterized in that the buffer size is smaller than a value obtained by subtracting Q from an upper limit value. In a reconfiguration processing device that reconfigures a packet processing circuit without interruption while receiving an input packet from a communication network and transmits the packet as an output packet through the packet processing circuit, the reconfiguration processing device Has a process management control unit and an input packet buffer unit, and the process management control unit receives a reconfiguration instruction signal from the outside, and receives the reconfiguration instruction signal from the outside to receive queue. A reconfiguration signal processing unit that outputs a reconfiguration instruction signal held in the reception queue to the packet processing circuit and performs reconfiguration when a reconfiguration execution instruction timing signal is input. Have When the packet buffer unit inputs an instruction to store the input packet, the packet buffer unit stores the input packet. When the reconfiguration is completed, the packet buffer unit reads the stored packet and outputs it as an output packet to the communication network via the packet processing circuit An input packet storage unit for transmitting, and when receiving an input packet empty signal transmitted from the packet processing circuit when there is no input packet to be subjected to packet processing, a signal for storing the input packet is transmitted to the input packet storage unit. And a buffer control unit that outputs a reconfiguration execution instruction timing signal to the process management control unit. The reconfiguration processing device according to any one of claims 8, 9 and 12, wherein the process management control unit sets a time period from the start to the completion of reconfiguration of the packet processing circuit as T2. An input packet control unit that outputs a read instruction signal to an input packet buffer unit when a time equal to or greater than T2 has elapsed since the reconfiguration instruction signal was output to the packet processing circuit. The packet buffer unit includes an input packet storage unit that inputs the read instruction signal, reads the stored packet, and transmits the packet as an output packet via the packet processing circuit. . 13. The reconfiguration processing device according to claim 8, 9 or 12, wherein the process management control unit receives a reconfiguration completion signal output when reconfiguration is completed from a packet processing circuit. And an input packet control unit that outputs a read instruction signal to the input packet buffer unit. The input packet buffer unit inputs the read instruction signal, reads the accumulated packet, and outputs the packet. A reconfiguration processing apparatus comprising: an input packet storage unit that transmits as a packet through the packet processing circuit.

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