JP2501141B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a bipolar transistor is formed on a semiconductor layer on an insulating substrate having a so-called SOI structure, and a manufacturing method thereof.

[0002]

2. Description of the Related Art As an insulating substrate, an oxide film is sandwiched between 2
SIMOX (SIMO) in which oxygen is ion-implanted from one surface of a silicon substrate or a bonded substrate in which a plurality of silicon substrates are bonded to form an oxidized region at a predetermined depth below the surface.
X) substrates and the like are known. These so-called SOI substrates are suitable for forming a semiconductor element on the semiconductor layer on the surface and dielectrically separating the surroundings, and are suitable for manufacturing a semiconductor element that can operate at high speed with low parasitic capacitance. With the improvement of technology, the thickness of the silicon active layer on the oxide film of the SOI substrate can be made submicron. Such SO
M that suppresses short channel effect with high gm by using I substrate
An OS transistor can be formed. However, in order to increase the load driving capability, it is desired to make a bipolar transistor. A normal bipolar transistor adopts a vertical structure in which a current is passed in a vertical direction. However, in the case of an SOI substrate, the number of steps is large in manufacturing a vertical bipolar transistor, and it is difficult to form a buried layer of a collector. There are many problems. Therefore, a bipolar transistor having a lateral structure is manufactured.

FIG. 7 shows a conventional lateral bipolar transistor having an SOI structure.

A semiconductor layer 50 for manufacturing a semiconductor element is formed on an insulating substrate 51 formed of silicon oxide SiO2 or the like.

The semiconductor layer 50 has, for example, a p-type impurity concentration suitable for forming the p-type base region 52, and a portion other than a region where a semiconductor element is to be formed is oxidized to form an element isolation region 55. . In the element region surrounded by the element isolation region 55, n-type impurities are selectively doped, and the n-type emitter region 53 and the n-type collector region 54 are formed.
Is formed.

On the semiconductor element forming semiconductor layer 50,
An insulating layer 57 such as SiO2 is formed and an opening is formed in a desired area. Through these openings, n ⁺ -type polycrystalline silicon electrodes 62 and 63 contacting a desired semiconductor region are formed.

Similarly, an insulating film 58 of SiO 2 or the like is formed, an opening is formed on the p-type region 52, and then a p ⁺ -type polycrystalline silicon electrode 61 is formed.

In the structure shown, the polycrystalline silicon electrode 61 forms a base extraction electrode, the polycrystalline silicon electrode 62 forms an emitter extraction electrode, and the polycrystalline silicon electrode 63 forms a collector extraction electrode. These polycrystalline silicon electrodes 61, 62, 63 are separated from each other by insulating layers 57, 58, 59 such as silicon oxide.
An opening is provided in a desired region of the insulating layer 59, and a base electrode 64, an emitter electrode 65, and a collector electrode 66 made of a metal such as aluminum are formed through the opening. The base electrode 64 contacts the polycrystalline base extraction electrode 61, the emitter electrode 65 contacts the polycrystalline emitter extraction electrode 62, and the collector electrode 66 contacts the polycrystalline collector extraction electrode 63.

In this way, a lateral bipolar transistor is manufactured using the SOI structure.

The emitter region 53 and the collector region 54 are
It is manufactured by diffusing impurities from the surface of the p-type semiconductor layer 50. In this case, the boundaries between the emitter region 53 and the collector region 54 are formed so as to separate from each other as they enter the semiconductor layer 50 from the surface. Therefore, the lateral width (base width) of the base region 52 changes with the depth.

In order to form an opening on the surface of the p-type base region 52 and form the base lead-out electrode 61 of a polycrystalline silicon electrode, the p-type base region 52 is formed.
The lateral dimension of must be kept above a certain value. For example, the lateral width of the base region 52 is 0.1 to 0.15.
The limit is μm.

[0012]

In order to manufacture a high-speed lateral bipolar transistor, it is desirable that the base width be as narrow as possible and uniform in the depth direction.

An object of the present invention is to provide a semiconductor device capable of maintaining a base width uniform in the depth direction and being manufactured with sufficiently high accuracy.

Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of controlling the base width with high accuracy.

[0015]

According to the present invention, there is provided a semiconductor device comprising:
A first-conductivity-type single crystal semiconductor layer disposed on an insulating substrate, a mask layer having an end portion formed in partial contact with the single crystal semiconductor layer, and an end side surface of the mask layer. An insulating region, a base region of a second conductivity type opposite to the first conductivity type formed by ion implantation below the insulating region of the single crystal semiconductor layer, and a mask layer of the single crystal semiconductor layer and an insulating region. An unexposed region having a first conductivity type emitter region formed by ion implantation adjacent to the base region.

The semiconductor device manufacturing method of the present invention is
A step of forming a mask layer on the first conductivity type single crystal semiconductor layer on the insulating substrate, and using the mask layer as a mask, impurities of the second conductivity type opposite to the first conductivity type are added to the single crystal semiconductor layer. Forming a second conductivity type region by ion implantation; depositing an insulating layer covering the mask layer and performing anisotropic etching to form an insulating region on the side surface of the mask layer; And a step of forming a first conductivity type emitter region by ion-implanting a first conductivity type impurity using the insulation region as a mask and leaving a second conductivity type base region under the insulation region.

[0017]

Since the width of the base region 6a can be controlled by the thickness of the insulating region 7 formed on the side surfaces of the mask layers 4 and 5, highly accurate base width control is possible.

Since the base region and the emitter region are formed by ion implantation, the base width can be made uniform in the depth direction of the base region. Therefore, a high performance lateral bipolar transistor can be manufactured.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention. A single crystal semiconductor layer 2 is formed on an insulating substrate 1, and a lateral bipolar transistor is formed in the single crystal semiconductor layer 2.

That is, an n ⁺ type emitter region 8 is formed on the right side of the drawing, a narrow p type base region 6a is formed in connection with this emitter region 8, and an n type collector region, n ⁺ is formed on the left side thereof. A mold collector take-out region 12 is formed. In addition, in the surface portion of the single crystal semiconductor layer 2,
The p ^{+ type} external base region 9 is in contact with the p type base region 6a.
Has been created.

On the external base region 9, a polycrystalline semiconductor layer 4 containing p-type impurities is formed in contact with the opening of the insulating layer 3. An insulating layer 5 of SiO2 or the like is formed on the polycrystalline semiconductor layer 4, and both layers form a mask layer. On the side surfaces of the mask layers 4 and 5, an insulating region 7 as a so-called sidewall oxide is formed with a predetermined thickness.

An insulating region 7 corresponding to the base region 6a is formed on the side surface of the polycrystalline semiconductor layer 4 in contact with the single crystal semiconductor layer 2, and a similar insulating region 7 is formed on the opposite side. ing. The n ⁺ -type emitter region 8 and the collector extraction region 12 are defined on the outer edges of these insulating regions 7.
Are formed.

An emitter electrode 14 and a collector electrode 16 made of a metal such as aluminum are formed on the emitter region 8 and the collector lead-out region 12.

The base region 6a and the emitter region 8 are
It is formed by ion implantation. Therefore, the boundary between the base region 6a and the emitter region 8 is defined by the single crystal semiconductor layer 2
Is defined substantially perpendicular to the surface of the. Also, the impurity concentration distributions of the base region 6a and the emitter region 8 can be made substantially uniform in the depth direction.

In this way, the base region 6a having a substantially uniform thickness and impurity concentration in the depth direction can be produced, so that a high performance lateral bipolar transistor can be realized.

FIG. 2 shows an essential part of a manufacturing process for manufacturing the lateral bipolar transistor shown in FIG.

First, an insulating layer 3 made of SiO2 or the like is formed on the single crystal semiconductor layer 2 formed on the insulating substrate 1, and an opening is formed in a desired region thereof. Then, the single crystal semiconductor layer 2
A polycrystalline semiconductor layer 4 is formed on the surface, and an insulating layer 5 made of SiO2 or the like is continuously deposited on the polycrystalline semiconductor layer 4 by plasma CVD or the like.
The term "polycrystal" is a broad concept including amorphous.

A photoresist layer is formed on the polycrystalline semiconductor layer 4 and the insulating layer 5, exposed to a desired pattern to form a photoresist mask, and the exposed insulating layer 5 is formed.
Then, the polycrystalline semiconductor layer 4 is removed by etching such as inactive ion etching (RIE). After that, the photoresist is also removed to obtain the structure shown in FIG. The polycrystalline semiconductor layer 4 is heavily doped with p-type impurities by doping the source material with impurities or by doping the impurities after the layer is formed.

Using the patterned polycrystalline semiconductor layer 4 and insulating layer 5 as a mask, p-type impurities such as B ions are ion-implanted to form p-type region 6 in the exposed region.

Thereafter, as shown in FIG. 2B, an insulating layer of oxide, nitride or the like is deposited to a predetermined thickness on the surface of the semiconductor structure, and anisotropic etching such as reactive ion etching (RIE) is performed. To do. When the insulating layer having a predetermined thickness is removed by the anisotropic etching in the direction perpendicular to the surface of the single crystal semiconductor layer 2, the insulating layer on the surface of the single crystal semiconductor layer 2 and
The insulating layer on the insulating layer 5 is removed, but the polycrystalline semiconductor layer 4 is removed.
And the insulating layer 7 formed on the side surface of the insulating layer 5 thereon
Remain with the upper part thereof etched. That is, the insulating region 7 constitutes a so-called sidewall insulator. The thickness of the insulating region 7 can be accurately controlled by controlling the thickness when depositing the insulating layer.

That is, the insulating region 7 is formed on the p-type region 6 substantially vertically with a predetermined width. Using polycrystalline semiconductor layer 4 and insulating layer 5 thereon, and sidewall insulating region 7 as a mask, n-type impurities (for example, arsenic As) are ion-implanted to produce n ⁺ -type region 8. At this time, the p-type region 6a having a predetermined width remains under the insulating region 7 which is the sidewall oxide.
This p-type region 6a forms a base region (intrinsic base region).

That is, two times of ion implantation shown in FIGS. 2A and 2B are applied to the insulating region 7 forming the sidewall.
By forming and interposing, the base region 6a corresponding to the width of the insulating region 7 can be manufactured with high precision.

Thereafter, as shown in FIG. 2C, the semiconductor structure is heated to a predetermined temperature and held for a predetermined time to diffuse p-type impurities from the polycrystalline semiconductor layer 4 into the single crystal semiconductor layer 2, A p ^{+ type} external base region 9 for drawing out the base region is prepared. The external base region 9 electrically connects the polycrystalline semiconductor layer 4 and the base region 6a.

In this way, the base region 6a having an extremely thin base width can be manufactured with high precision.
The insulating region 7 made of an oxide film, a nitride film or the like has a thickness of, for example, 50 to 100 nm, and the thickness can be controlled with an accuracy of about 10 nm or less. Therefore, the base region 6a
The base width can be controlled to an accuracy of about 10 nm or less.

In the above manufacturing method, for example, the thickness of the insulating layer 3 on the surface of the single crystal semiconductor layer 2 is about 10 to 50.
The thickness of the polycrystalline semiconductor layer 4 is, eg, about 300 nm, and the thickness of the insulating film 5 such as an oxide film thereon is, eg, about 300 nm. The p-type region 6 is ion-implanted by, for example, boron with an impurity concentration 1E18c
Perform so that it is about m ^-3 . Note that the single crystal semiconductor layer 2
Contains an n-type impurity of, for example, about 1E17 cm ⁻³ .

The insulating region 7 on the side walls of the mask layers 4 and 5 is
For example, it is formed of a silicon nitride film having a thickness of about 50 to 100 nm. The ion implantation for forming the emitter region 8 shown in FIG. 2B is performed by using, for example, phosphorus (P) which is an n-type impurity.
Is manufactured by ion implantation with an impurity concentration of about 1E20 cm -3.

In the first ion implantation, the conductivity type of the single crystal semiconductor layer 2 is compensated and inverted, and in the second ion implantation,
The conductivity type of the first ion implantation is further compensated and inverted.

In this way, a lateral bipolar transistor having a base region of a predetermined width can be manufactured with high precision.

In the manufacturing method shown in FIG. 2, only the parts for forming the base region and the emitter region are shown. However, by adjusting the patterning of the polycrystalline semiconductor layer 4 and the insulating layer 5 thereabove, the pattern shown in FIG. The n ⁺ -type collector take-out region 12 shown in can be formed at the same time when the emitter region 8 is formed.

The lateral bipolar transistor shown in FIG. 1 constitutes a lateral bipolar transistor having a uniform base width in the depth direction and capable of high-speed operation. The base electrode is formed on the surface portion of the single crystal semiconductor layer 2. It is connected to the polycrystalline base region 4 via the external base region 9. Therefore, during operation, there is some asymmetry in the depth direction.

FIG. 3 shows the structure of a lateral bipolar transistor having improved symmetry in the depth direction. 3A shows a schematic plan view, and FIG. 3B shows a schematic sectional view.

In the present embodiment, the single crystal semiconductor layer on the insulating substrate is selectively oxidized leaving a substantially cross-shaped element region to form a single crystal semiconductor region surrounded by the element isolation region 10. The external base region 18 is formed at two opposing branch portions of the cross-shaped single crystal semiconductor region. In addition, the emitter region 8 is provided on the other two branch portions facing each other.
And collector region 12 is formed. The base electrode 20 is connected to the external base region 18, and the emitter region 8
Is connected to the emitter electrode 14, and the collector region 12 is connected to the collector electrode 16.

In this structure, since the intrinsic base region 6a sandwiched between the emitter region 8 and the collector region 12 is connected to the electrode from the side through the external base region 18, it is substantially in the depth direction. It can be a uniform contrasting configuration. Therefore, it is possible to configure a lateral bipolar transistor that effectively utilizes the entire thickness of the single crystal semiconductor layer.

FIG. 4 shows an embodiment having a more specific configuration according to the concept of FIG. The element region surrounded by the element isolation region 10 is centered on the intrinsic base region 6a, and the external base region 18 is provided above and below the intrinsic base region 6a, and the collector regions 2 are provided on the left and right thereof.
12 and the emitter region 8 are formed. The collector region is composed of an n ⁻ type active collector region 2 and an n ⁺ type collector extraction region 12. The n ⁺ type emitter region 8 faces the n ⁻ type active collector region 2 with a predetermined gap therebetween, and defines the intrinsic base region 6a therebetween. External base regions 18 having a high p-type impurity concentration are formed above and below the intrinsic base regions 6a.

A manufacturing method for highly accurately making the intrinsic base region 6a of the lateral bipolar transistor shown in FIG. 4 thin will be described with reference to FIGS. Note that FIG.
6 (A), (B), and (C) show plan views, and FIG.
(A), (B), (C), and (D) are 6A in FIG.
-6A ', 6B-6B', 6C-6C ', 6D-6D'
FIG.

First, an SOI substrate having an n-type single crystal silicon layer 2 on an insulating substrate 1 is prepared.

Next, as shown in FIGS. 5A and 6A, the single crystal silicon layer 2 is oxidized so as to surround the element formation region, and the element isolation region 10 is produced. For example, a nitride film is formed on the single crystal semiconductor layer, and patterning is performed using a photoresist layer to manufacture a mask of the nitride film corresponding to the element region. Subsequently, the single crystal silicon layer is oxidized to oxidize the single crystal silicon layer except for the element region covered with the nitride film mask, to form the element isolation region 10. After that, the nitride film mask is removed to form the single crystal semiconductor layer 2 forming the element region. When manufacturing an npn bipolar transistor, the single crystal semiconductor layer 2 has an n ⁻ impurity concentration of about 1E17 cm ^−3.
The type area.

Next, the surface of the single crystal semiconductor layer 2 is about 10 to 10.
The silicon oxide film 21 is formed by oxidizing about 50 nm.
A resist layer is formed on this silicon oxide film and patterned by lithography to form a contact hole for a collector lead electrode.

As shown in FIGS. 5 (B) and 6 (B), an n ⁺ type polycrystalline silicon layer 22 having a thickness of about 300 nm is formed thereon.
It is formed and patterned into a desired pattern to form a polycrystalline collector extraction region 22. This polycrystalline collector take-out region 22 is in contact with the n ⁻ type collector region 2 therebelow in the contact region exposed in the opening 24 of the oxide film 21.

An insulating layer 23 made of silicon oxide or the like is formed on the polycrystalline collector extraction region 22, for example, to have a thickness of about 300 nm.
And is deposited to a degree to cover the polycrystalline collector take-out layer 22. By forming a photoresist layer on the insulating layer 23 and patterning by RIE using photolithography, as shown in FIG.
Mask layers 22 and 23 as shown in FIG. 6B are formed. The mask layer formed of the polycrystalline collector take-out region 22 and the insulating layer 23 has a side surface substantially vertical to the substrate surface.

Using the mask layers 22 and 23 as masks, p
Type impurities, eg, boron, with an impurity concentration of about 1E18 cm
Impurity is implanted so as to be ⁻³ . In this way, the p ⁺ type region 6 is formed in the region exposed outside the masks 22 and 23.

Next, a silicon nitride film is deposited on the surface to a predetermined thickness, and anisotropic etching is performed to remove the silicon nitride film 7 on the side surface and other portions. In this way, the sidewall nitride film 7 is formed on the side surfaces of the mask layers 22 and 23.
Is formed.

In the state where the side wall nitride film 7 shown in FIG. 6C is formed, an n-type impurity such as phosphorus (P) is ion-implanted from above the substrate to compensate the p ⁺ -type region 6 and the n ⁺ -type region. 8 is produced.

A photoresist layer 26 is formed on the portion which will be the external base region, and ions are not implanted below these regions. This state is shown in FIG.

In this way, a large amount of n-type impurity is doped only in the portion to be the emitter region, and the n ⁺ -type emitter region 8 is formed by compensating for the p-type impurity. For example, the emitter region 8 has an n-type impurity concentration of about 1E20 cm ^-3 .

After that, the photoresist layer 26 and the nitride film 7 are removed, and a predetermined electrode is formed to form a lateral bipolar transistor as shown in FIG.

According to this embodiment, the width of the base of the lateral bipolar transistor is controlled by the thickness of the nitride film 7 formed on the side wall of the mask layer, and the width of the base film is made uniform in the depth direction with an accuracy of about 10 nm, for example. can do.

According to the embodiment described above, a lateral bipolar transistor having an extremely thin base width and controlled with high precision can be manufactured in the SOI structure.

Thus, in the bipolar transistor according to the present invention, since the elements are completely separated by the dielectric,
It is possible to fabricate a bipolar transistor that can operate at extremely high speed.

Further, the manufacturing method of the lateral bipolar transistor described above requires fewer steps and masks than the conventional manufacturing method of the bipolar transistor. Therefore, it is possible to manufacture with low manufacturing cost and high yield.

Although the present invention has been described with reference to the embodiments, the present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations and the like can be made.

[0063]

As described above, according to the present invention,
Provided are a bipolar transistor capable of controlling a base width uniformly, extremely thinly, and highly accurately, and a manufacturing method thereof.

Therefore, it is possible to provide an SOI semiconductor integrated circuit having an extremely high speed and high performance bipolar transistor.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 shows a main part of a manufacturing method for manufacturing the configuration of FIG. 2A, 2B, and 2C are cross-sectional views showing the main part of the manufacturing method.

FIG. 3 shows another embodiment of the present invention. 3A is a plan view and FIG. 3B is a sectional view taken along the line 3B-3B ′.

FIG. 4 is a plan view showing a more specific configuration of the embodiment of FIG.

FIG. 5 is a diagram for explaining the steps of the manufacturing method for manufacturing the embodiment of FIG. 5 (A), (B), and (C)
It is a top view which shows the principal process of a manufacturing method.

6A and 6B are views for explaining steps of a manufacturing method for manufacturing the embodiment of FIG. 6 (A), (B),
(C) and (D) are 6A-6A 'line, 6B-6B' line, 6C-6C 'line, and 6 shown in FIGS. 5 (A), (B), and (C).
It is sectional drawing which follows the D-6D 'line.

FIG. 7 is a cross-sectional view showing a lateral bipolar transistor having an SOI structure according to a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Single crystal semiconductor layer 3 Insulating layer 4 Polycrystalline semiconductor layer 5 Insulating layer 6a Base region 7 Insulating region (sidewall) 8 Emitter region 9 External base region 10 Element isolation region 12 Collector extraction region 14 Emitter electrode 16 Collector electrode 18 external base region 20 base electrode

Claims (5)

(57) [Claims] 1. A mask layer having a first-conductivity-type single crystal semiconductor layer (2) arranged on an insulating substrate, and an end portion formed on the single crystal semiconductor layer (2) with partial contact. (4,
5), an insulating region (7) formed on the side surfaces of the end portions of the mask layers (4, 5), and below the insulating region (7) of the single crystal semiconductor layer (2) by ion implantation. And a base region (6a) of a second conductivity type opposite to the first conductivity type and the mask layers (4, 5) of the single crystal semiconductor layer (2) and the insulating region (7). A semiconductor device having a first conductivity type emitter region (8) formed by ion implantation adjacent to the base region (6a) in a non-existing region. 2. The semiconductor device according to claim 1, wherein
The mask layer (4, 5) is a semiconductor device including a second-conductivity-type polycrystalline semiconductor layer (4) in contact with the single crystal semiconductor layer (2). 3. The semiconductor device according to claim 1, wherein:
The single crystal semiconductor layer has a cross shape in a cross shape,
A semiconductor device in which the emitter region (8) and the collector region (12) are formed on opposite branches of a set, and both ends of the base region are connected to another pair of opposite branches. 4. A step of forming a mask layer (4,5) on a first conductivity type single crystal semiconductor layer (2) on an insulating substrate (1), and masking the mask layer (4,5). Used as
Forming a second conductivity type region (6) by ion-implanting an impurity of a second conductivity type opposite to the first conductivity type into the single crystal semiconductor layer (2); and forming the mask layers (4, 5). Forming an insulating region (7) on the side surface of the mask layer (4, 5) by depositing an insulating layer covering it and performing anisotropic etching; and the mask layer (4, 5) and the insulating layer. Using the region (7) as a mask, first conductivity type impurities are ion-implanted to form a first conductivity type emitter region (8), and a second conductivity type base region (6) is formed under the insulating region (7).
A method of manufacturing a semiconductor device, including the step of leaving a). 5. The mask layer (4, 5) includes a polycrystalline semiconductor layer (4) doped with a second conductivity type impurity, which is in contact with the single crystal semiconductor layer (2), and further the polycrystalline semiconductor layer. The method of manufacturing a semiconductor device according to claim 4, further comprising the step of diffusing a second conductivity type impurity from (4) to the single crystal semiconductor layer (2).