JP2526779B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which operates as a bipolar transistor, and more particularly to a lateral transistor structure which enables a high speed operation by causing an emitter-collector current to flow uniformly.

[0002]

2. Description of the Related Art In a semiconductor device of a general lateral bipolar transistor, an emitter / base / collector region is linearly formed. On the other hand, Japanese Patent Laid-Open No. 61-743
Japanese Patent No. 68 discloses a transistor in which each region is arranged concentrically as shown in FIG. In the figure, (A)
Is a plan view, and (B) is a cross-sectional view taken along line BB of (A). This transistor has a semi-insulating semiconductor substrate 61.
The N ⁺ -type first region 6 which becomes the emitter region in order from the center
2 and a P ⁺ -type third region 64 that serves as a base region and an N ⁺ -type second region 63 that serves as a collector region are formed concentrically. The emitter electrode 65, the base electrode 67, and the collector electrode 66 are connected to the respective regions.

When a forward bias voltage is applied between the third and first regions, a virtual base region 69 is formed below the third region by the injection of majority carriers. Since the virtual base region, that is, the current path due to the injected carriers is formed in the semi-insulating region, the diffusion length of the injected carriers is extremely long, the recombination speed is small, and the influence of the collector voltage is small. In addition, since they are concentric, all of the base current, collector current, and virtual base region are made uniform in the element, and as a result, they are said to be suitable for high output and high frequency.

[0004]

However, in the above-mentioned conventional technique, desired characteristics cannot be obtained unless a semiconductor having a semi-insulating property or a high specific resistance such as GaAs is used.
There was a drawback that the material was limited. Further, since this virtual base region is formed by injecting majority carriers, it is not possible to form a channel with a large width in the depth direction unless a high operating voltage is applied. It was necessary to devise such as raising. Further, the lateral arrangement causes the portion where the virtual base region is formed to be long, and it takes time for electrons to travel through this portion, so that there is a drawback that the speed is naturally limited. In addition, higher output is mentioned, but for that purpose, it is necessary to increase the size of the circle in the first region, and the speed decreases in inverse proportion to this, while increasing the size of the second and third regions. As the size increases accordingly, there is a drawback that the occupied area becomes large.

On the other hand, the structure shown in FIG.
2. Symposium on VLSI Techn
logic Digest of Technical
Papers. P54. FRACS (Fully
Radiatire Current Death St
"A High-Speed Bi
polar Transistor with Sub
-0.1 μm Emitter ”. In this transistor, a hemispherical groove is formed in a collector region 54 surrounded by a silicon oxide film 57 on a substrate 51, a base region 53 is formed on the surface by boron diffusion, and phosphorus-doped polysilicon 56 is formed as a groove. A buried emitter region 52 is formed and an emitter electrode 58 is formed to complete the transistor.

In this structure, electrons move radially from the spherical emitter region to operate at high speed. However, in this case, since the shape of the base drawn by the base polysilicon 55 is long and the base resistance is high, the cutoff frequency f _T is high, but the maximum oscillation frequency fmax is high.
Is not expected, and it is difficult to apply it to high frequency circuits.

[0007]

In order to solve the above-mentioned drawbacks, the present invention provides an insulating film on the surface of a substrate, a semiconductor layer on the insulating film, and a bipolar transistor on the semiconductor layer. In the formed semiconductor device, the circle
A columnar first conductivity type emitter region, and the emitter region
The cylindrical first part that is in contact with the outer periphery of and surrounds the emitter region.
2 conductive type base region and the outer periphery of the base region
First-conductivity-type collector region surrounding the base region
And having the emitter region, the base region and the front
Each region of the collector region is from the surface of the semiconductor layer to
Is it formed vertically or diagonally until it reaches the insulating film?
From the surface of the semiconductor layer having a slit-like shape
The cylindrical outer periphery of the base area is reached until the insulating film is reached.
One or a plurality of connected base fins are radially connected to each other.
The base fin is formed to extend inside the rectifier region.
Lateral type bipolar with a base electrode connected to the top of the
In a semiconductor device equipped with an error transistor. here
At the emitter region, the base region and the core region.
The insulation in at least one of each of the
Embedded metal electrode that reaches the membrane or penetrates halfway
Can be Also, collector electrode and emitter
One of the extraction electrodes is on the surface of the semiconductor layer
And the other is located between the substrate and the insulating film .

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

1A and 1B are views showing a first embodiment of the present invention. FIG. 1A is a plan view and FIG. 1B is a sectional view taken along line BB of FIG. In this figure, an insulating layer film 8 is formed on a substrate 1, and a collector region 4 is formed in the shape of an island region surrounded by an insulating region 7. Then, in it, a cylindrical N-type emitter region 2, a cylindrical P-type base region 3 in contact with the outside of this emitter region 2, and a P connected to this base region 3 are connected.
Type base fin region 5 and P type base contact region 6
Are formed. All of these regions 2, 3, 4, and 5 are formed so as to reach the insulating layer film 8 in a straight line vertically from the surface 12 of the semiconductor layer 11.

In this way, a lateral bipolar transistor is formed with the island region 4 as the collector region, and the electrons injected into the emitter region 2 pass through the base region 3 almost horizontally and reach the collector region 4 to perform this operation. In terms of a vertical cross section, this is performed in all parts above and below the cylindrical emitter region.

In plan view, the electrons radially reach the outer collector region 4 from the central emitter region.

As described above, according to the present invention, by forming the transistor structure, which has been conventionally planar, in three dimensions, it becomes possible to flow more electrons.

Next, an example of a method of manufacturing the transistor of FIG. 1 will be described with reference to FIGS. 2 and 3, (A) is a plan view and (B) is a cross-sectional view taken along the line BB of (A). Further, in FIG. 4, (A) is a plan view and (B) is (A).
3B is a cross-sectional view of the B-B section of FIG. 3C, and FIG. 6C is a cross-sectional view of the CC section of FIG.

First, as shown in FIGS. 2 (A) and 2 (B),
An N-type single crystal silicon layer 11 is formed on the insulating layer film 8 on the substrate 1 and is surrounded by the insulating region 7 to leave an island region. Then, the P ⁺ type base contact region 6 is formed on the surface 12 in the island region by diffusion or ion implantation. Here, the insulating layer film 8 is formed using an existing wafer bonding technique or an insulating layer embedding technique typified by SIMOX. The insulating region 7 may be either thermally oxidized or PN separated. Next in FIG.
As shown in (A) and (B), the P-type base forming region 3 ′ including the emitter forming region and the P-type base fin region 5 are included.
Is fixed without scanning with a boron ion beam, ions are implanted in the (110) direction using the inorganic mask material 13 as a mask, and the subsequent heat treatment for activation is performed. When the ion beam is angled by this ion implantation, the effect of channeling is weakened, so that the ion beam is fixed and perpendicular to the surface 12. That is, the plane orientation of the N-type island region is (11
If 0) is set and the beam for ion implantation is fixed and implanted, the implanted boron greatly advances in the channeling direction of the crystal. For example, at an energy of 70 KeV, a profile having a peak at a depth of 0.25 μm can be obtained in the <9.11.5> direction, but a profile having a substantially flat concentration from 0.35 to 0.9 μm in the <110> direction. Has been obtained. If the implantation energy is increased here, a flat concentration profile can be obtained at a deeper place, and if several implantation energies are combined, it is possible to form a flat concentration profile from a shallow place to a deep place. .

Next, as shown in FIGS. 4 (A), (B) and (C), an insulator is deposited on the entire surface and anisotropically etched back, so that only the side wall of the inorganic mask 13 is insulated. The sidewall 14 of the object is formed. At this time, FIG.
As shown in (C), the mask 1 on the base fin region 5
Since the space between the holes 3 is narrow, it is completely filled with the sidewall 14. Next, the emitter region 2 is formed by ion-implanting an N-type conductive material such as As to perform the thermal activation process, so that the base region 3 remains below the insulator 14 attached to the sidewall of the inorganic layer mask 13. The lateral bipolar transistor of the embodiment shown in FIG. 1 of the present invention is completed.

Next, another example of a method of manufacturing the bipolar transistor of FIG. 1 will be described with reference to FIGS.
5 to 7, (A) is a plan view and (B) is a cross-sectional view taken along the line BB of (A).

First, as shown in FIG. 5, the insulating layer film 8 and the N-type silicon layer 11 are formed on the substrate 1 as in FIG. 2, and the silicon layer 11 is surrounded by the insulating region 7 in the island region. The slit-shaped base fin region 5 is formed by the ion implantation method.
Then, using the inorganic mask 16 as a mask, a cylindrical hole 15 having the same plane shape as the emitter region is formed from the surface of the silicon layer to the insulating layer film 8. Therefore, even if the base fin region 5 is a little long, it is deleted in this step and no problem occurs. Further, when the base fin region 5 is formed by ion implantation, lateral expansion occurs, but this does not affect other regions either, so no problem occurs. Further, when forming the cylindrical space 15, if the wafer has a (110) plane, a vertical space can be formed by removing it with an alkaline etching solution such as hydrazine.
If it is other than the (0) plane, it is formed by anisotropic dry etching. Next, as shown in FIG. 7, the inside of the cylindrical hole 15 is filled with arsenic-doped polysilicon or single crystal silicon to form an N-type emitter region 2, and a P layer is formed on the surface of the silicon layer.
A mold base contact region 6 is formed.

FIG. 8 is a plan view showing a transistor provided with a plurality of base fins and base contacts as a second embodiment of the present invention. That is, FIG. 8 is a plan view showing an example of a device for reducing the resistance value of the base,
FIG. 8A has a second base fin region 22 and a second base contact region 21. Further, FIG. 8B further has a third base fin region 23 and a third base contact region 24. With these additional base fins and contacts, it is possible to reduce the resistance value of the base resistance up to the base region 3 by half or by ⅓. Further, since the resistance value of the base region 3 is half or 1/3, it is possible to provide a structure capable of reducing the resistance value. Therefore, if the number of base fins and base contacts is reduced, further reduction is possible.

FIG. 9 is a sectional view showing a third embodiment of the present invention. By embedding a metal electrode 9 in each of the emitter region 2 and the collector region 4 of this embodiment, the device is designed so as to reduce the emitter resistance and the collector resistance. By embedding the metal electrode 9 in this way, the resistance values of the emitter and the collector between the upper and lower sides of the transistor can be reduced, and the imbalance of the current amounts on the upper side and the lower side of the transistor can be reduced.

FIG. 10 is a plan view showing a fourth embodiment of the present invention. This embodiment is an example in which the buried metal electrode 32 is buried also in the base contact region, and it is possible to obtain the same effect as the above-mentioned reduction of the resistance value of each of the collector and the emitter. The collector-side buried metal electrode 33 is C
They are arranged in a letter shape, which makes it possible to uniformly capture the electrons radially emitted from the emitter region 2.
In this example, there is no problem in combining two or more base fins and base contacts as shown in FIG.
In (A), the collector-embedded metal electrode 33 produces a desired effect by embedding two semi-arc-shaped ones.

FIG. 11 is a sectional view showing the fifth embodiment of the present invention. In this embodiment, a device for eliminating the current imbalance between the upper and lower sides of the transistor is devised, and the emitter electrode and the collector electrode are taken out from opposite sides. That is, the electrode side is taken out from the upper side on the emitter side, and the buried lower electrode 36 is taken out from the collector 4 side. With such a device, all the electrons flowing from the emitter electrode are on the lower collector electrode 3
Flow toward 6 and no local concentration occurs. There is no problem if the emitter and collector electrodes are taken out in opposite directions. As an example of the method of manufacturing the structure of this embodiment, only the collector electrode is formed after the shape shown in FIG. 9 or 10 is formed, and then the back surface is ground to expose the emitter and base regions, and then another The substrate 1 is adhered to the substrate 1 with an adhesive layer 10 and then both electrodes of the emitter and the base are formed.

FIG. 12 is a cross section showing a sixth embodiment of the present invention. In this embodiment, the length of the transistor is lengthened when only a certain depth is available. That is, a substrate having <110> formed in an oblique direction is used, and the shape of FIG. 12 (A) is obtained by implanting ions from the <110> direction. 2 times (square root of 2 times)
It is possible to make it longer. In addition, FIG. 12B shows one of the measures for eliminating the current imbalance between the upper and lower sides of the transistor, in which the emitter-collector distance is set on the upper side and the bottom side is made closer. Have As a result, the increase in the collector resistance in the downward direction is offset by increasing the distance between the collector electrode and the base.

In the above embodiment, the embedded metal electrodes are W (tungsten), TiW (Titan), Al.
Although metals such as (aluminum) are assumed, substitution of other metals such as polysilicon or polysilicon is not prohibited.

[0024]

As described above, the transistor having the lateral structure according to the present invention has the following effects.

1. Since the base region can be formed to be short, the traveling distance of electrons is short and the high speed is excellent.

2. Since the transistors are formed in the depth direction of the substrate, transistors of various lengths can be formed even though they occupy the same area, and currents from small currents to large currents can be handled.

3. Since the transistor is a cylindrical type, and the emitter, base, and collector are in contact with each other, the transistor can be driven at a low voltage, and the high voltage required for forming the virtual base region is unnecessary.

4. This leads to improvement of the maximum oscillation frequency in order to provide a means for lowering the base resistance.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention, (A)
Is a plan view and (B) is a cross-sectional view taken along line BB of (A).

FIG. 2 is a diagram showing a step of an example of a method of manufacturing the bipolar transistor of the first embodiment, (A) is a plan view, and (B) is a cross-sectional view of a BB portion of (A). is there.

3A and 3B are views showing one step after FIG. 2, in which FIG. 3A is a plan view and FIG. 3B is a cross-sectional view taken along the line BB in FIG. 3A.

FIG. 4 is a diagram showing a step subsequent to FIG. 3, in which (A) is a plan view, (B) is a cross-sectional view taken along the line BB in (A), and (C) is C- in (A). It is sectional drawing of C part.

FIG. 5 is a diagram showing a step of another example of the method for manufacturing the bipolar transistor of the first embodiment, (A) is a plan view, and (B) is a cross-section taken along the line BB of (A). It is a figure.

6A and 6B are diagrams showing one step after FIG. 5, in which FIG. 6A is a plan view and FIG. 6B is a cross-sectional view taken along the line BB in FIG.

FIG. 7 is a diagram showing a step subsequent to FIG. 6, in which (A) is a plan view and (B) is a cross-sectional view taken along the line BB of (A).

FIG. 8 is a diagram showing a second embodiment of the present invention, (A)
And (B) are plan views of different modes.

FIG. 9 is a cross-sectional view showing a third embodiment of the present invention.

FIG. 10 is a plan view showing a fourth embodiment of the present invention.

FIG. 11 is a sectional view showing a fifth embodiment of the present invention.

FIG. 12 is a diagram showing a sixth embodiment of the present invention,
(A) And (B) is a sectional view of a mode which differs in each other.

13A and 13B are views showing a conventional bipolar transistor, in which FIG. 13A is a plan view and FIG. 13B is a cross-sectional view taken along the line BB in FIG. 13A.

FIG. 14 is a sectional view showing another conventional bipolar transistor.

[Explanation of symbols]

 1, 51, 61 substrate 2 emitter region 3 base region 3'base forming region including emitter forming region 4 collector region 5, 22, 23 base fin region 6, 21, 24 base contact region 7 insulating region 8 insulating layer film 9, 31, 32, 33 Embedded metal electrode 35, 36 Electrode 10 Adhesion layer 11 Silicon layer 12 Surface of silicon layer 13, 16 Mask 14 Sidewall 15 Cylindrical hole 52 Emitter 53 Base 54 Collector 55 Base polysilicon 56 Emitter polysilicon 57 Oxide film 62 First region 63 Second region 64 Third region 69 Virtual base region 58, 65, 66, 67 Electrode

Claims (3)

(57) [Claims] 1. A semiconductor device in which an insulating film is provided on a surface of a substrate, a semiconductor layer is provided on the insulating film, and a bipolar transistor is formed on the semiconductor layer, the columnar first conductivity type emitter. Area and the emitter area
A cylindrical shape that surrounds the emitter region in contact with the outer periphery of the region
The second conductivity type base region and the outer periphery of the base region.
And a collector region of the first conductivity type surrounding the base region
The emitter region, the base region and
Each region of the collector region is located in front of the surface of the semiconductor layer.
It is formed vertically or diagonally until it reaches the insulating film,
And having a slit-like shape from the surface of the semiconductor layer
Cylindrical outer periphery of the base region until reaching the insulating film
One or more base fins connected to
The base film is formed to extend inside the collector region.
A semiconductor device comprising a lateral type bipolar transistor, characterized in that a base electrode is connected to an upper part of the transistor. 2. The emitter region, the base region and
2. The semiconductor device according to claim 1, wherein a metal electrode reaching or partially penetrating the insulating film is embedded in at least one of the collector region and the collector region . 3. One of a collector electrode and an emitter lead electrode is located on the surface of the semiconductor layer, and the other is
The semiconductor device according to claim 1 , wherein the semiconductor device is located between the substrate and the insulating film .