JP2502152B2 - LCD drive circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a liquid crystal drive circuit including a MOS transistor.

<Prior Art> A liquid crystal drive circuit is provided in a liquid crystal display device 1 as shown in FIG.
Segment output signals I ₁ to, ..., and the segment signal output circuit 2 for outputting I _n, backplate output signal H _1, ..., H _m
And a back plate signal output circuit 3 for outputting

Conventional segment and backplate output signals are 4th
As shown in the figure, the circuit for outputting these signals has the configuration shown in FIG.
FIG. 5 (a) is a segment signal output circuit, and FIG. 5 (b).
Is a back plate signal output circuit.

V _A and V _B of this segment signal output circuit are frame 1
(S = H), V _A = V _A1 , V _B = V _B1 , frame 2 (S =
In L), it is controlled so that V _A = V _A2 and V _B = V _B2 . At each duty, with signal i = H, transistors Pa and Nb are turned on to output V _A1 level in frame 1, and transistors Pb and Na are turned on to output V _B2 level in frame 2. , The liquid crystal display is turned on, the signal i = L, the transistors Pb and Na are turned on to output the V _B1 level in the frame 1, and the transistors Pa and Nb are turned to the V _A2 in the frame 2.
Outputs the level and turns off the light.

With this segment signal output circuit, transistors Pa, N
b, Pb, and Na are tied together. Normal output buffer
With Pa and Na only, when frame 1 is turned on and Na outputs V _B1 level, and when frame 2 is turned on, Pa is turned on and V _A2
Back gate bias is applied to the Na and Pa transistors when the level is output (Na substrate potential V _B2
Source potential of V _B1 becomes higher and the substrate potential V _A1 of Pa becomes lower than the source potential of Pa becomes V _A2 ), the ON resistance of the transistor increases, and the liquid crystal that is a load cannot be driven, In frame 1, V _A1 level to V _B1 level,
In frame 2, the output signal waveform from the V _B2 level to the V _A2 level becomes blunt and the display quality deteriorates (see FIG. 6). In order to compensate the deterioration of the on-resistance due to this back gate bias, two transistors of Pb and Nb are added, and as a transfer gate, the level can be output with a small on-resistance in any case, and the rounding of the output signal waveform is performed. The display quality is kept good.

<Problems to be Solved by the Invention> In the conventional method, the output buffer section of the segment signal output circuit requires four transistors, which requires a very large area.

It is an object of the present invention to provide a method capable of forming an output buffer section of a segment signal output circuit with two transistors like a normal output buffer without deteriorating the display quality.

<Means for Solving the Problem> The liquid crystal drive circuit of the present invention, the first frame and the second frame are alternately repeated, in the first frame, to output the power supply potential based on the ON display data, Based on the off display data, outputs a predetermined first potential between the power supply potential and the ground potential, in the second frame,
A liquid crystal drive circuit that outputs the ground potential based on ON display data and outputs a predetermined second potential between the power supply potential and the ground potential based on OFF display data, wherein A frame signal defining a frame and a logic signal based on display data are applied to its gate, and its source is applied with the power supply potential in the first frame, and the second signal in the second frame. Single P-channel MO to which electric potential is applied
The S transistor and the logic signal are applied to its gate, and its source is applied with the first potential in the first frame and with the ground potential in the second frame. In the liquid crystal drive circuit in which the drain of one N-channel MOS transistor is connected and the connection point is an output terminal, the well of the P-channel MOS transistor is fixed to the same potential as the source of the P-channel MOS transistor,
The substrate of the N-channel MOS transistor is fixed to the ground potential, and in the initial period of each duty,
Means for turning on the N-channel MOS transistor regardless of the levels of the frame signal and the display data, and means for applying the ground potential to the source of the N-channel MOS transistor in the initial period. It is a feature.

<Examples> Hereinafter, the present invention will be described in detail based on Examples.

A segment and backplate signal output circuit according to the present invention is shown in FIGS. 1 (a) and 1 (b). This circuit is considered in the CMOS process of P substrate and N well.
Basically, the substrate potential of the transistor Pa (more accurately, the potential of the N well) is fixed to the same V _A as the source potential of Pa, and the signal T causes a short discharge period at the beginning of each duty of the segment and back plate output signals. It is configured to have.

 The output signal from this circuit is shown in FIG.

As a countermeasure against the back gate bias of the transistor Pa of the segment signal output circuit, the substrate potential of Pa (more precisely, the potential of the N well) is fixed to V _A at the same potential as the source of Pa.
It is possible to set the potential of the well to V _A if it is separated from the internal logic and only Pa is composed of a single well.
Even if V _A changes to V _A1 and V _A2 , the substrate (N well) and the source gate have the same potential, so that the back gate bias is not applied. However, since the substrate potential of the transistor Na is fixed to the V _B2 level, the potentials of the substrate and the source cannot be the same as in Pa, and back gate bias cannot be prevented. Therefore, the circuit configuration is as shown in FIG. 1, and the signal T is provided with a short discharge period at the beginning of each duty of the segment and back plate output signals. That is, the segment and back plate signals shown in FIG. 2 are output. If such a signal is output, when the V _A1 level is output, the charge that is charged up in the liquid crystal is in a state where no back gate bias is applied during the discharge period (when T = H, V _B = V _B2 because ), A small on resistance Na is discharged for a short time, and then V _B = V _B1 and N
The V _B1 level is output by a. For this reason, it has a large on-resistance when the back gate bias is applied.
It is not necessary to drive the liquid crystal that is a load with Na, the waveform is not blunted, and the display quality is good.

<Effects of the Invention> As described above, according to the present invention, the output buffer section of the segment signal output circuit can be configured by two transistors without deteriorating the display quality.
The liquid crystal drive circuit can be configured in a smaller area, which is extremely effective in practice.

[Brief description of drawings]

1 is a circuit diagram of a segment signal output circuit and a back plate signal output circuit according to the present invention, FIG. 2 is a waveform diagram of a segment output signal and a back plate output signal according to the present invention, and FIG. 3 is a liquid crystal display system. Block diagram, FIG. 4 is a waveform diagram of a conventional segment output signal and a backplate output signal, FIG. 5 is a circuit diagram of a conventional segment signal output circuit and a backplate signal output circuit, and FIG. 6 is Pa, N
It is a segment output signal waveform diagram at the time of only a.

Claims (1)

(57) [Claims] 1. A first frame and a second frame are alternately repeated, and in the first frame, a power supply potential is output based on ON display data, and the power supply potential and ground are output based on OFF display data. A predetermined first potential between the potentials is output, in the second frame, the ground potential is output based on the ON display data, and a predetermined first potential between the power supply potential and the ground potential is output based on the OFF display data. A liquid crystal drive circuit for outputting two potentials, wherein a logic signal based on a frame signal defining the first frame and the second frame and display data is applied to its gate, and its source is connected to the first frame. A single P-channel MOS to which the power supply potential is applied in the frame and the second potential is applied in the second frame
A transistor and the logic signal are applied to its gate, and its source is applied with the first potential in the first frame and is applied with the ground potential in the second frame. In the liquid crystal drive circuit in which the drain of the N-channel MOS transistor is connected and the connection point is an output terminal, the well of the P-channel MOS transistor is fixed to the same potential as the source of the P-channel MOS transistor, The substrate of the MOS transistor is fixed to the ground potential, and in the initial period of each duty, regardless of the levels of the frame signal and the display data,
Means for turning on the N-channel MOS transistor;
A liquid crystal drive circuit comprising means for applying the ground potential to the source of the N-channel MOS transistor in the initial period.