JP2507486B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a spare memory array and a roll call circuit for detecting whether or not the spare memory array has been used.

[Conventional technology]

2. Description of the Related Art In recent years, semiconductor memory devices have come to have a redundant configuration with a spare memory array to improve the yield as the storage capacity increases. In this case, in the final product form, it is not known whether or not the defective memory cell is replaced by the redundant structure.

However, as in the case of reliability analysis, it may be necessary to know that there is a replaced address, and therefore, a roll call circuit that is a function of detecting a replaced address is often provided.

A conventional semiconductor memory device of this type will be described with reference to the drawings.

FIG. 4 is a block diagram showing an example of a conventional semiconductor memory device.

The first and second row decoders 2a and 2b each select one of a plurality of row lines by the row address signals XA0 to XA8 input via the row address buffer 1.

The column decoder 7 selects one of the plurality of column lines according to the column address signals YA0 to YA9 input via the column address buffer 6.

The first and second memory arrays 4a, 4b are respectively the first
And the row lines from the second row decoders 2a and 2b and the column lines from the column decoder 7, and outputs the information of the memory cells corresponding to the selected row and column lines.

The first and second spare decoders 3a and 3b respectively receive the row address signals XA0 to XA8 from the row address buffer 1, and the row address signals XA0 to XA among the plurality of spare row lines.
If there is one corresponding to A8, the spare row line is selected and the first and second spare row selection signals Φ _SP1 and Φ _SP2 are output.

The first and second spare memory arrays 5a and 5b are connected to the spare row lines from the first and second spare decoders 3a and 3b, respectively, and are connected to the column lines from the column decoder 7 for selection. The information of the memory cells corresponding to the prepared spare row line and column line is output.

The output circuit 8 receives the output signal of the first memory array 4a or the spare memory array 5a and the second memory array 4b or the spare memory according to one address switching signal XA9 of the row address input via the switching signal buffer 9. Either one of the output signals of the array 5b is selected and output.

The roll call circuit 10b receives the first and second spare row selection signals Φ _SP1 and Φ _SP2 and detects that the spare memory arrays 5a and 5b have been selected by the change of the current I _D ′ flowing to the terminal T _1. .

Normally, when there are defective memory cells in the memory arrays 4a and 4b, the memory cells of the spare memory arrays 5a and 5b are selected row by row. That is, replacement between memory cells is performed.

FIG. 5 is a circuit diagram showing an example of a specific circuit configuration of the roll call circuit 10b of the semiconductor memory device shown in FIG.

A voltage higher than the power supply voltage Vcc by about 3V is applied to the terminal T ₁ , and when the spare memory arrays 5a and 5b are not selected, that is, when there is no replacement, the spare row selection signals Φ _SP1 and Φ
_{Since SP2} is at a low level, the transistors Q ₁ and Q ₂ are non-conductive and the current I _D ′ does not flow to the terminal T ₁ , but the memory array 4a or
If the spare memory array 5a or 5b is replaced with the spare memory array 5a or 5b, the spare memory array 5a or 5b is selected and the spare row selection signal Φ _SP1
Or, Φ _SP2 rises, the transistor Q ₁ or Q ₂ becomes conductive, the current I _D ′ flows to the terminal T ₁ , and it is detected which row address XA0 to XA8 has been replaced (hereinafter, this row address is called a replacement address). it can.

[Problems to be solved by the invention]

The conventional semiconductor memory device described above has a spare row selection signal Φ
Since it is configured to detect whether or not the spare memory arrays 5a and 5b are selected only by _SP1 and Φ _SP2 , the replacement address can be detected, but the first and second spare memory arrays 5a and 5b can be detected. There is a drawback that it cannot be distinguished which one of them has been selected.

An object of the present invention is to provide a semiconductor memory device capable of distinguishing which one of the first and second spare memory arrays is selected.

[Means for solving problems]

A semiconductor memory device according to the present invention is configured to select one of a plurality of row lines according to a row address signal.
Row decoders and column decoders that select one of a plurality of column lines according to a column address signal, are connected to the row lines from the first and second row decoders, respectively, and are connected from the column decoders. First and second memory arrays that are connected to the column lines and output the information of the memory cells corresponding to the selected row lines and column lines, and a plurality of spare row lines that receive the row address signals respectively. If there is one corresponding to this row address signal, the first and second spare decoders that select the spare row line and output the first and second spare row selection signals, and the first and second spare decoders, respectively. First and second memory cells connected to the spare row line from the second spare decoder and connected to the column line from the column decoder to output the information of the memory cells corresponding to the selected spare row line and column line. Second reserve A memory array, and an output circuit that selects and outputs one of the output signal of the first memory array or the spare memory array and the output signal of the second memory array or the spare memory array according to an address switching signal, According to the address switching signal, the first and second
And a roll call circuit for detecting which one of the first and second spare memory arrays is selected by outputting one of the spare row selection signals.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

This embodiment is different from the conventional semiconductor memory device shown in FIG. 4 in that the roll call circuit 10 includes a first and a second semiconductor memory device.
Spare row selection signal [Phi _SP1, [Phi addition to the first and second memory arrays 4a, enter either select one address switch signal XA9 and precharge signal [Phi _P of 4b the address switching signal _SP2 XA9 Selects either one of the first and second spare row selection signals Φ _SP1 and Φ _SP2 to control the transmission to the output terminal, and the first and second spare memory arrays 5a and 5b.
It is possible to detect which one of them has been selected.

Next, a specific circuit configuration of the roll call circuit 10 and its operation will be described.

FIG. 2 is a circuit diagram showing a specific circuit configuration of the roll call circuit 10.

Transistors Q ₁ and Q ₂ have transistors Q ₅ to Q ₂ , respectively.
₇ and Q ₈ is composed to Q ₁₀ address switch signal XA9, ▲ ▼
Preliminary row selection signal Φ via a gate circuit that opens and closes by 9
_{Since SP1} and Φ _SP2 are input, when the address switching signal XA9 for selecting the first memory array 4a side and the spare memory array 5a side is "1", the first spare row selection signal Φ _SP1 Are transmitted to the transistor Q ₁ , but the second spare row selection signal Φ _SP2 is blocked by the address switching signal XA9 and is not transmitted to the transistor Q _2, and the second memory array 4b and the spare memory array 5b are connected. When the address switching signal XA9 to be selected is "0", the opposite is true, and it is possible to detect which side has selected the spare memory arrays 5a and 5b.

FIG. 3 is a circuit diagram showing a specific circuit configuration of the roll call circuit according to the second embodiment of the present invention.

In the roll call circuit 10a of this embodiment, the output of the gate circuit on the side of the first spare row selection signal Φ _SP1 and the output of the gate circuit on the side of the second spare row selection signal Φ _SP2 are wired-OR connected to simplify the circuit. It has been transformed.

〔The invention's effect〕

As described above, the present invention provides a roll call circuit,
In addition to the first and second spare row selection signals, an address switching signal for switching the first and second memory arrays is input, and one of the first and second spare row selection signals is input by the address switching signal. By selecting one of them and controlling the transmission to the output end, it is possible to distinguish which one of the first and second spare memory arrays is selected.

[Brief description of drawings]

FIG. 1 is a block diagram showing the first embodiment of the present invention, and FIG.
FIG. 3 is a circuit diagram showing an example of a specific circuit configuration of the roll call circuit of the embodiment shown in FIG. 1, and FIG. 3 is a specific circuit configuration of the roll call circuit of the second embodiment of the present invention. FIG. 4 is a block diagram showing an example of a conventional semiconductor memory device, and FIG. 5 is an example of a concrete circuit configuration of a roll call circuit of the semiconductor memory device shown in FIG. It is a circuit diagram shown. 1 ... Row address buffer, 2a, 2b ... Row decoder, 3a,
3b ... Spare decoder, 4a, 4b ... Memory array, 5a, 5b ...
... Spare memory array, 6 ... Column address buffer, 7 ...
… Column decoder, 8 …… Output circuit, 9 …… Switching signal buffer, 10,10a, 10b …… Roll call circuit, C ₁ , C ₂ …… Capacitor, I ₁ …… Inverter, Q _{1 to} Q ₁₃ …… Transistor.

Claims (1)

(57) [Claims] 1. A first and second row decoder, each of which selects one of a plurality of row lines by a row address signal,
A column decoder that selects one of a plurality of column lines according to a column address signal is connected to a row line from each of the first and second row decoders and connected to a column line from the column decoder. Then, the first and second memory arrays that output the information of the memory cells corresponding to the selected row line and column line, and the row address signal that is input to each of the plurality of spare row lines. If there is one corresponding to the signal, the spare row line is selected, and the first and second spare decoders that output the first and second spare row selection signals, and the first and second spare decoders, respectively. First and second spare memories connected to the corresponding spare row lines and connected to the column lines from the column decoder and outputting the information of the memory cells corresponding to the selected spare row lines and column lines. An array, Dress the the switching signal by the output signal of the first memory array or the spare memory array second
Output circuit for selecting and outputting one of the output signals of the memory array or the spare memory array, and selecting one of the first and second spare row selection signals by the address switching signal. And output the first and second
And a roll call circuit for detecting which one of the spare memory arrays has been selected.