JP2516673B2 - Viterbi decoder bit error rate detection method - Google Patents

Description

The present invention relates to a bit error rate detecting method in a Viterbi decoder, and more particularly, to an improved method capable of easily predicting a bit error rate in real time without feedback of decoded data. And a bit error rate detection method.

[Prior Art] Satellite communications, which mainly mediate geostationary orbit satellites, have been put into practical use as various commercial communications, and their effectiveness has been remarkably expanded as a medium compatible with fixed point broadcasting or mobile communications.

In recent years, digital technology has been introduced into this type of satellite communication, and a digitally modulated signal is transmitted as data, and this signal is digitally demodulated in a receiver.

In such digital satellite communication, as is well known, the satellite line has different properties in terms of propagation delay time and noise distribution compared to the terrestrial data line network. Therefore, the satellite line is different from the terrestrial line in the satellite line. It is necessary to adopt error control technology.

That is, in the satellite link, the noise added to the transmission path can be considered as various Gaussian noises, and if the transmission rate is low enough to ignore intersymbol interference, the noise is considered to be independent between each code. Conceivable. In addition, the satellite line can be represented as a discrete and memoryless binary symmetrical communication channel.

Therefore, while utilizing such characteristics, various error control techniques are used in satellite communication.

Convolutional coding is well known as a conventional error control method, and it is not a block in which information bits are transmitted. This coding method is particularly suitable when information is continuously input to an encoder. The sequence of symbols is automatically encoded. That is, the information symbols are continuously shifted through the K (constraint length) stage shift register, and v encoded symbols are generated and transmitted at each shift. The v coded symbols are generated by a parity check, that is, the contents of several stages of the shift register are ORed together. The length K of the shift register is called a code constraint length, and the coding rate is R = 1 / v. It is generally known that the error rate of a randomly selected convolutional code decreases exponentially as the constraint length increases.

On the other hand, the Viterbi decoding method is used as an algorithm for decoding the above-mentioned convolutional code.

According to the Viterbi decoding algorithm, two paths leading to a given node are examined, a path most likely to be used in the encoder is selected, and this most probable path (remaining path) is saved. Is thrown away. And
This procedure is repeated for all states at each grid level.

FIG. 3 shows a schematic configuration of a conventional Viterbi decoding system, in which input signals P and Q taken from a satellite line are taken.
Is converted into a signal by the input interface 10, and is Viterbi-decoded by the addition comparator 12, and then stored in the path memory 14.

In the illustrated conventional device, the summing comparator 12 has a plurality of metric memories 16.

In the summing comparator 12, the cumulative metric of the two paths coupled at each contact are compared, only the path with the largest metric is saved, the other paths are discarded, and this procedure is repeated to determine all remaining paths. To be done. This remaining path is the path memory 14
Are sequentially stored in.

As described above, in the Viterbi decoding, the decoding operation is always processed by the forward addition comparison without making a backtracking, the metric of each branch is determined for each stage of the decoding, and the cumulative metric is calculated to be appropriate by the alternative. A simple operation is repeated only to determine a proper path.

However, of course, since the above operation is performed for each state, the complexity of the decoder is proportional to the number of states, and has the characteristic that it increases exponentially with the constraint length of the code. Therefore, this drawback requires an enormous memory (2 ^K-1 × L (L is the number of information bits)) bits of the remaining path memory to store the information of all paths.

In FIG. 3, the final output is the maximum (ma)
x) The content of 100 in the path memory is output.

[Problems to be Solved by the Invention] As described above, according to the Viterbi decoding method, it is possible to effectively correct a bit error that has occurred in a transmission path. However, when such Viterbi decoding is used, It is impossible to completely remove the code error, and it is generally necessary to always know the bit error rate accurately. However, conventionally, such monitoring of the bit error rate is performed by feeding back a decoded signal of Viterbi decoding, re-encoding it, and comparing it with input data of a decoder. There is a problem that a circuit configuration is required.

In particular, according to the above-mentioned re-encoding / comparing method, a complicated circuit is required to absorb the input / output delay time of the Viterbi decoder, and the display range of the bit error cannot be sufficiently taken, so that the accurate bit error rate There was a problem that it was difficult to display.

Furthermore, in practice, in order to detect the required bit error rate of several digits, the amount of recode comparison data must be increased, and such bit error rate can be detected in real time while performing Viterbi decoding. There was a problem that it was difficult to display.

The present invention has been made in view of the above conventional problems,
It is an object of the present invention to provide an improved bit error rate detection method capable of predicting a bit error rate which changes in real time with a simple circuit configuration.

[Means for Solving the Problem] In order to achieve the above object, the present invention focuses on the fact that the content of the path memory is a data string whose probability increases sequentially from the initial bit to the final bit. The feature is that the bit error rate can be detected in real time because the accumulated value at this time indicates the bit error rate as it is when the path memory information of the specific middle bit at the intermediate position of the memory is accumulated. .

That is, the predetermined N-th (N is an integer equal to or greater than 1) bit data is a mixture of "0" and "1" data. These data converge to either "0" or "1" data while repeating the Viterbi decoding, but since the influence of bit error still remains in the middle stage, "0"
And "1" are mixed. Therefore, when the “0” and the “1” are mixed, the error rate can be calculated by calculating the ratio.

[Operation] That is, according to the present invention, the initial bit of the path memory includes the bit error in the transmission path as it is,
On the other hand, this becomes the data for which error correction has been performed in the last bit of the path memory, and from this it can be understood that the error rate is successively decreasing in the intermediate bits in the intermediate position of the path memory.

Therefore, if you add the midway bits that are arbitrarily selected,
For example, the contents of 64 memories will be sequentially determined to be either "0" or "1" which is the data finally output from the path memory. Then, since it is a bit in the middle, a bit error is mixed in a part thereof.

Therefore, the data having the smaller number of intermediate bits, for example, the smaller number of data "0" when the whole is "1" or the smaller number "1" when the whole is "0".
Will indicate the bit error rate.

Therefore, if the smaller number of data is obtained, and this is integrated a predetermined number of times and displayed, it is possible to detect and display in real time as a bit error rate.

[Embodiment] A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic configuration of a decoder to which the present invention is applied in Viterbi decoding with a constraint length K = 7, a coding rate of 1/2, and a path memory length of 40, which is the same as that of FIG. 3 described above. The same reference numerals are given to the members and the description thereof will be omitted.

A feature of the present invention is that the intermediate bit at the intermediate position of the path memory 14, according to the embodiment, the 26th bit path memory data is integrated and output as a bit error rate. So the path memory
Since the path memory data in the vicinity of the central bit of 14 is in the middle of error correction and a trace of bit error remains, the bit error rate can be shown in real time as it is by integrating these.

In FIG. 1, the 26th-bit path memory data of the path memory 14 is added by a 16-bit adder 20, and this is latched by a first latch circuit 22.

FIG. 2A shows an example of the 26th bit of the path memory data of the path memory 14. In this case, the probable data is "0", and it is considered that some errors are mixed in this.

That is, as shown in FIG. 2A, different "1" data is stored in the 63rd line, the different data indicates an error, and the path memory 14 goes to the 40th bit which is the final bit. By then this error will be corrected.

However, in the present invention, the error in the middle bit of the path memory 14 indicates the bit error rate, and the bit error rate in Viterbi decoding can be predicted by this error rate.

That is, in FIG. 2A, the integrated value is “1”,
It indicates a bit error rate of 1/64.

Therefore, if this is integrated multiple times, for example 2 ¹⁶ times, 10
It is possible to obtain bit error rates from ^-2 to 10 ^{-7 with} an accuracy of 0.5 digits or more.

Of course, it is uncertain whether the majority bit of the intermediate bit selected for detecting the bit error rate, that is, the 26th bit data in the embodiment is "0" or "1" as shown in FIG. 2B. , Simply displaying the 26th bit of data causes the following inconveniences.

That is, in the case of FIG. 2B, the integrated value is “63”, which indicates an error-free data amount.As a result, in such a case, the bit error rate must be calculated by the calculation of 64-63. I won't.

In FIG. 1, the data converter 24 performs this calculation,
In this way, the integrated value of the 26th bit, which is a particular selected intermediate bit each time decoding is performed, is sequentially performed by the first embodiment.
It is integrated in the latch circuit 22.

Then, according to the embodiment, the first latch circuit accumulates the bit error rate for the above-mentioned 2 ¹⁶ times of decoding, and stores it in the second latch circuit 26. When the 2 ¹⁶ times of integration is completed, the timing circuit 27 causes the first latch circuit to
A signal is output to 22 to reset the contents, and the next integration starts from 0.

On the other hand, the contents stored in the second latch circuit 26 are displayed on the display 28 together with the data update, and the bit error rate at that time is displayed in real time.

In practice, the latch reset by the timing circuit 27 is defined by a method of display by the required rate speed and display 28 of the bit error rate, in the embodiment, approximately as long as more than Viterbi decoding frequency 100kbps, integration of 2 ¹⁶ times By this, the display 28 can update and display the bit error rate at intervals of about 1 second.

Of course, in the present invention, it is possible to improve the range and accuracy of the bit error rate by increasing the integrated number.

[Effects of the Invention] As described above, according to the present invention, the bit error rate can be detected and displayed in real time extremely simply by integrating the data of the intermediate bits of the path memory, and a complicated circuit configuration can be realized. It is possible to accurately predict a bit error rate that changes momentarily without needing it.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a preferred embodiment of a Viterbi decoder to which the bit error rate detecting method according to the present invention is applied, and FIGS. 2A and 2B are explanations showing an example of a path memory intermediate bit in the present invention. FIGS. 3A and 3B are block diagrams showing the outline of a conventional Viterbi decoder. 14 …… Pass memory 20 …… Adder 22,26 …… Latch circuit 28 …… Display

Claims (1)

(57) [Claims] 1. The input data coded and transmitted are added and compared and sequentially stored in a metric memory, and the most probable path is stored in a path memory for each node stage according to the contents of the addition and comparison. In a repeating Viterbi decoder, a determination step of determining which of "0" and "1" is smaller in the path memory data of the N-th (N is an integer of 1 or more) bit of the path memory, A step of calculating a ratio of "0" or "1" judged to be small by the judgment step in the N-th path memory data, and outputting the ratio as a bit error rate. A method for detecting a bit error rate of a Viterbi decoder, characterized by: