JP2522364B2 - Method for manufacturing thin film field effect transistor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a thin film field effect transistor used for a matrix display device and the like, and a method for manufacturing the same.

(Prior Art) In recent years, various types of thin film transistors have been proposed with the spread of active matrix liquid crystal display elements. At present, all of the ones that have been put to practical use have an inverted staggered structure in which the gate is arranged below the laminated film and the source and drain are arranged above the laminated film. (SEMICONDUCTORS AND SEM)
I-METALS Vol. 21, Part D, Item 89) See LeComber and Spear et al.) In the conventional thin film transistor, as shown in FIG. 4, the gate electrode 1 and the gate insulating film are formed on the insulating substrate. Amorphous silicon nitride thin film as 2,
An amorphous silicon thin film 3 is formed in this order, a phosphorus-doped amorphous silicon thin film 4 is further formed thereon, and Cr electrodes 5 as source and drain electrodes are arranged on the amorphous silicon thin film 4 to form a channel layer. Forming contacts. In this case, as it is, the drain part and the source part are in the normal state of being doped with phosphorus-doped amorphous silicon thin film, and the transistor operation is not performed. It was necessary to completely remove it by etching.

(Problems to be Solved by the Invention) However, since it is difficult to uniformly etch only a phosphorus-doped amorphous silicon thin film in a large area, a certain amount of non-doped layers below the amorphous silicon thin film cannot be uniformly etched. It was etched to the depth to completely remove the phosphorus-doped layer. However, stopping the etching while sufficiently satisfying the uniformity and reproducibility was considerably unstable with respect to the environment at the time of etching or a slight change in the surface condition due to the process.
For example, if a thin natural oxide film is generated on the surface or if a trace amount of organic matter remains, the etching rate changes, the time required for etching changes, and even if etching is performed for the same time under the same conditions. It will not be etched to the same depth. Therefore, there is a problem in that even if the devices are manufactured under the same conditions, variations occur among the devices. Particularly, when the liquid crystal display element is repeatedly manufactured, a fairly strict control is required to ensure reproducibility.

It is an object of the present invention to provide a thin film field effect transistor having a structure capable of eliminating the instability caused by the etching removal and realizing the reality of source / drain separation with good reproducibility, and a manufacturing method thereof.

(Means for Solving the Problems) A method for manufacturing a thin film field effect transistor of the present invention is
A gate electrode, a gate insulating film, and a silicon thin film are formed in this order on an insulating substrate, a Group 5 element or its compound is ion-implanted over the entire surface of the silicon thin film, and a source / drain electrode is further formed. A group 3 element or a compound thereof is ion-implanted into the silicon thin film between the contact region with the drain electrode to form a high resistance region.

(Function) Ion implantation can control the distribution of implanted impurities in the depth direction very precisely, and even when applied to a large area, it can be performed with higher uniformity and reproducibility than etching. On the other hand, when an amorphous semiconductor thin film layer doped with a Group 5 element such as phosphorus or a compound thereof is doped with a Group 3 element such as boron or a compound thereof,
Carrier compensation is provided. At this time, if the doping of the Group 5 element and the doping of the Group 3 element are performed by ion implantation, the distributions in the depth direction of both are sufficiently matched for compensation. Taking advantage of this, after sequentially forming a gate electrode, a gate insulating film, and a silicon thin film on an insulating substrate,
By ion-implanting the entire group 5 element or its compound without a mask, and then by ion-implanting the group 3 element or its compound into the region on the gate electrode where the source and drain are separated, A thin film field effect transistor can be formed without the step of etching the doping layer.

(Embodiment) FIG. 1 shows a sectional view of an embodiment of the thin film field effect transistor of the present invention. FIG. 2 shows a plan view of this transistor. The process of manufacturing this transistor will be described below.

First, 1000 Å of Cr is deposited on the insulating substrate by the sputtering method. Unnecessary Cr is removed by etching while leaving the pattern of the gate electrode 1 for this Cr. Further, after thoroughly washing this with pure water, an amorphous silicon nitride thin film 4000 Å and a hydrogenated amorphous silicon thin film 3000 Å are continuously formed as the gate insulating film 2 by using the plasma CVD method. Then, phosphorus is ion-implanted uniformly over the entire surface at a dose of 3 × 10 ¹⁵ dose / cm ² at 25 kV. Along with this, phosphorus is distributed as shown in FIG. After removing the natural oxide film formed on the surface with dilute hydrofluoric acid, Cr was sputtered to 500 Å.
Deposit. By annealing this at 230 ℃,
Simultaneously with the formation of the silicide 6 between the amorphous silicon and Cr, the implanted phosphorus is activated in the amorphous silicon to form the active region 4. Where the deposited Cr
Is etched to the pattern of the source / drain electrode 5 overlapping the pattern of the gate electrode 1 in FIG. At this time, since Cr silicide is formed at the interface between Cr and amorphous silicon, this is removed with 3% buffered hydrofluoric acid. Here, using Cr as an ion-shielding mask, boron fluoride (BF ₂ ⁺ ) is uniformly ion-implanted at 35 kV by 3 × 10 ¹⁵ dose / cm ² . Along with this ion implantation, boron atoms are distributed as shown in FIG. When this is annealed at 230 ° C., boron is activated and compensation is performed in this portion, the resistance rises by seven digits or more, and the high resistance region 7 is formed. At this time, fluorine remains in the amorphous silicon thin film,
It does not play a major role in the film by binding to dangling bonds in the film. As a result, the source and drain are accurately separated. Finally, the two layers of amorphous silicon nitride and hydrogenated amorphous silicon are removed by etching except for the island 9 necessary for TFT.

In the above embodiment, the annealing is performed twice, but the final annealing may be performed only once. When boron is ion-implanted, B ⁺ or BF ⁺ may be used instead of BF ₂ ⁺ . In the case of B ⁺ , the injection acceleration voltage is 9 kV, BF ⁺
In case of, the acceleration voltage is set to 24 + V and 3 × 10 ¹⁵ dose / cm ²
Only, ion implantation is good.

(Effects of the Invention) According to the present invention, the source and drain can be separated uniformly over a large area and with good reproducibility.

[Brief description of drawings]

FIG. 1 is a sectional view of an embodiment of the present invention. FIG. 2 is a plan view of an embodiment of the present invention. FIG. 3 is a diagram showing the concentration distribution of impurities in the depth direction. FIG. 4 is a sectional view of a conventional example. In the figure, 1 ... Gate electrode, 2 ... Gate insulating film, 3 ... Amorphous silicon thin film, 4 ... Active region, 5 ... Source or drain electrode, 6 ... Cr silicide, 7 ... High Resistance region, 9 ... Island.

Claims (1)

(57) [Claims] 1. A gate electrode on an insulating substrate from a substrate side,
A gate insulating film and a silicon thin film are formed in this order, and a Group 5 element or a compound thereof is ion-implanted on the entire surface of the silicon thin film,
Further, after forming the source / drain electrodes, a high resistance region is formed by ion-implanting a Group 3 element or a compound thereof into the silicon thin film between the contact regions of the source and drain electrodes. Manufacturing method.