JPH0746728B2 - Method for manufacturing semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a thin film field effect transistor (hereinafter abbreviated as TFT) using a silicon compound semiconductor thin film such as amorphous silicon.

Configuration of Conventional Example and Problems Thereof FIG. 1 is a process sectional view of a TFT using a conventionally developed silicon compound semiconductor (for example, amorphous silicon). First, as shown in FIG. 1A, a first metal layer 2 (for example, NiCr) serving as a gate electrode is selectively deposited on an insulating substrate, for example, a glass plate 1. Next, a gate insulating layer 3 (for example, a silicon nitride film), an amorphous silicon layer 4 containing no impurities, and an amorphous silicon layer 5 containing impurities (for example, a p-doped n-type amorphous silicon layer) are formed on the entire surface. To wear. When using amorphous silicon doped with phosphorus as an impurity, the electric conductivity is 10 ^-2 to 10 ^-3 (Ω
/ □) ^{-1 A} film thickness of 500Å or more is required.

Thereafter, the amorphous silicon layers 4 and 5 shown in FIG. 1 (b) are selectively removed to form island-shaped amorphous silicon layers 4'and 5 '. Although not shown in FIG. 1, an opening is formed in the gate insulating layer 3 on the first metal layer 2 to partially expose the first metal layer 2 and then, as shown in FIG. 1 (c). In this way, a pair of source / drain wirings 6 and 7 made of the second metal layer partially overlapping the first metal layer 2 are selectively deposited so as not to form the offset and gate structures.

Finally, as shown in Fig. 1 (d), source / drain wiring
By removing the amorphous silicon layer 5'on the amorphous silicon layer 4'which does not contain impurities by using 6 and 7 as a mask, the conventional TFT
Is completed.

Here, as shown in FIG. 1 (c), the amorphous silicon layer 5'containing impurities is selectively removed using the source / drain wirings 6 and 7 as masks. If the amorphous silicon layer containing impurities remains between the source / drain wirings 6 and 7 insufficiently, the leak current between the source / drain increases, and therefore it must be completely etched. In a specific combination, molybdenum is used for the gate metal layer 2, amorphous silicon layer 5'containing phosphorus as an impurity, aluminum is used for the source / drain wirings 6 and 7, and the etching liquid is hydrofluoric acid: nitric acid = 1: 30 liquid. When used, the etching speed of the amorphous silicon layer is accelerated by about 5 to 10 times, and the amorphous silicon layer up to 5000 Å containing no impurities is only 4 to 4 times.
It disappears in 5 seconds. If the channel section becomes too thin
The on-current of the MIS transistor is remarkably reduced, and it is not rare that it is 1/100 or less as compared with the case of proper etching. However, there is no etching material with a large selection ratio of amorphous silicon containing impurities and amorphous silicon not containing impurities, in other words, there is no etching material with a large difference in etching speed, and a stable and reproducible etching material is used. The engraving speed is as fast as 200-300Å / sec
It is difficult to selectively remove a large area uniformly only in the amorphous silicon layer containing 0Å impurities.

Therefore, as shown in FIG. 1D, when the amorphous silicon layer 5'containing impurities is removed, the silicon layer 4'containing no impurities is also partially removed by over-etching to form the concave portion 10. . Here, in a TFT having a good ohmic contact between the semiconductor active region and the source / drain electrodes and having a ratio W / L of the channel width W to the channel length L of 1, the gate voltage Vg = 12v, the drain voltage Vd = 12v, and the source grounded A current of about 3 × 10 ^-6 A flows under the conditions. However, the electric conductivity of the layer 5'which should be provided in ohmic contact with the layer 4'which becomes the semiconductor active region and the source / drain electrode wirings 6 and 7 is 10%.
^For TFTs as bad as ^-6 to 10 ^-7 (Ω / □) ^-1 , the thickness of layer 5'is 7
Even if it is about 00Å, under the same conditions as above (Vg = Vd = 12v, grounded source), only a current of 1 × 10 ⁻⁸ A or less flows, and good ohmic contact cannot be obtained.

Further, when an enhancement type TFT having a phosphorus-doped n-type amorphous silicon layer as the amorphous silicon 4'containing impurities is heat-treated in N ₂ at 250 ° C. for 1 hour, as shown in FIG. The dark current in the OFF state (gate voltage Vg = O) increases by about two orders of magnitude compared to before the heat treatment, and the electrical characteristics deteriorate. It is considered that this is because the blocking effect for holes of the n-type amorphous silicon layer 4'becomes worse with the heat treatment.

An object of the present invention is to solve the above-mentioned conventional problems. For example, a method for manufacturing a highly reliable semiconductor device by suppressing an increase in dark current in an OFF state after one hour at 250 ° C. in N ₂ is suppressed. The purpose is to provide.

According to the present invention, after the non-single-crystal silicon compound semiconductor layer is formed, an n-type or p-type microcrystalline silicon compound semiconductor layer is formed to obtain ohmic contact between the semiconductor layer and the source / drain electrode. With the manufacturing method capable of stabilizing the removal process of the n-type or p-type microcrystalline silicon compound semiconductor layer on the channel portion using the drain electrode as a mask, and suppressing deterioration of transistor characteristics in a thermal process after completion of the transistor. is there.

Description of Embodiments FIG. 2 is a process sectional view of a semiconductor device of the present invention. It should be noted that each part having the same function is given the same number as in FIG.

First, as shown in FIG. 2 (a), a first metal layer 2 (for example, Ni
Cr) is selectively deposited. Next, on the entire surface, a gate insulating layer 3 made of, for example, a silicon nitride layer, an amorphous silicon layer 4 as a non-single-crystal silicon compound semiconductor layer containing no impurities such as groups III and IV, and impurities such as P and B are included. An n-type or p-type microcrystalline silicon compound semiconductor layer 15 is deposited. These deposition methods are
If silicon nitride is to be formed as the gate insulating layer 3 by using the plasma deposition method by glow discharge of silane-based gas, it can be obtained by mixing ammonia (NH ₃ ) and nitrogen. Further, the manufacturing conditions of microcrystalline silicon containing impurities, for example, n ⁺ type microcrystalline silicon are as follows. Gas of silane 5sccm, phosphine 0.07sccm, H ₂ 150sccm was mixed, vacuum degree 1.4Torr, substrate temperature 260 ℃, high frequency power 200W (electrode diameter 30cm) at 13.56MHz, electrode spacing 22mm, X
The existence of a crystalline region has been confirmed by observation of line diffraction. The sheet resistance is 10 (Ωcm) ^{-1 and the} activation energy is 0.02 eV. Thus, the n ⁺ type microcrystalline silicon film 15 is deposited by about 150 Å.

After that, as shown in FIG. 2B, the amorphous silicon layer 4, n ⁺
Type microcrystalline silicon layer 15 is selectively removed to form layers 4'and 15 '
To form an island region. Although not shown in FIG. 2, an opening is formed in the gate insulating layer 3 on the first metal layer 2 to partially expose the first metal layer 2 and then, as shown in FIG. As described above, a pair of source / drain wirings 6 and 7 made of a second metal layer, for example, Al, which partially overlaps the first metal layer 2 is selectively deposited so as not to form an offset gate structure. . Finally, as shown in FIG. 2D, using the source / drain wirings 6 and 7 as a mask, the n ⁺ -type microcrystalline silicon layer on the amorphous silicon layer 4 ′ containing no impurities is used.
By removing 15 ', the inverted stagger type TFT is completed.

When HF: HNO ₃ 1:30 is used as a stable etching material here, the etching rate of the microcrystalline silicon layer 15 ′ containing impurities is 400 to 500 Å / sec, and the amorphous silicon layer containing no impurities. 4'etching rate (200-300Å / sec)
, Which is about twice that of the above, and the selection ratio is improved.

Further, as shown in FIG. 2D, when the microcrystalline silicon layer 15 'containing impurities is removed, the amorphous silicon 4'containing no impurities is also partially removed by over-etching to form the concave portion 20. To do. However, in this case, the thickness of the film containing impurities is 15
The film thickness is 0Å, which is less than one-third that of the conventional film thickness of 500Å.

Considering that the impurities in the film containing impurities are diffused into the amorphous silicon film not containing impurities, if overetching is performed by the same amount as the thickness of the film containing impurities, in the conventional case, Approximately 1000Å is required to be etched, and in the TFT according to the present invention, the total thickness to be etched is less than one third of the conventional thickness of 300Å. Here, as one of the etching methods, first, by dipping in fuming nitric acid, and then by dipping in 0.01 mol solution of hydrofluoric acid, microcrystalline silicon containing impurities is etched by about 50 Å. Therefore, if it is repeated about 6 times, about 300Å will be etched. According to this method, the conventional TFT needs to be repeated 20 times, and in consideration of variations and uncertainties due to the increase in the number of times, the conventional TFT was not carried out. The introduction of the crystalline silicon layer established a stable etching method.

In addition, an oxide film is formed by an anodic oxidation method utilizing the large difference in electric conductivity between the microcrystalline silicon layer 15 containing impurities and the amorphous silicon layer 4 not containing impurities, and the method of etching with hydrofluoric acid is used. If the sheet resistance is low (10Ωc
m ^-1 ) is a great advantage.

Also, probably because the sheet resistance of the n ⁺ type microcrystalline silicon layer 15 ′ according to the present invention is low, if the film thickness is only 150 Å, which is one-third or less of the conventional value, a current value slightly higher than the conventional value can be obtained. . Furthermore, as an enhancement type TFT having an n-type microcrystalline silicon layer doped with phosphorus as a microcrystalline silicon layer containing impurities, even after heat treatment at 250 ° C. in N _{2 for} 1 hour,
As shown in FIG. 4, the current value in the OFF state (gate voltage Vg = o) hardly changed as compared with that before the treatment, and a TFT having a large temperature degree of freedom in a highly reliable process was obtained. It is considered that, regardless of the heat treatment, the blocking effect for holes of the n-type microcrystalline silicon layer is not inferior to the initial stage.

EFFECTS OF THE INVENTION By using microcrystalline silicon containing impurities, the film thickness can be made as thin as 150Å. Therefore, the accuracy of removing the semiconductor layer containing impurities on the channel portion is improved by the new etching method. Further, TFT prepared according to the invention, in N _2, 25
Even after heat treatment at 0 ° C for 1 hour, deterioration of blocking effect for minority carriers of ohmic contact layer made of microcrystalline silicon compound semiconductor is suppressed, and change of drain current in OFF state can be reduced, resulting in improved heat resistance of TFT. Therefore, there is an effect that a highly reliable TFT can be manufactured without deterioration of TFT characteristics in the thermal process after completion of the TFT.

[Brief description of drawings]

1A to 1D are process sectional views of a conventionally developed TFT, FIGS. 2A to 2D are process sectional views of a TFT according to an embodiment of the present invention, and FIG. FIG. 4 is a characteristic diagram of the developed TFT, and FIG. 4 is a diagram showing electrical characteristics of the TFT according to the present invention before and after heat treatment in N ₂ at 250 ° C. for 1 hour. 1 ... Glass plate, 2 ... Gate electrode, 3 ... Gate insulating film, 4 ... Amorphous silicon layer containing no impurities, 6,7 ...
… Source / drain wiring, 15 …… Microcrystalline silicon layer containing impurities.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ikunori Kobayashi 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Seiichi Nagata, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (56) References JP-A-58-212177 (JP, A)

Claims (1)

[Claims] 1. A method of manufacturing a thin film field effect transistor having an inverted stagger structure using an amorphous silicon semiconductor layer in a semiconductor active region, the method comprising the steps of sequentially forming a gate insulating film and the amorphous silicon semiconductor layer, Forming an n-type or p-type microcrystalline silicon semiconductor layer on the semiconductor layer;
Forming a source / drain electrode on the microcrystalline silicon semiconductor layer, and removing the microcrystalline silicon semiconductor layer with an etching solution containing hydrofluoric acid and nitric acid as main components, using the source / drain electrode as a mask. A method of manufacturing a semiconductor device, comprising: