JP2531833B2 - Level conversion circuit - Google Patents

Description

The present invention relates to a level conversion circuit, and more particularly to a level conversion circuit for converting a level of an ECL logic level to a CMOS logic level in a BICMOS type logic circuit.

[Conventional technology]

Conventionally, as a level converter of this type, the circuit shown in FIG. 3 is generally well used. As shown in FIG. 3, the conventional level conversion circuit has P-channel MOS transistors 13 and 15 and N-channel MOS transistors 14 and 16.
When the ECL logic level is inputted to the input terminals 59 and 60 as the logic levels A and, respectively, the logic level from the output terminal 61 becomes
A predetermined CMOS logic level is output.

[Problems to be resolved by the invention]

In the conventional level conversion circuit described above, in FIG. 3, when the ECL logic level is input to the input terminals 59 and 60, the CMOS logic level is output from the output terminal 61. Now, at the ECL logic levels A and A inputted from the input terminals 59 and 60, when A is high and low, the P-channel MOS transistor 13 is off. Therefore, the N-channel MOS transistors 14 and 16 are also OF
The state becomes F, and only the P-channel MOS transistor 15 turns on.
It becomes the state of. That is, as the logic level output from the output terminal 61, the power source voltage V _CC supplied from the terminal 62, that is, the CMOS logic level high is output.

Next, when the input ECL logic level A is low and high, only the P-channel MOS transistor 15 is turned off and the other transistors 13, 14 and 16 are turned on. Therefore, in this case, as the logic level output from the output terminal 61, the CMOS logic level low is output. In this state, both the P-channel MOS transistor 13 and the N-channel MOS transistor 14 are in the ON state, so that the through current constantly flows. This operation state is as shown in FIG. 4, and it can be seen that the mirror current (1) constantly flows corresponding to the logic levels A and. That is, there is a drawback in that the shoot-through current is constantly consumed as consumption current.

[Means for solving the problem]

The level conversion circuit of the present invention includes a current mirror circuit,
In a level conversion circuit formed by including a MOS transistor that outputs a mirror current, the mirror current is controlled and supplied by a first MOS transistor that supplies a constant mirror current and an output logic level of the level conversion circuit. And a second MOS transistor that functions as a current mirror circuit.

〔Example〕

Next, the present invention will be described with reference to the drawings. First
The drawing is a circuit diagram of the first embodiment of the present invention. As shown in FIG. 1, this embodiment includes P-channel MOS transistors 1, 3, 4 and 5, N-channel MOS transistors 2 and 6, and an inverter 7.

In FIG. 1, P-channel MOS transistors 1 and 3 form a current mirror circuit of N-channel MOS transistor 6, and N-channel MOS transistor 2
Set the mirror current of. The P-channel MOS transistor 5 forms an output circuit of the level conversion circuit together with the N-channel MOS transistor 6, and its output is output from the output terminal 53 via the inverter 7, and
When input to the gate of the P-channel MOS transistor 4,
It controls the mirror current of the P-channel MOS transistor 3.

Now, when the input ECL logic level A changes to low, P
The channel MOS transistors 1 and 3 are turned on, and the mirror current is supplied to the N-channel MOS transistor 2, but when the logic level O at the output terminal 53 changes to high, the P-channel MOS transistor 4 for controlling the mirror current is supplied.
Is turned off, and the mirror current is not supplied to the P-channel MOS transistor 3.

FIG. 4 shows the input / output logic level and the mirror current (2) corresponding to the above operation in a time relationship. In FIG. 4, the mirror current (1) indicated by the broken line is as described above.
The mirror current in the conventional level conversion circuit is shown.

Next, a second embodiment of the present invention will be described. Second
The figure is a circuit diagram of the second embodiment. As shown in FIG. 2, in this embodiment, P-channel MOS transistors 7, 9, 11 are used.
And N-channel MOS transistors 8, 10, and 12.

The difference between this embodiment and the first embodiment is that the mirror current of the P-channel MOS transistor 9 is controlled by the N-channel MOS transistor 10, and
The logic level output from the output terminal 57 is directly input for controlling the base of the channel MOS transistor 10. Other operations are similar to those in the first embodiment.

〔The invention's effect〕

As described above in detail, the present invention includes a MOS transistor that constantly supplies a constant mirror current and a MOS transistor that supplies a mirror current controlled by an output logic level as a current mirror circuit. The through current of the current mirror circuit in the steady operation state can be reduced, and the level conversion circuit with low power consumption can be provided.

[Brief description of drawings]

1 and 2 are circuit diagrams of the first and second embodiments of the present invention, FIG. 3 is a circuit diagram of a conventional example, and FIG. 4 is a diagram showing an operating state of the circuit. In the figure, 1,3,4,5,13,15 ... P-channel MOS transistors, 2,6,14,16 ... N-channel MOS transistors, 7 ...
… Inverter.

Claims (1)

(57) [Claims] 1. A level conversion circuit including a current mirror circuit and a MOS transistor for outputting a mirror current, comprising: a first MOS transistor for supplying a constant mirror current; and an output logic of the level conversion circuit. A level conversion circuit comprising: a second MOS transistor controlled to supply a mirror current according to the level; and a current mirror circuit.