JP2532138B2 - Logic circuit delay time analyzer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] An analyzer for delay time of an electric signal in designing a logic circuit, wherein a plurality of sections are provided for the purpose of shortening the design time by facilitating the design of the logic circuit. A distributed graph with a means to calculate the ratio of the delay time for each section to the delay time of the entire critical path from the delay time of the entire critical path and a block diagram in which the calculation result of the above ratio is symbolized. A means for displaying on a graphic display is provided, and when the critical path considering the rising side effective waveform of the electric signal waveform and the critical path considering the falling side effective waveform are the same, as a single distributed graph If the above critical paths are different, display them separately. To.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for analyzing the delay time of an electric signal on the circuit when designing a logic circuit, and in particular, displays the ratio of the delay time for each target path section on a graphic display. The present invention relates to an analysis device that facilitates analysis by displaying it.

[Prior Art] In designing a logic circuit, it is essential to examine whether or not the created logic circuit operates normally.

In a logic circuit, it is important for a certain gate to satisfy a logic condition whether or not an intended signal reaches the gate. Therefore, in the analysis of the logic circuit, a path through which the signal passes. It is necessary to analyze the delay time for each.

Then, if an inconvenient part is detected as a result of the analysis, the operation of correcting the circuit and performing the analysis again is repeated.

FIG. 4 is a diagram showing an example of such a conventional analysis procedure, in which 51 is a master file for CAD, 52 is an FF check program, 53 is an FF check result file, 54 is an analysis program, and 55. Represents a list.

That is, in the figure, the logic circuit designer inputs the designed logic circuit as data according to a predetermined promise as circuit elements and connection conditions, and stores the data in the master file 51 for CAD.

Then, this data is subjected to a path ready check between FFs by the FF check program 52.

 The result is output to the FF check result file 53.

Next, using the data output to the FF check result file 53 as input, the analysis program 54
Perform analysis using.

Since the result is output as a list 55, the logic circuit designer reviews the list and if there is an inconvenient part,
Correct this, repeat the analysis for new data, and repeat this process until the error is eliminated.

[Problems to be Solved by the Invention] The analysis of a logic circuit as described above is indispensable in designing a logic circuit, and the analysis is performed in order to realize a highly reliable logic circuit. The results are of a nature that must be carefully examined and reliably fed back to the original design.

However, the above-mentioned method that has been conventionally performed has the following problems.

Since the analysis is performed by batch processing, it takes time to obtain the processing result, and it is easily influenced by the processing status of other jobs in the processing apparatus.

Since the output of the analysis result by the analysis program is in the list format, it is difficult to decipher it and error is likely to occur.

Although the section delay time between each pin could be known by the analysis program, there was no way to know the ratio of the delay time of each section to the entire FF path delay time in the FF path. Therefore, the conventional method is not always good in processing efficiency, and the logic circuit designer knows the section delay based on the hard copy of the critical path displayed in the FF check result list or the graphic delay, There is a problem that it takes a lot of time in the process of modifying the circuit because the work such as calculating the ratio by a calculator or manual calculation must be performed.

The present invention has been made in view of such conventional problems, and an object of the present invention is to provide an analysis device that can easily decipher the analysis result and can significantly reduce the time required for the process of correcting the circuit.

[Means for Solving the Problems] According to the present invention, the above-mentioned object is achieved by the means described in the claims.

That is, the delay time analysis device for a logic circuit of the present invention is
A device for analyzing the delay time of an electric signal in a logic circuit, and calculates the ratio of the delay time of each section to the delay time of the entire critical path from the delay time of the entire critical path consisting of multiple sections. Means and a means for displaying a graph in which the delay time for each section is distributed at the ratio together with the block diagram of the logic circuit, and the critical path and the falling edge in consideration of the rising side effective waveform of the electric signal waveform. When the critical paths considering the side effective waveform are the same, they are displayed as one graph, and when the above critical paths are different,
The feature is that they are displayed separately.

[Operation] According to the present invention, in order to facilitate the analysis of the worst case of the delay condition (which is referred to as a critical path in this specification) in the inter-FF path delay analysis by using the above means. For example, the following means can be taken.

The analysis result, which was in the form of a list in the past, is displayed on a graphic display using multi-window so that it can be analyzed by conversation processing.

The gates and FFs are symbolized and displayed so that the designer can easily understand them.

The interval delay between each pin is displayed not only as a numerical value but also as a percentage of each interval delay with respect to the total delay together with a graph as a percentage. (In this specification, this is referred to as a graphic distribution.) The critical path may have different paths through which the rising edge (UP waveform) of the signal is effective and the falling edge (DOWN waveform) of the signal is effective. However, in the present invention, UP / D
If the OWNs are different, they are displayed in different windows and UP /
If DOWN has the same path, it can be displayed in the same window.

This is also true for graphic distributors.

[Embodiment] FIG. 1 is a block diagram of an embodiment of the present invention.
Is a main control unit, 2 is a command control unit, 3 is an analysis command group, 4 is a display data creation unit group, 5 is a block index display command, 6 is a pin index display command,
Reference numeral 7 is a critical path display command, 8 is a graphic distribution display command, and 9 to 12 are display data creating sections.

In the figure, the command control unit 2 has a function of calling a command selected by the main control unit 1.

The block index display command 5 creates block index information and outputs an index list.

The pin index display command 6 creates pin index information and outputs a pin index list.

The critical path display command 7 outputs data for displaying a critical path with the specified pin as a target pin in a block diagram.

Graphic distribution display command 8 is
Create and output a graphic distribution based on the specified critical path.

Each display data creation unit 9 belonging to the display data creation unit group 4
Reference numerals 12 to 12 edit the data output by the corresponding commands and display the edited data on the display of the display unit.

FIG. 2 is a diagram showing a display example of a procedure until a graphic distribution graph is displayed by using this embodiment, and FIG. 2A is a block index display of a logic block existing on a target logic circuit. , (B) shows the pin index display of the pin on the block specified by the designer, and (c) shows the critical path among the paths reached by the designer as a block diagram. (D) shows a state in which a graphic distribution graph is displayed in the block diagram by selecting a graphic distribution display command in the block diagram designated by the designer.

FIG. 3 is a diagram showing an example of a critical path displaying a graphic distribution. 13, 16 are symbolized FFs, 14 and 15 are symbolized gates, and 17 are numerical values. Total delay value, 18
Is a block index, and 19 and 20 are graphic distributions.

[Effects of the Invention] As described above, according to the present invention, it is possible to greatly reduce the time required to analyze the delay time of an electric signal in designing a logic circuit and modify the circuit based on the analysis result. Becomes

That is, conventionally, the logic circuit designer knew the interval delay based on the FF check result list, the hard copy of the critical path displayed in the graphic delay, etc., and calculated the ratio with a calculator or hand calculation. Although it takes a lot of time and labor, in the present invention, the result can be instantly and visually obtained only by selecting the command. Therefore, there is an effect that the time required for the logic circuit designer to modify the circuit can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an example of a display procedure of displaying a graphic distribution graph of the embodiment, and FIG. 3 is a critical diagram showing a graphic distribution. FIG. 4 is a diagram showing an example of a path, and FIG. 4 is a diagram showing an example of a conventional analysis procedure. 1 ... Main control unit, 2 ... Command control unit, 3 ... Analysis command group, 4 ... Display data creation unit group, 5 ... Block index display command, 6 ... Pin index display command, 7 ... Critical・ Path display command,
8: Graphic distribution display command,
9 to 12 ... Display data creation unit, 13, 16 ... Symbolized FF, 14, 15 ... Symbolized gate, 17 ... Total delay value, 18 ... Block index, 19, 2
0 …… Graphic Distributor

Claims (1)

(57) [Claims] 1. An apparatus for analyzing a delay time of an electric signal in a logic circuit, wherein the delay time of each critical path consisting of a plurality of sections is compared with the delay time of each critical path. Means for calculating the ratio of the electric circuit and the block diagram of the logic circuit, and a means for displaying a graph in which the delay time for each section is distributed at the ratio, and a critical value considering the rising side effective waveform of the electric signal waveform.・ Critical considering the path and falling side effective waveform ・
If the paths are the same, display them as one graph,
A delay time analysis device for a logic circuit, wherein each of the critical paths is displayed separately when the critical path is different.