JP4006062B2 - Logic circuit analyzer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a logic circuit analysis method, and more particularly to a logic circuit analysis method used when tracing a signal flow of a designed logic circuit.
In designing a logic circuit, when a target result is not obtained as a result of simulation, the logic circuit is analyzed by tracing the input / output logic of each logic block.
[0002]
[Prior art]
Conventionally, after simulating a logic circuit, tracing is performed by specifying a pin for performing back tracing by manual operation based on the result of the simulation.
If a pin different from the pin to be reached is designated, the pin is designated again and traced, and the above operation is repeated until the desired pin is reached.
[0003]
Therefore, in order to efficiently analyze the logic circuit, for example, according to Japanese Patent Laid-Open No. 5-225286, the input / output signal system is displayed separately from the other signal systems to recognize the signal system. An invention has been proposed that facilitates analysis.
Japanese Patent Application Laid-Open No. 5-225286 discloses a circuit element for extracting a path between input / output pins by simply designating an input / output pin and performing a path trace between the input / output pins and color-coding with other signal lines. A connection search method is described.
[0004]
[Problems to be solved by the invention]
However, in the conventional logic circuit analysis method, since the tracing is performed by instructing the branch destination (path) by manual operation based on the result of the simulation, the branch destination has to be instructed by manual operation, which is incorrect. In some cases, it was necessary to go back to the original pin, specify a different pin from the previous pin, apply the backtrace again, and repeat until the required pin could be analyzed. Met.
[0005]
Further, the invention disclosed in Japanese Patent Laid-Open No. 5-225286 extracts the path between the input / output pins by simply designating the input / output pins and performing the path trace between the input / output pins, and is color-coded with other signal lines. It is possible to recognize only one system signal. For other paths, it is necessary to specify input / output pins again and perform path trace. If you want to analyze the entire logic circuit, Similarly, the analysis takes time and is inefficient.
[0006]
The present invention has been made in view of the above points, and an object thereof is to provide a logic circuit analysis method capable of easily tracing a desired path.
[0007]
[Means for Solving the Problems]
Claim 1 of the present invention is a logic circuit analyzing apparatus for performing a process of analyzing a flow of a signal logical block, pin signal flows before Symbol logic blocks, and analyzes the connection of the pin, and records An analysis unit ; a pin through which the signal of the logical block recorded by the analysis unit flows; and a display unit that displays a connection relation of the pin. The analysis unit can flow the signal of the logic block. It is characterized by having path trace means for analyzing and recording all the pins having the characteristics and the connection relation of the pins.
[0008]
According to the first aspect, by analyzing, recording, and displaying the pin through which the logic block signal flows and the connection relationship between the pins, the transmission source can be easily recognized for each pin. The branch destination can be easily recognized. Therefore, the trace branch destination can be easily selected and the analysis can be performed efficiently .
[0009]
In addition, according to the first aspect, by analyzing and recording all the pins on which the logic block signal may flow and the connection relation of the pins by the path trace means , the transmission source can be easily set for each pin. Therefore, the branch destination of each pin can be easily recognized at the time of tracing, so that the branch destination of the trace can be easily selected and the analysis can be performed efficiently.
[0010]
According to a second aspect of the present invention, the analysis unit includes a pin through which a logical signal of the logic block flows, and a simulation unit that analyzes and records a connection relation of the pin. According to claim 2, pin by simulation means flows logically signal of logic blocks, and analyzes the connection of the pin, by recording, to recognize the state of the signal at each pin at a predetermined logic The trace branch destination can be easily selected according to the signal state, and the analysis can be performed efficiently.
[0011]
Claim 3, the path trace means, all pins that may signal the logical block flows in the same direction as the flow of the signal, and a forward tracing means for analyzing the connection relationships of the pin, and records And all the pins analyzed and recorded by the forward trace means , and all the pins in which the signal of the logic block may flow in a direction opposite to the signal flow with respect to the connection relation of the pins, and And a back trace means for analyzing the connection relation of the pins and narrowing down the connection relation between the pins and the pins.
[0012]
According to the third aspect, after analyzing and recording all the pins in which the logic block signal may flow by the forward trace means and the connection relation of the pins, the logic traced by the forward trace means by the back trace means By narrowing down the desired pins based on all the pins that can cause the block signal to flow and the pin connection relationship, it is possible to easily recognize the branch destinations of the necessary pins, thus making it easy to select the branch destination of the trace. Can be performed efficiently.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing an embodiment of the present invention.
The logic analysis apparatus 1 to which the logic analysis method of this embodiment is applied has a keyboard 2, a mouse 3, an input interface 4 for inputting instructions from the keyboard 2 and the mouse 3, and a structure of a logic circuit to be analyzed. A stored logic circuit database 5, a CPU 6 that performs analysis processing, a program memory 7 that stores programs to be processed by the CPU 6, an analysis result storage unit 8 that stores analysis results at the CPU 6, and a CRT 9 that displays the analysis results , A display controller 10 that controls display on the CRT 9, an input interface 4, a logic circuit database 5, a CPU 6, a program memory 7, and an analysis result storage unit 8.
[0014]
The logic analysis device 1 performs a process of analyzing the connection of the logic circuit based on the logic circuit data stored in the logic circuit database 5 according to an analysis program stored in advance in the program memory 7.
The program stored in the program memory 7 has a path trace function for analyzing the path of the logic circuit, and a simulation function for setting a predetermined initial setting value in the logic circuit and analyzing the input / output logic. The analysis result is stored in the analysis result storage unit 8.
[0015]
The analysis result stored in the analysis result storage unit 8 is converted into image data by the display controller 10 and displayed on the CRT 9.
Next, the analysis operation by the CPU 6 will be described.
FIG. 2 shows a processing flowchart by the CPU of one embodiment of the present invention.
When the CPU 2 is instructed by the keyboard 2 and the mouse 3 to perform a trace function for performing a path trace of the logic circuit stored in the logic circuit database 5, the CPU 6 first determines the logic circuit to be analyzed by the program stored in the program memory 7. Designation of hierarchy is instructed. When the hierarchy of the logic circuit to be analyzed is designated by the keyboard 2 and the mouse 3, the logic circuit data is read at the designated hierarchy from the logic circuit database 5 (step S1-0).
[0016]
Next, it is determined whether or not the logic circuit to be analyzed is a scan chain (step S1-1).
If it is not a scan chain in step S1-1, each path is traced, a mark is given to a pin through which the path passes, and stored in the analysis result storage unit 8 (step S1-2).
[0017]
Here, the path trace will be described with reference to FIG.
FIG. 3 is a diagram for explaining the operation of path tracing according to an embodiment of the present invention. FIG. 2 shows the case of the AND gate. In the case of the AND gate, the signal supplied to the input pin a is not supplied to the output pin c if the logic of the input pin b is “0”, but the input pin a is input. When the logic of the pin b is “1”, it is supplied to the output pin c. For this reason, the path trace is determined to be a path through which signals pass in both paths a → c and b → c. That is, in the path trace, not all the paths that logically pass are traced, but all paths that the logic may pass are traced.
[0018]
On the other hand, in the simulation, since the logic of the output pin c is determined according to the logic of the input pin b, it is determined that the path a → c does not pass. As described above, all path traces that may pass through are sequentially determined.
If it is a scan chain system in step S1-1, the CPU 6 performs forward trace and back trace in each of the scan system and clock system, narrows down the path, and stores the result in the analysis result storage unit 8 (step S1). S1-3).
[0019]
Further, when the pins are marked in step S1-2 and step S1-3, and the connectable pins are recorded for each marked pin, the CPU 6 next performs a simulation. In the simulation, first, initial setting values to be supplied to the input terminals of the logic circuit to be analyzed are set (step S1-4).
Next, a simulation is performed according to the initial setting value set in step S1-4, the signal transmission state of the marked pin is detected, and stored in the analysis result storage unit for each pin (step S1-5). ).
[0020]
Next, the CPU 6 controls the display controller 10 to display the analysis result in the analysis result storage unit 8 together with the logic circuit on the CRT 9 in steps S1-1 and S1-3 (step S1-6).
Next, when the change of the initial setting value is instructed by the instruction of the keyboard 2 or the mouse 3, the process returns to step S1-4, the initial setting value is changed, and the simulation is performed again (step S1-7).
[0021]
Here, the display result displayed on the CRT 9 in step S1-6 will be described.
FIG. 4 shows a display example of the analysis result of one embodiment of the present invention.
When the analysis result is displayed in step S1-6, the logic circuit 100 is displayed. In the logic circuit 100, marks a to u are given to the input / output pins of the logic blocks 111 to 116, and the logic values “1”, “0”, and “x” of the simulation result are displayed.
[0022]
Below the logic circuit 100, the signal supply source is displayed for each of the input / output pin marks a to u of the logic blocks 111 to 116. For example, the pin marks a to d are input pins of the logic circuit 100, and the signal supply source pin marks a to u are not displayed, so that the signal supply source is empty.
The pin marked e is an input pin of the gate 111 and is connected to the pin marked b which is the input pin of the logic circuit 100, and a signal is supplied from the pin marked b. Therefore, the pin mark b is displayed on the pin mark e. At this time, since the signal supplied to the pin of the pin mark b is the clock CLK, “(CLK)” indicating the clock is given to the pin mark b.
[0023]
Similarly, the pin mark f is an input pin of the gate 111 and is connected to a pin of the pin mark c which is an input pin of the logic circuit 100, and a signal is supplied from the pin of the pin mark c. Therefore, the pin mark c is displayed on the pin mark f. At this time, since the signal supplied to the pin of the pin mark c is the control signal CNT, “(CNT)” indicating the control signal is given to the pin mark c.
[0024]
Further, the pin mark h, which is an output pin of the gate 111, is supplied with an output result corresponding to the logic of the signal supplied to the pins of the pin marks e and f, so that the pin marks e and f are displayed. , Pin marks b (CLK) and c (CNT) which are signal supply sources of the pin marks e and f are displayed. Similarly, the signal supply source is displayed on the pin marks g to u.
[0025]
A display showing the pin mark of the simulation signal source is displayed below the logic circuit 100 and on the left side of the display of the path trace signal source.
For example, a logical value “1” is supplied to the pin mark a, a logical value “0” is supplied to the pin mark b, a logical value “1” is supplied to the pin mark c, and a logical value “1” is supplied to the pin mark d. Then, since the pin marks e, f, g, m are directly connected to the pin marks a, b, c, d, the logic “1”, “0”, “ “1” and “1” are supplied as they are. Therefore, as a simulation signal source, pin mark b (CLK) is displayed on pin mark e, pin mark c (CNT) is displayed on pin mark f, pin mark d is displayed on pin mark g, and pin mark a is displayed on pin mark m. .
[0026]
Further, in the pin mark h, if the gate 111 is an AND gate, the pin mark c (() when the logic value of the pin mark b (CLK) is “0”, that is, the logic value of the pin mark e is “0”. Regardless of the logical value of CNT), that is, the logical value of the pin mark f, the logical value of the pin mark h that is the output of the gate 111 is “0”. Therefore, as a result of simulation, it can be determined that the signal supplied to the pin mark b (CLK), e is supplied to the pin mark h, and the pin mark b (CLK), e is displayed on the pin mark h. The
[0027]
As a result of the simulation using the initial setting values as described above, the pin marks a to u through which the logic passes are displayed for each pin mark a to u.
As shown in FIG. 4, pin marks a to u are displayed on the logic circuit 100, and a logic value of a simulation result corresponding to a predetermined initial setting value is displayed for each path. Further, as described above, pin marks that can be traced for each of the pin marks a to u and pin marks that can be passed as a result of a predetermined initial setting value are displayed in a list form below the logic circuit 100.
[0028]
For this reason, when a predetermined output is not obtained with respect to a predetermined initial setting value in the logic circuit 100, when back tracing is performed on the logic circuit 100 in order to analyze the logic circuit 100, FIG. By recognizing the list for each pin mark displayed at the bottom of the logic circuit 100 as shown, the branch destination from each pin can be easily recognized and the next pin can be easily selected, so that the trace can be efficiently performed. Yes.
[0029]
In this embodiment, the logic circuit format is determined in step S1-2. In the case of a scan chain, in addition to the forward trace in step S1-1, the back trace is further performed in step S1-3. The analysis can be performed by narrowing down the path.
FIG. 5 is a diagram for explaining the operation at the time of analysis of the scan chain according to one embodiment of the present invention.
[0030]
The logic circuit 200 forms a scan chain. The scan chain includes gates 211 to 214 and flip-flops 221 to 223, and the gates 211 to 213 and flip-flops 221 to 223 are alternately arranged.
In the case of a scan chain, the path from the input terminal SI to the output terminal SO is detected by a forward trace from the input terminal SI and a back trace from the output terminal SO in the scan system, as shown by “=” in FIG. The path of pin mark b → g → j → l → m → n → p → r → s → t → v → x → y → z is recognized.
[0031]
As for the clock system, forward tracing is performed from the clock input TCK, back tracing is performed from the clock terminals of the flip-flops 221 to 223, and a path from the clock input TCK to the flip-flops 221 to 223 is detected. − ”Recognizes paths of pin marks a → f → i → k, a → f → i → q, and a → f → i → w as shown by bold lines.
[0032]
Note that pin marks a to z are given to the pins of each logical block at the time of scanning and clock tracing.
As described above, when the logic circuit has the scan chain structure, the scan system and the clock system can be easily recognized by displaying the path, and when the back trace is performed at the time of analysis, it can be easily recognized where the signal is stagnant.
[0033]
Also, when displaying a path, by distinguishing the signal attributes by line type or color, it is possible to easily identify the signal attributes: scan signals, clock signals, or control signals. it can.
For example, in FIG. 5, the scan signal is displayed as “=”, the clock signal is displayed as a “−” thick line, and the control signal is displayed as a “−” thin line.
[0034]
Further, when signals having different attributes pass through the same line, the signals can be reliably identified by displaying the signals having different attributes in parallel. For example, in FIG. 5, in the pin marks j → i, m → n, p → r, s → t, v → x, and y → z, the scan signal is “=” and the control signal is “−”. Thin lines are displayed in parallel.
[0035]
In this embodiment, the scan system signal, the clock system signal, and the control system signal are displayed according to the line type such as “=”, “−” thick line, “−” thin line, but the present invention is not limited to this. You may display according to a color instead of a thing.
Further, by specifying the logical hierarchy or the physical hierarchy of the logic circuit to be analyzed in step S1-0, the analysis can be performed at a necessary hierarchy.
[0036]
FIG. 6 is a diagram for explaining display according to the hierarchy of an embodiment of the present invention.
For example, in step S1-0, when the hierarchy of the logic circuit 310 is designated as the most detailed level 1 and analysis is performed, the logic elements 311 to 316 are displayed as shown in FIG. Pin marks a to c, f to l, p to v, and x are given to the input / output pins and displayed.
[0037]
In step S1-0, if the hierarchy of the logic circuit 310 is designated as level 2 of a hierarchy higher than level 1, and analysis is performed, logic blocks 321 and 322 are displayed as shown in FIG. , 322 are given pin marks a to e, mo to w, x, and displayed.
In this way, by specifying the hierarchy, the analysis can be performed in a desired unit such as a logic element unit or an LSI unit, so that the analysis can be efficiently performed in the logic circuit.
[0038]
【The invention's effect】
As described above, according to the first aspect of the present invention, by analyzing, recording, and displaying the pin through which the logic block signal flows and the pin connection relationship, the transmission source can be easily recognized for each pin. Therefore, it is possible to easily recognize the branch destination of each pin at the time of tracing, so that it is possible to easily select the branch destination of the trace and to perform analysis efficiently.
[0039]
In addition, according to the first aspect, by analyzing and recording all the pins on which the logic block signal may flow and the connection relation of the pins by the path trace means , the transmission source can be easily set for each pin. Therefore, it is possible to easily recognize the branch destination of each pin at the time of tracing. Therefore, it is possible to easily select the branch destination of the trace and to perform analysis efficiently.
[0040]
According to claim 2, pin by simulation means flows logically signal of logic blocks, and analyzes the connection of the pin, by recording, to recognize the state of the signal at each pin at a predetermined logic It has features such as easy selection of trace branch destinations according to the signal state, and efficient analysis. According to the third aspect, after analyzing and recording all the pins in which the logic block signal may flow by the forward trace means and the connection relation of the pins, the logic traced by the forward trace means by the back trace means By narrowing down the desired pins based on all the pins that can cause the block signal to flow and the pin connection relationship, it is possible to easily recognize the branch destinations of the necessary pins, thus making it easy to select the branch destination of the trace. It has the feature that it is possible to perform analysis efficiently.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 2 is an operation flowchart of a CPU according to an embodiment of the present invention.
FIG. 3 is a diagram for explaining a path trace operation according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a display example of an analysis result according to an embodiment of the present invention.
FIG. 5 is an operation explanatory diagram at the time of scan chain analysis according to an embodiment of the present invention.
FIG. 6 is a diagram for explaining display according to a hierarchy according to an embodiment of the present invention;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Logic circuit analyzer 2 Keyboard 3 Mouse 4 Input interface 5 Logic circuit database 6 CPU
7 Program memory 8 Analysis result storage unit 9 Display controller 10 CRT
11 Bus

Claims (3)

In the logic circuit analyzing apparatus for performing a process of analyzing a flow of a signal logical block,
Pin signal flows before Symbol logic blocks, and analyzes the connection of the pin, and analyzing means for recording,
A pin through which the signal of the logic block recorded by the analyzing means flows, and a display means for displaying a connection relation of the pins;
Further, the analysis means has all the pins through which the signal of the logic block may flow, and path trace means for analyzing and recording the connection relation of the pins. 2. The logic analysis apparatus according to claim 1, wherein the analysis means includes a pin through which a signal logically flows in the logic block, and a simulation means for analyzing and recording a connection relationship between the pins. The path trace means is a forward trace means for analyzing and recording all the pins through which the signal of the logic block may flow in the same direction as the signal flow, and the connection relation of the pins,
All the pins analyzed and recorded by the forward trace means , and all the pins in which the signal of the logic block may flow in the opposite direction of the signal flow with respect to the connection relation of the pins, and 3. The logic analysis apparatus according to claim 2, further comprising back trace means for analyzing a pin connection relationship and narrowing down the pin and pin connection relationship.

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