JP2534714B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which logic blocks are connected by multilayer wiring.

[Conventional device]

As a conventional technique for connecting between logic blocks in a semiconductor device, for example, a technique described in Japanese Patent Laid-Open No. 61-232634 is known. In this type of conventional technology, through holes are used for wiring between logic blocks, for example, from the first wiring layer to the third wiring layer, which directly conducts electricity without interposing an intermediate wiring layer. A conventional through hole for this kind of wiring will be described below with reference to the drawings.

5 (a) and 5 (b) are cross-sectional views of through holes connecting adjacent wiring layers, and FIGS. 6 (a), 6 (b) and 7
The figure is a cross-sectional view of a through hole connecting between the first wiring layer and the third wiring layer. 5 to 7, 11 is a substrate, 12 is a first wiring layer wiring, 13 is an interlayer insulating film, 14 is a second wiring layer wiring, and 17 is a third wiring layer wiring.

When connecting the wirings of adjacent wiring layers, for example, the wirings of the first wiring layer and the second wiring layer, the through holes are
As shown in FIG. 2B, the first provided on the substrate 11
A hole is formed in the interlayer insulating film 13 on the wiring layer wiring 12, and a metal such as aluminum is vapor-deposited on the second wiring layer including the hole. By vapor deposition of this metal, as shown in FIG. 5A, the second wiring layer wiring 14 is formed, and the second wiring layer wiring 14 and the first wiring layer wiring 12 are connected through the through holes. Will be done. Almost all of the metal particles are deposited in the direction perpendicular to the substrate 11 in the vapor deposition of the metal, and the amount of the metal particles deposited in the oblique direction is generally small. However, the hole for a through hole that connects adjacent wiring layers has a relatively shallow depth,
The inclination of the diagonal line 16 between the bottom surface and the top surface of the hole is relatively gentle as shown in FIG. 5 (b), and metal is easily deposited on the side surface of the hole even if the amount of metal particles obliquely driven is small. Therefore, the second wiring layer wiring 14 formed by this metal vapor deposition
As shown in FIG. 5 (a), the wire is securely connected to the first wiring layer wiring 12 through the through hole without causing a disconnection at the step 15 at the top of the hole for the through hole.

FIGS. 6 (a) and 6 (b) show the case where the first wiring layer wiring 12 and the third wiring layer wiring 17 are connected by the same through hole as described above. In this case, as shown in FIG. 6 (b), the hole for the through hole passes through the second wiring layer 14 'and the two interlayer insulating films 13, so that the depth of the hole is different from that of the adjacent wiring. It is considerably deeper than the holes for through holes that connect the layers to each other. Therefore, the inclination 19 of the diagonal line between the bottom surface and the top surface of the hole becomes large, and the amount of metal deposited on the side surface of the hole becomes very small. Therefore, the connection between the third wiring layer wiring 17 formed in the third wiring layer and the first wiring layer wiring 12 is the sixth wiring layer.
As shown in FIG. 3A, it is performed through a thin metal vapor deposition film on the inner wall of the through hole.
A disconnection is likely to occur at the step portion 18 of the insulating layer 13 on 4 '.

A method of increasing the diameter of the through-hole as a method for surely connecting the wiring layers by forming a metal vapor-deposited film with a sufficient thickness on the side wall even if the depth of the through-hole is increased. There is. FIG. 7 shows a cross section of a through hole that connects the first wiring layer wiring 12 and the third wiring layer wiring 17 by enlarging the hole diameter for the through hole. If it is made large, the wiring layers can be surely connected to each other even by the deep through holes.

[Problems to be solved by the invention]

In the above-mentioned conventional technique, a through hole for directly connecting wiring layers separated by another wiring layer without interposing a wiring layer between the first wiring layer and the third wiring layer is provided. It is necessary to make the diameter of the hole larger than that of the through hole which connects the adjacent wiring layers. Therefore, the wiring pitch must be increased, which causes a problem that the integration degree of the semiconductor device is reduced. It was

That is, the connection between the logic blocks is made by an automatic wiring program implemented in an electronic computer, and is defined in advance so that different signals do not short-circuit when different signals are wired in parallel in the same wiring layer. It is common to perform wiring and connection on the designed wiring grid. However, if the diameter of the through hole is large, a short circuit may occur between wirings. Therefore, it is necessary to define the wiring grid described above with a coarse grid with a widened wiring interval. There are cases where the degree of integration is reduced. For example, in the master slice type semiconductor device, since the terminal position of the logic block inside the master slice type semiconductor device is predetermined on the base chip, as shown in FIG. It is possible to directly connect the first wiring layer and the third wiring layer by using a wiring grid in which the intervals 33 between the wirings 31 in the third wiring layer are made rough and the through holes 32 having a large hole diameter are used. In this case, the degree of integration of the semiconductor device is not so lowered.

However, in a semiconductor device other than the master slice type described above, usually, as shown in FIG. 8B, through holes 34 having a small hole diameter that connect adjacent wiring layers to each other are used, and the wirings 31 are connected to each other. While the space 35 can be formed by a narrow wiring grid, in order to directly connect the first wiring layer and the third wiring layer, in the same way as the mutual space 33 between the wirings 31 shown in FIG. However, the wiring grid must be roughened, and the degree of integration of the semiconductor device is greatly reduced.

An object of the present invention is to solve the above-mentioned problems of the prior art, and to enable multilayer wiring using only through holes with small hole diameters that connect adjacent wiring layers to each other, without lowering the degree of integration. It is an object of the present invention to provide a semiconductor device capable of connecting between logic blocks.

[Means for solving problems]

According to the present invention, the object is to provide a logic circuit block,
In a semiconductor device including at least three wiring layers including a lower wiring layer, an intermediate wiring layer, and an upper wiring layer, a plurality of terminals of logical blocks connecting the logical blocks to each other are provided in the intermediate wiring layer, Interconnection between the plurality of terminals that connect the logic blocks to each other is performed by connection by the intermediate wiring layer and the lower wiring layer and connection by the intermediate wiring layer and the upper wiring layer. Wherein the connection by the intermediate wiring layer and the lower wiring layer includes through-hole connection between the intermediate wiring layer and the lower wiring layer, the connection by the intermediate wiring layer and the upper wiring layer, This is achieved by including a through hole connection between the intermediate wiring layer and the upper wiring layer.

[Operation] By providing the above-mentioned configuration, it becomes possible to wire the inter-terminal wiring of the logic block through the through hole with a small hole diameter and a shallow hole depth that connects the adjacent wiring layers. The degree of freedom in selecting the wiring layer can be increased. Further, since the terminals can be connected only by the through holes having the small hole diameter, it is not necessary to set the wiring grid roughly, and the integration degree of the semiconductor device is not deteriorated.

〔Example〕

Hereinafter, an embodiment of a semiconductor device according to the present invention will be described in detail with reference to the drawings.

1 is a sectional view of a semiconductor device at a terminal position of a logic block showing an embodiment of the present invention, FIG. 2 is a view showing an example of a logic block, and FIGS. 3 (a) and 3 (b) are the present invention. FIG. 3 is a plan view of one embodiment and a perspective view showing a state of wiring on the first wiring layer to the third wiring layer. 1 to 3, 1 is a first wiring layer, 2 is a second wiring layer, 3 is a third wiring layer, and 4 is a first wiring layer.
Wiring layer wiring, 5 is the second wiring layer wiring, 6 is the third wiring layer wiring, 7 and 22 are logic block terminals, 8 is a through hole between the first wiring layer 1 and the second wiring layer, and 9 is the third wiring. Through hole between the layer and the second wiring layer, 20 is a logic block, 21 is a diffusion layer, 23 is a through hole between adjacent wiring layers, 24 is a polysilicon layer, 25 is a metal wiring between elements, 26 is a power supply wiring, 27 Is GN
It is D wiring.

The embodiment of the present invention shown in FIG. 1 is an example in which the entire semiconductor device is composed of three wiring layers. The element 7 of the logic block in the semiconductor device is provided in the second wiring layer 2. There is. Wiring between the logic blocks using the terminals 7 can be performed by the second wiring layer wiring 5 without using another wiring layer, and between the first wiring layer 1 and the second wiring layer 2. Using the through hole 8 of the first wiring layer wiring 4
Alternatively, the third wiring layer wiring 6 can be used by using the through hole 9 between the third wiring layer 3 and the second wiring layer 2.

FIGS. 3 (a) and 3 (b) are plan views and a perspective view of each wiring layer showing such wiring, and the terminals of the logic block 20 in the semiconductor device including a plurality of logic blocks 20 are shown. The connections between the logic blocks according to 7 are shown. The part indicated by X in FIG. 3 (a) is the second part.
A through hole 9 provided between the wiring layer 2 and the third wiring layer 3, The mark indicates that it is provided at the position of the terminal 7. Further, a portion indicated by a triangle is a through hole 8 provided between the second wiring layer 2 and the first wiring layer 1, The mark indicates that it is provided at the position of the terminal 7. As can be understood from FIGS. 1 and 3 (a) and (b), the connection between the logic blocks according to this embodiment is a through hole for directly connecting the first wiring layer and the third wiring layer. Without using the through hole 8 connecting the first wiring layer 1 and the second wiring layer 2 and the through hole 9 connecting the second wiring layer 2 and the third wiring layer 3,
This can be done through the first wiring layer wiring 4 shown by the solid line, the second wiring layer wiring 5 shown by the dotted line, and the third wiring layer wiring 6 shown by the dashed line. Therefore, in the above-described embodiment, the through hole used can be formed with a small hole diameter,
There is no need to increase the grid spacing of the wiring grid, and the degree of integration of the semiconductor device is not reduced.

FIG. 2 shows an example of the configuration of the logic block 20. The logic block 20 is, for example, as shown in FIG.
21, polysilicon layer 24, inter-element metal wiring 25, power supply wiring 2
6. The GND wiring 27 and the GND wiring 27 are interconnected by the contact portions 28 and 29 to form a logic circuit including elements such as transistors. Each terminal 22 of logic block 20
Corresponds to the above-mentioned terminal 7, is placed on the second wiring layer 2, and is provided with a through hole for connecting to an adjacent wiring layer at the position of the terminal, if necessary. In this example, similarly, the inter-element metal wiring 25 and the power supply wiring 27 are all placed on the second wiring layer 2. This logical block is
The present invention only shows one example of the logic block to which the present invention is applied, and in the case of this example, the present invention provides a logic block having any type and function as long as its terminal is in the second wiring layer. Can also be applied. Further, the terminal 22 does not need to be arranged only around the logic block, and may be arranged inside the logic block.

In the above-described embodiment of the present invention, in a semiconductor device including at least three wiring layers, a plurality of terminals for logic blocks are formed in an intermediate wiring layer to connect the logic blocks to each other. The interconnection between the terminals is characterized by using a first connection by an intermediate wiring layer and a lower wiring layer and a second connection by an intermediate wiring layer and an upper wiring layer. is there.

As a result, the above-described embodiment can increase the degree of freedom in the interconnection of the signal lines between the plurality of terminals that connect the logic blocks to each other, and the signal line interconnection area that connects the logic blocks to each other can be increased. The semiconductor chip area can be remarkably reduced, and the remarkable action and effect that the integration density of the semiconductor device can be improved can be achieved.

Although the embodiment of the present invention described above is a case where the present invention is applied to a semiconductor device having three wiring layers, the present invention can also be applied to a semiconductor device having more wiring layers. In this case, the terminals of each block in the semiconductor device are the first wiring layer which is the lowermost layer and the nth wiring layer which is the uppermost layer.
It may be optionally provided in one or a plurality of intermediate layers excluding the wiring layer.

FIG. 4 is a sectional view showing another embodiment of the present invention. In this embodiment, there are five wiring layers, that is, a first wiring layer to a fifth wiring layer. In FIG. 4, 41 is a fourth wiring layer and 42 is a fifth wiring layer.
Wiring layer, 43 is a through hole of the third wiring layer and the fourth wiring layer,
Reference numeral 44 is a through hole between the fourth wiring layer and the fifth wiring layer, 45 is a fourth wiring layer wiring, 46 is a fifth wiring layer wiring, and other reference numerals are the same as those in FIG.

In the embodiment shown in FIG. 4, the semiconductor device is configured to have five wiring layers, and the terminals 7 of the logic block 20 inside the semiconductor device are any wiring layers of the second wiring layer 2 to the fourth wiring layer 41. It is arranged and configured. The terminals 7 of one logic block 20 do not all need to be provided in the same wiring layer.
The logic block 20 shown in the center of the figure has its terminal positions distributed over the second wiring layer 2 and the third wiring layer 3. Then, the connection between the logic blocks by the terminal 7 is made by connecting the wiring of the wiring layer including the terminal 7 or the through hole between the wiring layer and the wiring layer adjacent to the wiring layer and the wiring layer adjacent to the wiring layer. Through wiring. By doing so, even in a semiconductor device having a multi-layered wiring layer of three or more layers, it is possible to connect the logic blocks to each other only by using the through holes having the small hole diameters that connect the adjacent wiring layers. Therefore, the degree of integration of the semiconductor device is not reduced.

〔The invention's effect〕

As described above, according to the present invention, it is possible to perform multilayer wiring using only through holes having a small hole diameter that connect adjacent wiring layers to each other, and to provide a semiconductor device that does not reduce the degree of integration. be able to.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view at a terminal position of a logic block of a semiconductor device showing an embodiment of the present invention, FIG. 2 is a view showing an example of the logic block, and FIG. 3 (a). , (B) is a plan view of an embodiment of the present invention and a perspective view showing the state of wiring on the first to third wiring layers, and FIG. 4 is a sectional view showing another embodiment of the present invention. 5 (a) and 5 (b) are cross-sectional views of through holes connecting adjacent wiring layers, and FIGS. 6 (a), 6 (b) and 7 show a first wiring layer and a third wiring layer. FIGS. 8A and 8B are cross-sectional views of the through holes connecting between the through holes, and FIGS. 1 ... First wiring layer, 2 ... Second wiring layer, 3 ... Third wiring layer, 4, 12, 31 ... First wiring layer wiring, 5, 14 ... Second wiring layer wiring, 6, 17 ... Third wiring layer wiring, 7, 22 ... Logic block terminal, 8 ... Through hole between first wiring layer 1 and second wiring layer, 9 ... Through between second wiring layer and third wiring layer Hole, 11 ... Substrate, 13 ... Interlayer insulation film, 20 ... Logic block, 21 ... Diffusion layer, 23 ... Through hole between adjacent wiring layers, 24 ... Polysilicon, 25 ... Inter-element metal Wiring, 26 ... Power supply wiring, 27 ... GND wiring, 32 ... Through hole between first wiring layer and third wiring layer, 33, 35 ... Wiring space, 34 ... Adjacent wiring layer through hole, 40 ... First wiring layer terminal, 41 ... Fourth wiring layer, 42 ... Fifth wiring layer, 43 ...
Through hole between the third wiring layer and the fourth wiring layer, 44 ... Fourth
Through holes between the wiring layer and the fifth wiring layer, 45 ... fourth wiring layer wiring, 46 ... fifth wiring layer wiring.

Claims (1)

(57) [Claims] 1. A semiconductor device comprising a logic circuit block and at least three or more wiring layers of a lower wiring layer, an intermediate wiring layer and an upper wiring layer, wherein a plurality of logical blocks connecting the logical blocks to each other are provided. A terminal is provided in the intermediate wiring layer, and interconnections between the plurality of terminals that connect the logic blocks to each other are made by the intermediate wiring layer and the lower wiring layer, and the intermediate wiring layer and the intermediate wiring layer. The connection by the upper wiring layer, the connection by the intermediate wiring layer and the lower wiring layer,
A through hole between the intermediate wiring layer and the lower wiring layer, wherein the connection by the intermediate wiring layer and the upper wiring layer is a through hole between the intermediate wiring layer and the upper wiring layer. A semiconductor device including a connection.