JP2901311B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit which is used in a semiconductor integrated circuit, and more particularly to an improved semiconductor integrated circuit which realizes a partial function of a chip.

〔Overview〕

The present invention provides a semiconductor integrated circuit having a plurality of circuit blocks formed on a semiconductor chip, wherein a through hole is provided in the circuit block at a position connecting the internal circuit of the own circuit block to another circuit block. This is to reduce the size of the chip.

[Conventional technology]

One of the mainstream designs of LSIs (large-scale integrated circuits) in recent years is a cell-based design method. This method will be described with reference to the chip layout diagram of FIG. A partial circuit block (hereinafter, referred to as a cell) 11 that realizes a part of the entire circuit function is designed in advance. And this cell
The contact between the cell outer wiring of the cell internal wiring connecting the cell 11 and the outside of the cell is referred to as a cell terminal 14. After arranging the cells 12 and 13 necessary for forming the entire circuit on the chip 10, the cell terminals
A necessary inter-cell wiring 16 is provided between 14 and 15.

Regardless of whether a conventional cell is realized by a manual method or a computer, the layer of the cell terminal 14 (corresponding to the mask layer) is limited to one of the possible layers. For example, in the case of a two-layer wiring, the layer of the cell terminal 14 is limited to either the first wiring layer or the second wiring layer.

By the way, in order to perform the inter-cell wiring 16 most efficiently in order to minimize the chip size, it is preferable that the first layer be wired in the horizontal direction and the second layer be wired in the vertical direction, for example, over the entire surface of the chip. Have been done. In particular, the effect is remarkable when performing automatic design by a computer. Therefore, as shown in FIG. 4A, the conventional cell design is such that the cell terminals 24 placed on the upper and lower sides of the cell 21 are the second layer, and the cell terminals 25 placed on the left and right sides are the first layer. Has been done.

However, in many cases, rotating the direction of the cell by 90 degrees at the time of chip design can significantly reduce the chip size. In this case, as shown in FIG.
It is necessary to draw out the wirings 26a and 27a from the positions of and 25, and install through holes 35 and 36, respectively, and connect with the second layer wiring 32 and the first layer wiring 31 through the through holes 34 and 33, respectively. The area required for wiring is increased, and as a result, the chip area is increased.

[Problems to be solved by the invention]

In the above-described conventional cell design method for a semiconductor integrated circuit, since the terminal layer of the cell is limited to only one layer, there is a disadvantage that the chip size is increased rather than rotating the cell to reduce the chip size. .

The object of the present invention is to eliminate the disadvantages mentioned above,
It is an object of the present invention to provide a semiconductor integrated circuit which does not require an extra area for wiring even if cells are arranged in an arbitrary direction and can reduce a chip size.

[Means for solving the problem]

In a semiconductor integrated circuit having a plurality of circuit blocks formed on a semiconductor chip and multilayer wiring, the circuit block can be connected to any wiring layer at a terminal connecting the own circuit block and another circuit block. Having a through hole, one of the multilayer wirings has a through hole connectable to any wiring layer at a position facing the terminal, and the terminal and the wiring are respectively The semiconductor device is characterized by being connected by a wiring of a wiring layer different from a wiring layer of a wiring traversing between the terminal and the wiring via a through hole.

[Action]

Since the cell is provided with a through hole at a connection position with another cell, it is possible to connect to a desired layer wiring through the through hole.

This eliminates the need for extra through-holes and wiring for it, and does not require an increase in cell area even if cells are arranged in any direction, resulting in a smaller chip.

Further, by providing through holes at positions of desired layer wirings facing the through holes of the cells, the wiring can be minimized, and the chip can be further downsized.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a layout diagram of a chip showing a main part of a first embodiment of the present invention, in which one cell is taken out and shown.

The cell 1 according to the first embodiment has through-holes 4 and 5 provided at positions on the outer periphery of the cell connecting the cell internal circuit 2 and other cells, which is a feature of the present invention. The through holes 4 and 5 correspond to the cell internal wiring 3.
Is connected to the cell internal circuit 2. Here, the positions of the through holes 4 and 5 are determined as intersections between the cell internal wiring 3 and the outer periphery of the cell.

FIGS. 2 (a) and 2 (b) are chip layout diagrams showing main parts of a second embodiment of the present invention, in which wiring is actually performed using cells having the configuration of the first embodiment. FIG. 2 (a) shows an example in which the long side of the cell is arranged parallel to the first layer wiring, and FIG. 2 (b) shows the case where the long side of the cell is aligned with the second layer wiring. The case where they are arranged in parallel is shown.

In FIG. 2A, the through hole 4 of the cell 1 is shown.
Is connected to the through hole 33 provided on the first layer wiring 31 facing the through hole 4 by the wiring 6, and the through hole 5 is provided on the second layer wiring 32 facing the through hole 5. Connected to the through hole 34 provided.

Cell 1 is moved clockwise from the designed position in FIG. 2 (a).
In the case of FIG. 2B rotated by 90 degrees, the through hole 4 of the cell 1 is connected to the through hole 34a provided on the second layer wiring 32 by the wiring 6a, facing the through hole 4,
The through-hole 5 is connected to the through-hole 33a provided in the first wiring 31 opposite to the through-hole 5 by a wiring 7a.

2 (a) and 2 (b), the feature of the present invention is that, in addition to the provision of the through holes 4 and 5 in the cell 1, the first layer wiring 31 facing the through holes 4 and 5 and the Through holes 33, 33a, 34 on double layer wiring 32
And 34a.

According to the second embodiment, the through-holes 4 and 5 on the cell 1 can be arbitrarily treated as terminals of an optimum layer depending on the arrangement direction.

It is easy to solve the problem that the dimensions of the cell itself are not increased by providing through holes at the terminal positions of the cell, since there are generally many empty areas between the cell internal circuit portion and the cell outer shape.

Further, in the above description, although the case of two layers is taken as the multilayer wiring, it is similarly applied to the case of three or more layers.

〔The invention's effect〕

As described above, according to the present invention, by providing a through hole at a terminal position of a cell, even if the cell is arranged in an arbitrary direction, it is possible to prevent an unnecessary increase in a wiring area and to reduce the size of a chip. There is.

[Brief description of the drawings]

FIG. 1 is a layout diagram of a chip showing a main part of a first embodiment of the present invention. FIGS. 2 (a) and 2 (b) are chip layout diagrams showing main parts of a second embodiment of the present invention. FIG. 3 is a layout diagram showing an example of a chip based on the cell-based design method. 4 (a) and 4 (b) are layout diagrams of a chip showing main parts of a conventional example. 1, 11, 12, 13, 21 ... cell 2, ... cell internal circuit, 3
.... Cell internal wiring, 4, 5, 33, 33a, 34, 34a, 35, 36
…… Through hole, 6, 6a, 7, 7a, 26, 26a, 27, 27a
... wiring, 10 ... chip, 14, 15, 24, 25 ... cell terminals, 16 ... inter-cell wiring, 31 ... first layer wiring, 32 ... second layer wiring.

Claims (1)

(57) [Claims] 1. A semiconductor integrated circuit comprising a plurality of circuit blocks formed on a semiconductor chip and a multi-layer wiring, wherein the circuit block has a wiring layer connected to a terminal connecting its own circuit block and another circuit block. The terminal has a through hole that can be connected to any of the wiring layers at a position facing the terminal. The semiconductor integrated circuit is connected to each other by a wiring of a wiring layer different from a wiring layer of a wiring traversing the terminal and the wiring via the through hole.