JP2536503B2 - Data signal processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial Field B Outline of the Invention C Prior Art (Figs. 7 and 8) D Problems to be Solved by the Invention (Figs. 9 and 10) E Means for Solving Problems (Figs. 1, 2 and 5
Fig., Fig. 6) F action (Fig. 1, Fig. 2, Fig. 5, Fig. 6) G embodiment (G1) Configuration of the embodiment (Fig. 1, Fig. 2, Fig. 4) (G2 ) Phase correction principle (FIG. 3) (G3) Operation of the embodiment (FIGS. 2, 5, and 6) (G4) Other embodiment H Effect of the invention A Industrial field The present invention relates to a data signal processing device, and is particularly suitable for application when a data signal modulated by a biphasic mark method is reproduced from a magnetic recording magnetic tape.

B. Summary of the Invention The present invention provides a data signal processing device for reproducing a biphasic mark type data signal coming through a transmission system, by correcting the phase around the transmission system according to the bit error rate of the data signal. The bit error rate of the demodulated data signal can be reliably suppressed to the minimum value.

C Conventional Technology As a data signal processing device using a data signal modulated by the biphasic mark system, there is, for example, an 8 mm video system video tape recorder (VTR).

In this 8 mm video VTR, the audio signal is PCM coded, time-axis compressed, FM-modulated by the biphasic mark modulation method, and recorded on the audio track formed by connecting to the video track. Has been done.

In the biphasic mark type FM modulation, for example, as shown in FIG. 7 (A), the frequency signals S ₁ and S ₂ which are sine waves having a ratio of frequencies f ₁ and f ₂ of 1: ₂ are set to 0 Data is recorded on the magnetic tape as digital data while maintaining the phase relationship such that the cross points match. For example, when audio data is a logic "0" records the frequency signals S ₁ a low frequency f ₁ = 2.9 [MHz] on the magnetic tape, also when audio data is a logic "1", a high frequency f ₂ = 5.8 〔M
Hz] frequency signal S ₂ is recorded.

Thus, when the audio data recorded on the audio track on the magnetic tape is reproduced, FIG.
, The picked-up frequency signal S ₁ or S ₂
0 cross point is detected and, for example, PLL (phase locked lo
In the sampling pulse oscillation circuit op) configuration, lower than the frequency signals S ₁ of frequency f ₁ maintaining the 45 ° phase intervals, or to keep the 90 ° phase intervals with respect to the frequency signal S ₂ of frequency f ₂ Pulse output PLL ₀ oscillates.

Of the pulse output PLL ₀ , the frequency signal S ₁ has 45 °, 13
5 °, 225 °, sample the signal level LV ₁ frequency signals S ₁ using a 315 ° position produce sampling pulses pulse P _S (FIG. 7 (C), a logic "0" level as the read data To use.

Of the pulse output PLL ₀ , the frequency signal S ₂ of 90 °, 27
0 pulses occurring in ° phase samples the signal level LV ₂ of the frequency signal S ₂ is used as a sampling pulse P _S, used as a logic "1" level of the reproduced data.

Actually, in the 8 mm video type VTR, in the recording mode, a recording signal containing audio data as shown in FIG. 7A is recorded on the magnetic tape. The recording information thus recorded on the magnetic tape 1 is picked up in the magnetic head 2 as shown in FIG. 8, and after the peaking correction of the high frequency signal component of the video signal in the reproduced signal in the intermediate tuning circuit 3, The video signal VD is applied to the video signal processing circuit 4, and the audio data
AD is applied to the equalizer circuit 6 of the audio signal processing circuit 5.

Theoretically, if the ratio of the amplitude of the frequency signal S ₂ to the frequency signal S ₁ is about −6 [dB], the level difference between the signal levels LV ₁ and LV ₂ when the sampling pulse P _S is generated is determined. Therefore, it is considered that the data can be reproduced with a sufficiently low error rate.

D. Problems to be solved by the invention However, in practice, the frequency characteristics of the transmission system from the magnetic tape 1 to the intermediate tuning circuit 3 often differ depending on the model of the VTR, and especially the type of the magnetic tape 1 as a recording medium. If they are different, the phase around each frequency component included in the picked up audio data AD is different from each other, so that there is a problem that the conventional equalizer circuit 6 cannot perform equalization.

As an equalizer circuit that solves this problem, Japanese Patent Application No.
No. 241594 proposes a configuration in which it is determined whether the magnetic tape is a coating type magnetic tape or a vapor deposition type magnetic tape, and the characteristic of the equalizer circuit is changed and controlled accordingly. There is.

According to this, ideally, around the phase of the transmission system from the magnetic tape 1 to the intermediate tuning circuit 3, the phase of the frequency signals S ₁ and S ₂ with respect to the frequency f is a straight line K as shown in FIG. It is conceivable that the so-called phase around the above has a linear phase characteristic.

However, when a coated magnetic tape or a vapor-deposited magnetic tape is used, the curve K in FIG. 10 is caused by the unique physical characteristics of the tape itself, mainly the phase characteristics.
_As shown by _MP and K _ME , in the case of the coated magnetic tape, the phases of the frequency signals S ₁ and S ₂ tend to shift on the curve K _MP where the phase shift amount increases by, for example, + 20 °.
On the other hand, the vapor-deposited magnetic tape tends to have a small phase shift amount of, for example, about −5 ° to −10 ° as shown by the curve K _ME .

In this way, when the phase of the transmission system is phase-shifted, the value of θ ₀ around the phase with respect to the frequency f changes, so as shown in FIG. 9, the phase of the 0 cross point of the frequency signals S ₁ and S ₂ is changed. If the deviation occurs, there is a problem that the bit error rate of the demodulated data signal increases because the value of the sampling data changes.

The present invention has been made in consideration of the above points, and the equalizer output ADX obtained at the output end of the equalizer circuit 6 is
As described above with reference to FIG. 10, when the phase characteristic deviates from the ideal curve K due to the phase around the transmission system that transmits the data signal, the phase characteristic is set so as to minimize the bit error rate. It is intended to propose a data signal processing device capable of improving the bit error rate of the data signal obtained at the output end of the transmission system by correcting the above.

E Means for Solving the Problems In order to solve the above problems, in the present invention, a PCM audio signal reproducing means (1, 2 ,, for reproducing a PCM audio signal recorded on a coating type magnetic tape or a vapor deposition type magnetic tape). 3, 6) and a phase shift circuit 11 for phase-shifting the phase of the reproduced PCM audio signal ADX obtained from the PCM audio signal reproducing means (1, 2, 3, 6) according to the phase shift control signal PSH, PCM demodulation circuit 12 that demodulates PCM audio data AD _PCM from phase shift reproduction PCM audio signal PSO obtained from shift circuit 11, and PCM
_PCM detected by the demodulation circuit 12 The error detection circuit 13 for detecting the bit error rate of the audio data AD _PCM , and the _PCM detected by the error detection circuit 13 based on the bit error rate detection signal ER obtained from the error detection circuit 13. By forming the phase shift control signal PSH so as to minimize the bit error rate of the audio data AD _PCM , the phase shift generated in the reproduction PCM audio signal ADX according to the phase characteristics of the coating type magnetic tape or the vapor deposition type magnetic tape 1 And a phase correction circuit 14 for correcting the above in the phase shift circuit 11.

F function When the reproduced PCM audio signal obtained from the PCM audio signal reproducing means (1, 2, 3, 6) is demodulated in the demodulation circuit 12 under the influence of the phase characteristics of the coating type magnetic tape or the vapor deposition type magnetic tape. The bit error rate increases depending on the phase around which the data signal is received from the coating type magnetic tape or the vapor deposition type magnetic tape.

Therefore, the bit error rate is detected by the error detection circuit 13, and the amount of phase shift of the data signal passing through the phase shift circuit 11 is controlled by controlling the amount of phase shift of the phase shift circuit 11 based on the detection result. It is possible to control so that the bit error rate detected by the error detection circuit 13 is minimized.

Thus, even when the coated magnetic tape or the vapor-deposited magnetic tape as a recording medium having various phases is compatible, the bit of the data signal demodulated according to the phase characteristics of each coated magnetic tape or the vapor-deposited magnetic tape is used. The error rate can be reliably suppressed to a minimum.

G Embodiment One embodiment of the present invention will be described in detail below with reference to the drawings.

(G1) Configuration of the embodiment In FIG. 1 in which parts corresponding to those in FIG. 8 are designated by the same reference numerals, a reproduction PCM obtained at the output end of the equalizer circuit 6
The equalizer output ADX as an audio signal is phase-shifted in the phase shift circuit 11, and the phase-shifted output is output.
The PSO is given to the PCM demodulation circuit 12. The PCM demodulation circuit 12 demodulates the time-axis-compressed PCM audio data AD _PCM modulated by the biphasic mark modulation method and sends it to the error detection circuit 13.

The error detection circuit 13 detects the bit error rate based on the error detection CRCC code data attached to the PCM audio data compressed between the axes at the time of reproduction, and outputs the bit error rate detection signal ER to the phase correction circuit 14. Send out.

The phase correction circuit 14 is composed of a computer, and outputs a phase shift control signal PSH to the phase shift circuit 11 by executing a bit error rate improvement processing program as shown in FIG. Corrects and controls the phase shift amount for ADX.

In the case of this embodiment, as shown in FIG. 4, the phase shift circuit 11 comprises a series circuit of a variable capacitance diode C2, a coil L1 and a capacitor C3, and a variable resistor R5 between the transistors TP1 and TR2. The phase shift control signal PSH obtained from the phase correction circuit 14 (FIG. 1) is applied to the variable capacitance diode C2 through the circuit 11A.

Thus, the phase shift circuit 11 is provided with the phase shift control signal PS
By changing and controlling the capacitance value of the variable capacitance diode C2 by H, after shifting the phase of the equalizer output ADX input to the transistor TR1, the transistor TR2
The phase shift output SO as a phase shift reproduction PCM audio signal is sent to the PCM demodulation circuit 12 (FIG. 1) from the output terminal of the.

In this way, shifting the phase of the equalizer output ADX by means of the variable capacitance diode C2 is effective for the transmission system including the magnetic tape 1 currently used, as shown in FIG. Phase around θ _{0 in} FIG. 3
Is equivalent to changing the value of, and thus the value of the bit error rate E of the phase shift output PSO obtained at the output end of the phase shift circuit 11 is changed to the bit error rate curves W _MP , W _ME1 , W
Minimum value MIN _MP of _ME2, can be corrected to the MIN _ME1, MIN _ME2.

(G2) Phase Correction Principle As described above with reference to FIG. 10, the phase rotation θ ₀ from the magnetic tape 1 to the equalizer circuit 6 changes so as to ride on the ideal curve K with respect to the change of the frequency f. When it has such a phase characteristic, the equalizer output ADX obtained from the equalizer circuit 6 can reproduce PCM audio data with a minimum bit error rate.

However, when a coated magnetic tape is actually used as the magnetic tape 1, the PCM audio data is reproduced from the equalizer output ADX with the minimum bit error rate as shown by the curve K _{MP in} FIG. Around possible phase θ
₀ = θ _MP tends to increase. This means that as shown by the bit error rate curve W _MP in FIG. 3, the bit error rate becomes minimum at the phase around θ ₀ = θ _MP , and the phase around the transmission system increases around this phase around θ _MP. Or, if the bit error rate decreases, the bit error rate tends to increase accordingly.

Similarly, when a vapor-deposited magnetic tape is used as the magnetic tape 1, the phase rotation θ which minimizes the bit error rate is obtained.
_ME1 and θ _ME2 appear around the phase at a value lower than θ ₀ = θ _MP ,
As a result, if the phase around the transmission system increases or decreases around this value θ _ME1 or θ _ME2 , the bit error rate increases.

Actually, as the vapor-deposited magnetic tape, as shown by the bit error rate curves W _ME1 and W _ME2 in FIG. 3, there are a plurality of types of magnetic tapes having θ _ME1 and W _ME2 around the phase where the bit error rate is minimized. It has been confirmed.

When attempting to demodulate PCM data of multiple types of magnetic tapes that draw different bit error rate curves by using a common transmission system while maintaining compatibility, the phase characteristic of the transmission system is changed to an ideal phase curve K. Phase around θ ₀ =
When set to θ _K , the bit error rate of the equalizer output ADX is E _MP , E _ME1 , E _ME2 depending on the type of magnetic tape used.
, It does not always become the minimum value.

In the present invention, the bit error rate curve W _MP exhibited by the equalizer output ADX according to the type of the magnetic tape 1 used,
Or W _ME1 or W _ME2 , its minimum point MIN _MP , MI
The phase characteristic of the transmission system is controlled so that it has a phase around N _ME1 and MIN _ME2 .

Thus no matter what kind of magnetic tape is used,
Data can be reproduced with the minimum bit error rate.

(G3) Operation of the embodiment The phase correction circuit 14 gives the equalizer output ADX a phase shift amount that provides the minimum bit error rate of the bit error rate curve of the phase shift output PSO.

That is, the phase correction circuit 14 enters the bit error rate improvement processing program from step SP1 in FIG.
In 2, the variable capacitance diode C2 is reset to the initial capacitance value, and thus the correction capacitance value Δ of C2 of the variable capacitance diode Δ
Set C to ΔC = 0.

When the capacitance value of the variable capacitance diode C2 is reset to the initial value in this way, the bit error rate of the phase shift output PSO becomes a value corresponding to the phase shift amount determined by the initial value of the variable capacitance diode C2. As shown in the figure, in the bit error rate curve W _X1 , the error rate E ₀ is in the curve portion that monotonically decreases when the correction capacitance value ΔC increases, or as shown in FIG. Of the curve W _X2 ,
When the correction capacitance value ΔC increases, the error rate E ₀ in the curve portion increases monotonically.

Then, the phase correction circuit 14 shifts to step SP3, detects the bit error rate E ₀ by the bit error rate detection signal ER of the error detection circuit 13 and stores it in the E ₀ register provided in the internal memory, and then the step In SP4, N = 0 is similarly initialized in the N register provided in the internal memory.
This N register is a register that counts the number N of times of correction processing.

Subsequently, the phase correction circuit 14 adds "+1" to the count content of the N register at step SP5, and then, at step SP5.
At SP6, "+1" is added to the count content of the ΔC register.

Here, the ΔC register is a register that counts the correction capacitance value ΔC of the variable capacitance diode C2 of the phase shift circuit 11, and the value is incremented by “+1” each time one correction calculation is completed, and thus the phase shift is performed. The phase shift amount of the circuit 11 increases stepwise in increments of "+1".

Subsequently, in the phase correction circuit 14 step SP7, based on the bit error rate detection signal ER which is sent from the current error detection circuit 13, provided in the internal memory by detecting the current bit error rate E ₁ E ₁ Capture in register.

Thus, the bit error rate at the initial reset of the E ₀ register
A state is obtained in which E ₀ and the bit error rate E ₁ obtained in the error detection circuit 13 as a result of correcting the capacitance value of the variable capacitance diode C2 by one step are obtained, and the phase correction circuit 14
Determines whether the value of the bit error rate E ₁ obtained by the current detection operation is larger than the value of the bit error rate E ₀ obtained by the previous detection operation at the next step SP8.

If a negative result is obtained here, represents the value of the bit error rate E ₁ is less than the value of bit error rate E _0, this means that the equalizer output ADX is, the error rate curve of Figure 5 W _X1
As shown by, a phase shift output having a phase such that the bit error rate E corresponds to a monotonically decreasing waveform portion.
It shows that the PSO has been obtained and has not reached the minimum value yet.

At this time, the phase correction circuit 14 proceeds to step SP9 and transfers the contents of the E ₁ register to the E ₀ register, thus replacing the bit error rate E ₁ detected this time with the previous error rate E ₀ .

When this processing is completed, the phase correction circuit 14
After returning to SP5 and adding "+1" to the count content of the N register, in step SP6 "+1" is added to the ΔC register.
By adding, the correction capacitance value ΔC of the variable capacitance diode C2 of the phase shift circuit 11 is stepwise changed by "+1".

As a result, the bit error rate of the phase shift output PSO can be further modified by one step, and the present bit error rate E ₁ and the previous bit error rate E ₀ are compared in the subsequent step SP8.

If a negative result is obtained here, it means that the current error rate E ₁ is not the minimum value.Therefore, the phase correction circuit 14 again moves to the above-mentioned step SP9 and transfers the contents of the E ₁ register to the E ₀ register. Execute the transfer process.

In the same manner as described below, the phase correction circuit 14 operates in steps SP9-SP5.
The phase shift correction calculation loop of -SP6-SP7-SP8-SP9 is repeated until a positive result is obtained in step SP8.

When a positive result is obtained in step SP8,
This means that it is detected for the first time that the bit error rate E ₁ of the phase shift output PSO obtained by this phase shift correction operation is larger than the bit error rate E ₀ obtained by the previous phase shift correction operation. This means that the bit error rate obtained by the previous phase shift correction operation is
It indicates that E ₀ is the minimum value.

Thus, the phase correction circuit 14 is configured so that, with respect to the magnetic tape 1 currently used, the phase shift of the transmission system from the magnetic tape 1 to the phase shift circuit 11 is minimized by the previous phase shift correction operation so as to minimize the bit error rate. Can be adjusted. Therefore, the phase correction circuit 14 shifts to step SP10 when a positive result is obtained in step SP8,
Phase shift output PS by subtracting "-1" from the C register contents
After returning the phase shift amount of O to the phase shift amount at the time of the previous calculation processing, the process proceeds to the next step SP11.

In this step SP11, the phase correction circuit 14 determines whether the arithmetic processing circuit N is 2 or more. By the way, in the case of FIG. 5, since a positive result is obtained,
The phase correction circuit 14 proceeds to step SP12 and ends the bit error rate improvement processing program.

Thus, in step SP10, the bit error rate E ₀ set by the previous phase shift correction operation is set as the finally obtained minimum error rate E _MIN .

By the way, when the magnetic tape 1 has such a characteristic that the bit error rate when the phase shift circuit 11 is initialized as shown in FIG. 14 is step SP1-S
When P2-SP3-SP4-SP5-SP5-SP6-SP7-SP8 steps are processed, the phase shift amount of the phase shift circuit 11 is corrected by "+1" at step SP6 from the initially set bit error rate E ₀ value. Since the bit error rate E ₁ obtained as a result is larger, the phase correction circuit 14 obtains an affirmative result at step SP8, and accordingly, at step SP10.
After returning the correction amount by "-1" at step SP11
Then, it is determined whether or not N exceeds the number of calculation processes N = 2.

However, at this time, the number N of correction calculations is N = 1, and therefore the phase correction circuit 14 shifts to step SP13 by obtaining a negative result in step SP11.

This step SP13 subtracts "-1" from the contents of the .DELTA.C register, and thus the variable capacitance diode of the phase shift circuit 11 is
The correction capacitance value ΔC of C2 is reduced by “−1”.

Thus, the phase of the phase shift output PSO can correct the phase shift amount by the correction amount of "-1", and in this state, the phase correction circuit 14 is based on the bit error rate detection signal ER obtained from the error detection circuit 13 at present. The bit error rate E ₂ is detected and stored in the E ₂ register provided in the internal memory, and then the process proceeds to the next step SP15.

If a negative result is obtained in step SP15, this means that the previously detected bit error rate E ₀ is not the minimum value.
16 was transferred the contents of transfer connexion E ₂ registers E ₀ register returns to the foregoing step SP13.

Thus, once the correction calculation processing is completed, the phase correction circuit
14 indicates that the correction capacitance value ΔC of the phase shift circuit 11 is corrected by “−1”.

In this state, the phase correction circuit 14 sets the correction capacitance value ΔC of the variable capacitance diode C2 to “−” in step SP13.
1 "amount corresponding erroneous varying, the current in step SP14 after capturing bit error rate E ₂ to E ₂ register, the value of the bit error rate E ₂ is whether the last bit larger error rate E ₀ When the decision is made and a negative result is obtained, the above step
Returning to SP16, the present bit error rate E ₂ is replaced with the previous bit error rate E ₀ and the processing is executed.

In the same manner, the phase correction circuit 14 proceeds to steps SP16-SP13-SP14 until a positive result is obtained at step SP15.
-SP15-SP16 is repeated, and when a positive result is obtained in step SP15, the process moves to step SP17 and Δ
"+1" is added to the contents of the C register and the bit error rate improvement processing program is terminated in step SP12.

The positive result obtained at step SP15 is that this bit error rate E ₂ is the first bit error rate for the first time.
This means switching from E ₀ to the rising direction, which means that the previous bit error rate E ₀ is the minimum value.

Therefore, the phase correction circuit 14 can set the phase shift circuit 11 to the shift amount corresponding to the previous bit error rate E ₀ by returning the shift amount of the phase shift circuit 11 by “−1” in step SP17.

According to the above configuration, the phase obtained in the output terminal of the phase shift circuit 11 is determined by the phase shift amount in the system from the magnetic tape 1 to the magnetic head 2, the intermediate tuning circuit 3, the equalizer circuit 6, and the phase shift circuit 11. The bit error rate generated in the shift output PSO is directly detected by the error detection circuit 13, and the phase shift amount of the phase shift circuit 11 is controlled based on the detection result so that the bit error rate becomes the minimum value. As a result, even when the magnetic tape 1 is compatible with various types having different phase characteristics, the transmission system can be adjusted so as to minimize the bit error rate of reproduced data by following the phase characteristics of the magnetic tape. it can.

(G4) Other Embodiments (1) Although the present invention has been described in the above embodiment as being applied to the reproduction of the PCM audio signal in the video tape recorder of the 8 mm video system, the present invention is not limited to this. Without being limited to this, even when the present invention is applied to the case of reproducing a video data signal in a digital VTR, the same effect as the above case can be obtained.

(2) Also, although the present invention is applied to the case of processing a data signal picked up from a tape, the present invention is not limited to this, and in a transmission system for transmitting a biphasic digital signal through the transmission system, the transfer characteristic of the transmission system on the receiving side. Can be widely applied to correct

H Effect of the Invention As described above, according to the present invention, the bit error rate of PCM audio data is determined based on the phase around which a PCM audio signal is reproduced from a coating type magnetic tape or a vapor deposition type magnetic tape as a recording medium. Focusing on the changing points,
By correcting the phase shift amount of the reproduced PCM audio signal so as to minimize the bit error rate, it is possible to easily realize the data signal processing device capable of suppressing the bit error rate to a much smaller value.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data signal processing device according to the present invention, FIG. 2 is a flow chart showing the bit error rate improvement processing program, and FIG. 3 is a bit error rate depending on the type of magnetic tape. 4 is a characteristic curve diagram showing that the phase shift circuit changes, FIG. 4 is a connection diagram showing a concrete configuration of the phase shift circuit of FIG. 1, and FIGS. 5 and 6 are explanations of the correction operation for obtaining the minimum value. FIG. 7 is a curve diagram provided, FIG. 7 is a signal waveform diagram used to explain the data signal to be processed, FIG. 8 is a block diagram showing a conventional data signal processing device, and FIG. 9 is a phase shift of the frequency signals S ₁ and S ₂ . FIG. 10 is a signal waveform diagram for explaining the problems caused by the above, and FIG. 10 is a characteristic curve diagram showing the relationship between the biphasic mark data signal and the phase periphery. 1 ... Magnetic tape, 2 ... Magnetic head, 3 ... Intermediate tuning circuit, 6 ... Equalizer circuit, 11 ... Phase shift circuit,
12 ... PCM demodulation circuit, 13 ... error detection circuit, 14 ... phase correction circuit.

Claims (1)

(57) [Claims] 1. A PCM audio signal reproducing means for reproducing a PCM audio signal recorded on a coating type magnetic tape or a vapor deposition type magnetic tape, and a phase shift of a phase of a reproduced PCM audio signal obtained from the PCM audio signal reproducing means. A phase shift circuit that shifts the phase according to the control signal, a PCM demodulation circuit that demodulates PCM audio data from the phase shift reproduction PCM audio signal obtained from the above phase shift circuit, and a bit of the PCM audio data obtained from the above PCM demodulation circuit. An error detection circuit for detecting an error rate, and a phase for minimizing the bit error rate of the PCM audio data detected in the error detection circuit based on the bit error rate detection signal obtained from the error detection circuit. By forming the shift control signal,
A data signal processing device, comprising: a phase correction circuit for correcting the phase around the reproduced PCM audio signal in the phase shift circuit according to the phase characteristics of the coating type magnetic tape or the vapor deposition type magnetic tape.