JP2537484B2 - Distribution arbitration circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a device mounted on or formed in a common carrier, and more particularly to a silicon integrated circuit chip formed in or mounted on a silicon wafer.

Background of the Invention The demand for high speed, large capacity memory computers has led to the need for wafer scale integration using one silicon wafer as the carrier for 10, 100 or even 1000 integrated circuits. These integrated circuits are formed in a wafer and are separated from each other by pn junction or insulating layer separation. A conductor formed on or over the top plane of the wafer fulfills the function of interconnecting the circuits. Another similar connection method is to mount an entirely formed integrated circuit on a semiconductor wafer and then interconnect the circuits with conductors.
As an example of how to realize this, IEEE transaction
On Electron Device (IEEE Transaction o
n Electron Devicss), Vol.ED-15, No.9, 1968 9
Mon, Bage 660-663, “Wafer-Chip Assembly for Large-
Scale Integration) ".

In most of these structures, multiple integrated circuits are connected to a common data bus and each is coupled to a common arbitration circuit, which arbitration circuit generally comprises two or more circuits. It determines which circuit should get access if it wants to get access to the data bus, either at the same time or within a given period of time. One problem with the common arbitration circuit is that it has multiple wirings, thus limiting the number of circuits that can be used on a given semiconductor wafer, and also requires a transaction between two chips, which increases speed performance. It has an adverse effect.

Therefore, it is required to achieve the arbitration function required for multiple chips with a common data bus without the wiring and speed constraints found in the prior art.

SUMMARY OF THE INVENTION These constraints apply to the following devices, a plurality of element circuits each connected to a signal conduit path and prioritized for access to the signal conduit path, each priority of one of said element circuits: A circuit comprising a plurality of arbitration conduit paths, each of which has a priority associated therewith, and a clock conduit path for transmitting a clock signal, each of the element circuits having the lowest priority in some cases. Except for the element circuit having the order, one of the plurality of arbitration request circuits is included, and each of the element circuits has a plurality of arbitration decision circuits, except for the element circuit having the highest priority in some cases. Including one of them, each arbitration request circuit has a control terminal and a first and second terminal. A first transmission gate element having a second output terminal, the control terminal being coupled to the clock conduit path via a first coupling means, the first and second output terminals being individually , The part of the element circuit that determines whether or not the terminal circuit desires access to the signal conduit path and, in some cases, the transmission gate element in the element circuit with the lowest priority, the arbitration conduit path Each arbitration decision circuit comprises a binary logic gate or its logical equivalent having at least as many input terminals as the number of higher priority device circuits, and a given one The input terminal of the binary logic gate or its logical equivalent in the arbitration decision circuit of the device circuit. Zorega, connected to one of the higher priority arbitration conduit path,
Alternatively, the arbitration request circuit of the given one element circuit is connected to the second output terminal of the first transmission gate, and each arbitration decision circuit further includes a latch circuit element and a second transmission gate element. The second transmission gate element is coupled to the clock conduit path through the second coupling means which is complementary to the first coupling means, and the control terminal is respectively connected to the binary logic gate or its logical equivalent. And a circuit having first and second output terminals coupled to the input terminals of the object and the latch circuit element.

In a preferred embodiment of the present invention, a semiconductor wafer has a plurality of device circuits formed therein or mounted therein. This device circuit is typically a silicon integrated circuit, which is called a chip. Some of these chips are coupled to a common data bus, and at least two or more chips selectively require access to the data bus to carry signaling information from one chip to another. Each of these chips has a priority for transmitting information to the data bus. The carrier and at least some of the chips are the same material. Each of the chips that require access to the data bus includes an arbitration request circuit and an arbitration decision circuit. The arbitration request circuit allows the chip to transmit information to another chip via the data bus by selectively sending a signal requesting that the chip be granted access to the data bus. To do.

The arbitration decision circuit detects which of the other chips coupled to the data bus requires access to the data bus within any given time period, during which time the chip accesses the data bus. If it has a higher priority than any of the other chips it wants, it will allow that chip to gain access to the data bus. There are multiple arbitration conduits (conductors). Each arbitration request circuit has an output terminal coupled to one of the separate arbitration decision circuits, except possibly the arbitration request circuit having the lowest predetermined priority. Typically, each arbitration circuit
Sometimes it is coupled to several arbitration conductors, except for the chip arbitration decision circuit with the highest predetermined priority.

Providing a separate unique arbitration request circuit and a separate unique arbitration circuit as part of each chip that requires selective access to the common bus allows each chip to be centrally arbitrated. It reduces the wiring complexity for interconnecting the system to eliminate the need for a separate connection to the decision circuit. Therefore,
It can be interconnected in a variety of different configurations regardless of how the chips are coupled to a common circuit and without the speed penalty associated with the need to transact two circuits.

This element circuit (chip) consists of a central processing unit (CPU),
Memory Management Unit (MMU), Mass Acceleration Unit (MAU), Direct Memory Access Controller (DMA)
C), dynamic random access memory (DRA
M), static random access memory (SRA
M), read only memory (ROM), gateway (GTW)
Y), or various other circuits including analog circuits and circuits for transmitting and receiving optical signals.

Detailed Description of Embodiments Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a system comprising a chip 0, a chip 1, ... Chip 7 and a wafer 12 having integrated circuits (chips) designated as chips N and N + 1.
These chips are merely representative of a plurality of chips that are present on or attached to the wafer 12. Wafers are called carriers, and chips are also called integrated circuits, device circuits, or ICs. Chips 0, 1, ... 7 are shown connected to data / address bus 1 and data / address bus 2. The interaction between the chips 0, 1, ... 7 and the data / address bus 2 will be described below. Data / address for use in the invention
The presence of bus 1 is not necessary. Each of the data / address buses is also referred to as a signal connection path. Chips N and N + 1 are shown coupled to data / address bus 2 and data / address bus M. Chips 0, 1, ... 7
Each of them is a separate arbitration request circuit (ARC0, AR
C1, ... ARC7) and a separate arbitration decision circuit (denoted as AC0, AC1, ... AC7). ARC0 is not needed when chip0 has the lowest priority of the eight chips. Chips 0, 1, ... 7 selectively gain access to the data / address bus 2 to send signaling information from one chip to another chip or to some circuit (not shown) coupled to the data / address bus 2. Need that. The ARC and AC normally work together to allow only one of the eight chips to send (transmit) information to the data / address bus 2 at any given time or period. Basically, no other arbitration request circuit or arbitration decision circuit is needed to perform this function. Therefore, there is great flexibility in constructing various chips into a desired structure.

There are seven arbitration lines (conductors), A1, A2 ... A7, which are called arbitration conduits, and ARC1, ARC2 ... ARC7 are connected to A1, A2 ... A7, respectively. ARC0 is not bound to any arbitration conduit pathway. The AC circuits of chips 1 to 7 are A1 and A
2, ... Connected to the A7 line or the reference potential, chip 7 has the highest priority, each successive chip in turn has a lower priority, and chip 0 has the lowest priority. The AC circuit of Chip 7 is not connected to the arbitration line. This is the case during the access request period of the cycle of operation of chips 0 to 7, when chip 7 is requesting access to the data / address bus 2, even in the next appropriate transmission period of the cycle of operation, 7
Even when all of the chips are requesting access,
This means that chip 7 gets access. Chip 0 can gain access at the same time, or only when all seven other chips are not requesting access during a period of the access request period (selected period) of the cycle of operation.

Each of AC0, AC1, ... AC7 has eight terminals 0, 1, 2, 3, 4, 5, 6, and 7, as shown in FIG. AC1
Input terminal 1 of AC2, input terminals 1 and 2 of AC2, input terminal 1 of AC3,
2 and 3 (not shown) AC4 input terminals 1, 2, 3 and 4 (not shown), AC5 input terminals 1, 2, 3, 4 and 5
(Not shown), AC6 input terminals 1, 2, 3, 4, 5 and 6 (not shown) and AC7 input terminals 1, 2, 3, 4,
5, 6, and 7 are coupled to the reference potential Vref. Input terminals 1, 2, 3, 4, 5, 6 and 7 of AC0 are A1
To A7. Input terminals 2 to 7 of AC1 are coupled to A2 to A7, respectively. AC2 input terminals 3 to 7
Are respectively coupled to AC3 to AC7. Input terminals 4 to 7 of AC3 are coupled to A4 to A7, respectively. Input terminals 5 to 7 of AC4 are coupled to A5 to A7, respectively.

The clock line C1 is also called a clock conduit path, but each of ARC0 to ARC7 and inverter circuits I01, I1
1, ... Coupled to the input terminal of I71. The output terminals of I01, I11, ... I71 are coupled to AC0, AC1 ,. The remaining line R is coupled to each of AC0, AC1, ... AC7. The output terminals of ARC0 to ARC7 are
Are coupled to the input terminals of inverters I02, I12, ... I72. I
The output terminals of 02, I12, ... I72 are AC0 and AC, respectively.
1, ... Coupled to AC7 input terminal.

Shown in FIG. 2 is a portion of the system 10 of FIG. 1 showing the ARC1 and AC1 component portions. ARC0 and ARC2 to ARC7
Has basically the same structure as ARC1. AC0 and AC2 to AC
7 has basically the same structure as AC1. ARC1 includes a gate device Q1 shown as a field effect transistor, and a non-inverting driver circuit D1. The gate of Q1 is tied to C1.
The first output terminal of Q1 and the input terminal of D1 are coupled to node 14. The second output terminal of Q1 is coupled to the part of chip 1 which determines whether chip 1 requires access to data / address bus 2. The output terminal of D1 is coupled to A1 and one of the input terminals of inverter I12. AC1 is an 8-input AND with input terminals 0, 1, 2, 3, 4, 5, 6 and 7.
It includes a gate 22, a gate device Q2 shown as a field effect transistor, and a latch circuit 24. The gate of Q2 is coupled to the output terminal or node 16 of inverter circuit I11. I11
The input terminal of is coupled to C1. The output terminal of AND gate 22 is coupled to one of the output terminals of Q2, node 18. The second output terminal of Q2 is coupled to the input terminal or node 20 of latch circuit 24. The output terminal of the latch circuit is chip 2 for data /
Chip 2 that allows you to send information to address bus 2
Is combined with the part of.

The operations of chips 0, 1, 2, 3, 4, 5, 6, and 7 are basically as follows. At the start of the cycle of operation, both the clock signal and the reset signal are high, that is, "1". This sets all output terminals of all latch circuits from AC0 to AC7 to low value, that is, "0". At the beginning of the cycle following the clock (that is, when the clock goes from "0" to "1"), its reset signal changes from "1" to "0", and each of chips 0 to 7 Generates "1" or "0" from the associated ARC circuit. A "1" indicates that the chip producing the "1" does not need to gain access to the data / address bus 2 at this time. A "0" indicates that the chip producing the "0" wants to access the data / address bus 2 at this point. Chips 0 to 7 have the highest priority (ie, if this requires access to the data / address bus 2) for the other seven chips, for purposes of explanation only here. Can get access whether or not they need access), and chip 0 has the lowest priority (that is, if none of the other 7 chips needs access). Can only get access to)
With configuration and connection. The priority decreases with the designated number of chips.

The magnitude and polarity of the reference potential Vref is selected so that it is at the logic "1" level. Chip 7 gets "0" from ARC7
When sent to A7, the seventh input terminal of each of the AND gates AC0 to AC6 receives the "0" input signal, so that the output signals of each AND gate are all "0". In the latter half of this clock cycle (that is, the clock signal becomes “0”), each gate device of AC0 to AC6 (that is, Q2)
Are activated, and the "0" at the output terminals of the seven AND gates becomes the input signal to each of the seven latch circuits. This brings each of these seven latch circuits and the output to the "0" level. This is data for each of chips 0 to 6
The information you want to send to address bus 2 is data /
Do not reach address bus 2. AC7 receives a "1" input signal on AC7's input terminals 1-7 because they are tied to Vref, and ARC7 produces a "0" which is inverted by I72. Therefore, "1" is received on the input terminal 0. Eight "1" input signals to the AND gate of AC7 cause this output terminal to take the "1" level. In the second half of the clock cycle, Q2 of AC7 is activated,
This "1" signal becomes the input to the AC7 latch circuit. This sets the output terminal of the latch circuit to "1", which allows the chip 7 to transfer information to the data / address bus 2.

Assume now that chip 1 wishes to transmit information to the data / address bus 2 in the next cycle of the clock, and at this point all chips with higher priority do not wish to transmit information. To do.
This results in A2 to A7 being "1" and A1 being "0". When A1 goes to "0", this means that one of the inputs to the AND gate of AC0 goes to "0", thus the AND gate of AC0 has a "0" output, and the corresponding latch circuit is also low in clock. When it reaches a value (“0”), it has “0” output, so that it prevents (prevents) chip 0 from gaining access to the data / address bus 2. Since the ARC1 is "1", the input terminals 1 to 7 of the AND gate of AC1 are all "1" like the 0 input terminal. This causes the latch circuit of AC1 to be "1", which in turn causes the output terminal of this latch circuit to be "1". This allows the chip 1 to transfer information to the data / address bus 2. If Chip 1 wants to transmit but also one or more chips with a higher priority than this, Chip 1 may be one of the input terminals 1 to 7 of the AND gate of AC1 or Transmission is not performed because multiple data are "0".

Now suppose that in the next cycle of the clock, chip 0 wants to transfer information to the data / address bus 2 and all other chips do not want it.
All of the input terminals 1 to 7 of the AND gate of AC0 are "1", and the input terminal 0 thereof is also "1". When all eight input terminals of the AND gate of AC0 become "1", the output of the AND gate becomes "1", and the latch circuit associated with this becomes the output level of "1" in the next period of the clock cycle. take. As a result, chip 0 transfers information to data / address bus 2. This is not always necessary because I02 can secure "1" regardless of whether the input terminal 0 is "1" at the output terminal of the AND gate of AC0, and can be omitted in some cases. As a result, Chip 0 will transmit "random data" during all periods when the other chips do not need to transmit. Typically, the information transmitted contains at least one bit indicating that this is valid. If chip 0 transmits without this bit, this information is consequently ignored by all other chips. If I02 is removed, chip 0 will be replaced by other chips
When the access to the address bus 2 is not requested, the access can be secured without making this request. This saves one cycle of movement of Crocs,
Therefore, speed performance is improved.

If chip 0 and another chip simultaneously request transmissions to the data / address bus 2, the other chip becomes AC.
Disable 0 and gain access to data / address bus 2.

When a chip gains access to bus 2, it transmits that information in the first half of the next cycle of the clock, which information is received by all other chips coupled to bus 2. The transmitted information is decoded later in this cycle and is considered the recipient of that information 1
Only one or more chips will receive and decode it. The chip that received the transmitted information is
In the first half of the cycle, it sends back an acknowledgment signal on the ACK line (ACK) or a busy signal on the busy line (BY). When the chip sending the information receives the acknowledgment signal, it does not retransmit the same signal. When it receives a busy signal or no response signal, it subsequently transmits the same information.

The embodiments described herein are intended to illustrate the general principles of the invention. Various changes can be made without inconsistent with the spirit of the present invention. For example, AND of AC0 to AC7
Each of the inputs 1 to 7 to the gate can be programmed or connected to a programmed circuit to couple these input terminals to various combinations of A1 to A7, and the chip priority to the data / address bus. It may be possible to change it before it needs to gain access. ARC0 to ARC7 can also be programmed, or they can be combined as needed by connecting through programmed circuits. In addition, a distributed arbitrator included on all the chips that are on the same wafer and that need to selectively access the data / address bus for multiple other chips coupled to other data / address buses. A decision request circuit and an arbitration decision circuit can also be provided. Further, separate data / address buses can be coupled to each other via gate circuits. Further, the data / address bus may be aluminum, doped polysilicon, or another conductor, or an optical coupling device such as an optical fiber or air. In addition, the wafer and chip are Ga
It may be a Group III-V semiconductor compound such as As or GaAsInP. In addition, some chips can be provided with a bias to a bus so that no information is transmitted on that bus. Further, the number of chips may be basically any number of 2 or more. Further, multi-cycle arbitration can be performed. In addition, other types of gates can be used instead of the AND gate when the input signal to the gate is changed. Furthermore, the wafers shown as carriers can also have circuits (chips) or other elements attached to them which are not identical to each other or of the same material as the carrier. Further, the device circuit may be formed in the wafer 12 as a part thereof. Further, each ARC can be a separate integrated circuit chip and each AC can also be a separate integrated circuit chip. In addition, ARC and AC can be integrated on one common integrated circuit chip to provide a circuit that functions with ARC and AC on a second chip.

[Brief description of drawings]

FIG. 1 shows a silicon wafer on which a silicon integrated circuit is formed or mounted, and FIG. 2 shows a circuit configuration of some circuits shown in FIG. [Explanation of symbols for main parts] 10 …… System, 12 …… Wafer

Continuation of front page (56) References JP-A-54-100234 (JP, A) JP-A-58-149531 (JP, A)

Claims (4)

(57) [Claims] 1. A plurality of semiconductor IC chips (chip 0, chip 1, ... Chip N + 1) each connected to a signal conduit path (data / address bus 2) and prioritized for access to the signal conduit path. ) Of each of the above) determines the access to the signal conduit path, the circuit assigning a priority associated with each corresponding to the priority of one of the IC chips. Multiple arbitration conduit routes (A1, A2,
...... A7) and a clock conduit path (C1) for transmitting a clock signal, and each of the IC chips has a plurality of arbitration request circuits (except for the IC chip having the lowest priority in some cases). ARC0, ARC1, ... ARC7), each of which has multiple arbitration decision circuits (AC0, AC1, ... ARC), except for the IC chip with the highest priority in some cases. AC7), wherein the circuit comprises a first transmission gate element (Q1) in which each arbitration request circuit is integrated into a respective IC chip and has a control terminal and first and second output terminals. ), The control terminal is coupled to the clock conduit path via a first coupling means, the first and second output terminals each individually
Except for a part of the IC chip that determines whether the IC chip wants access to the signal conduit path and possibly the transmission gate element in the IC chip with the lowest priority, the second coupling means (D1 1) is connected to one of a plurality of arbitration conduit paths via), each arbitration decision circuit is integrated into each IC chip, and has at least as many input terminals as the number of higher priority IC chips. Input terminals of the binary logic gate or its logical equivalent in the arbitration decision circuit of a given IC chip, each of which has a higher priority. Connected to one of the conduit paths, or via a third coupling means (I12), Connected to the second output terminal of the first transmission gate of the arbitration request circuit of a given one of the IC chips, each arbitration determination circuit further including a latch circuit element (24) and a second transmission gate element (24). Q2), wherein the second transmission gate element is coupled to the clock conduit path via a fourth coupling means (I11) complementary to the first coupling means, and each of the control terminals comprises: A binary logic gate or a logical equivalent thereof and first and second output terminals coupled to an input terminal of the latch circuit element, wherein the latch circuit element further inputs a reset signal at the start of a cycle of operation. A circuit for resetting, wherein each of the first, second and third coupling means has only one input port. 2. The circuit according to claim 1, wherein at least one binary logic gate of the plurality of arbitration decision circuits is coupled to a node connected to a reference potential level (V _REF ). A circuit having an input terminal. 3. The circuit according to claim 1 or 2, further comprising a reset conduit path (RESET) coupled to each latch circuit element for resetting the latch circuit element. Circuit to be. 4. The circuit according to claim 1 or 2, wherein each of the first coupling means has a linear coupling, and each of the second coupling means has a linear coupling and a non-linear coupling. Each of the third coupling means has a line coupling, a second coupling means and an inverting driving circuit element, and each of the fourth coupling means has a line coupling and an inverting driving circuit element. A circuit having: