JP2541003B2 - Sample-hold circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit that samples and holds an instantaneous value of an analog signal, and more particularly to a sample and hold circuit that handles a high speed analog signal and is suitable for integration into an integrated circuit. .

2. Description of the Related Art Conventionally, as a sample hold circuit of this type, a circuit as shown in FIG. 3 is known, and its operation will be described below.

Now, in FIG. 3, the control input signals of the sample hold control input terminals 33 and 34 (normally, the input terminal 34 receives an inverted input of a rectangular wave whose phase is 180 ° different from the input terminal 33), respectively. In the case of the level state “H” and the low level state “L” (hereinafter always referred to as “H” and “L”), the transistor Q34 of the differential transistor pair Q34, Q35 and the differential transistor pair Q36, Q37, Both Q37 are conductive, both transistors Q35 and Q36 are cut off, and the state of this circuit is the sample mode. That is, the input terminal
The nunalog signal Vin input from 31 is applied to the base of the transistor Q31, and the transistor Q31 operates as an emitter follower. The diodes D31 to D33 connected to the emitter of the transistor Q31 operate as a level shift circuit, the current of which is supplied by the constant current source I34. _Assuming that the base-emitter voltage of the transistor Q31 is V _BE31 and the forward voltages of the diodes D31 to D33 are all equal, and V _D is set, the voltage applied to the base of the transistor Q32 is V _BE31 .
It becomes in-V _BE31 + 3V _D. The current obtained by adding the current of the constant current source I34 and the operating current of the transistor Q31 becomes the current of the constant current source I31 via the transistor Q34. The transistor Q32, which operates as an emitter follower and has the hold capacitor C _H connected to the emitter, receives the voltage of Vin-V _BE31 + 3V _D as a base and charges the hold capacitor C _H. If the base-emitter voltage of the transistor Q32 at this time is V _BE32 , the potential of the hold capacitor C _H becomes Vin− (V _BE31 + V _BE32 ) + 3V _D , and the potential is 3 V _D− (V _BE31 for the analog input signal Vin.
＋ V _BE32 ) Level shift and follow. Furthermore, the third
As shown in the figure, when an emitter follower circuit consisting of a transistor Q38 whose base is connected to the emitter of the transistor Q32 and a constant current source I33 is connected and the output signal V _O is taken out from the emitter of the transistor Q38, that is, the output terminal 32. When the base-emitter voltage of the transistor Q38 is V _BE38 , V _O = Vin- (V _BE31 + V _BE32 + V _BE38 ) + 3V
It becomes _D. Here, if the current densities of the transistors Q31, Q32, Q38 and the diodes D31 to D33 are set to be equal, V _BE31 + V _BE32 + V _{BE38 ≈3} V _D can be set, and as a result Vin ≈V _D It becomes possible. That is, in the sample mode, the output signal V _O follows the input signal Vin equally.

Next, the signals SH and SH of the terminals 33 and 34 are "L" and "H", respectively.
In the case of, the transistors Q34 and Q37 are both cut off, the transistors Q35 and Q36 are both conductive, and the circuit is in the hold mode. That is, since the transistors Q37 and Q32 are turned off, the charging operation of the hold capacitance G _H is stopped, and the transistor Q33 whose base is connected to one end of the hold capacitance G _H that is not on the ground side starts the operation to hold the hold capacitance G _H. The value of the potential Vin + V _D of _H is held. At this time, the currents of the constant current sources I31 and I32 are the diode D34 and the transistor Q.
35, Q36 from constant current source I34 and transistor Q33
Also, it is supplied from the power supply line 35 through the transistors Q35 and Q36.

As described above, in the sample mode, the output signal V _O follows the input signal Vin (V _O = Vin), and the sample holds the instantaneous value of the input signal Vin when the state switches to the hold mode. The function of the hold circuit is executed.

However, in the above-described conventional sample hold circuit, in the hold mode, the bias current (base current) of the transistor connected to the hold capacitance G _H.
Due to I _B , the output signal V _O exhibits a so-called droop characteristic in which it gradually exhibits a decreasing tendency at a rate of I _B / C _H.

On the other hand, in the case of handling a high-speed input signal, it is generally necessary to set the operating current of the element to a large value, and the bias current also increases, so that the droop becomes large in the conventional example as shown in FIG. After that, the original holding function of the sample hold circuit is lost.

In addition, the bias current I _B
A junction field effect transistor or a transistor with a large current amplification factor is often used as the transistor connected to the hold capacitor C _H with the intention of reducing the In addition, a process for simultaneously manufacturing the above-mentioned special transistor is required, and the process becomes complicated or expensive only for the purpose of dealing with the droop problem.

Furthermore, as in the case of using a circuit technology such as making the transistor connected to the hold capacitance C _{H a} Darlington connection type or newly providing a bias current compensation circuit, or when increasing the value of the hold capacitance G _H. However, even if they do not require complicated and expensive integrated circuit manufacturing processes, they are not suitable for speedup in nature, and the circuit response cannot follow the rapidly changing input signal in the sample mode. Cause problems.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore an object of the present invention is to provide a novel sample hold circuit capable of solving the above-mentioned problems inherent in the conventional technology. is there.

Means for Solving the Problems In order to achieve the above object, in a sample hold circuit according to the present invention, a constant current source and one transistor whose collector is connected to the constant current source and a base of the other transistor are constant. A first differential circuit including the other transistor biased to a voltage and having a collector connected to a power supply;
A first transistor having a base connected to the constant current source, a collector connected to the power source, and an emitter connected to a hold capacitor; and a single or a plurality of diodes having an anode side connected to the constant current source, one of A second differential circuit in which the collector of the transistor is connected to the common emitter of the first differential circuit and the collector of the other transistor is connected to the constant current source, and the collector of one transistor is connected to the power supply and the other A third differential circuit in which the collector of the transistor is connected to the emitter of the first transistor, an emitter follower that operates by receiving the voltage of the hold capacitor at the base, and the output of the emitter follower has the first difference. Means for returning the collector of the driving circuit to the base of the transistor connected to the constant current source.

EXAMPLES Next, the present invention will be specifically described with reference to the drawings for each of its preferable examples.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

Referring to FIG. 1, the input signal SH of the sample hold control input terminal 13 and its inverting input terminal 14 is now ▲
When ▼ is “H” and “L” respectively, that is, when this circuit is in the sample mode, the differential transistor pair Q14, Q
Of the 15 and the differential transistor pair Q16, Q17, the transistors Q14, Q17 are both in the conductive state, and the transistors Q15, Q16 are in the cut-off state. In this case, this circuit includes a differential transistor pair Q11, Q12, transistors Q13, Q18, Q14, Q17,
The constant current sources I11, I12, I13 and I14 and the resistors Rf and Rs operate as an inverting amplifier. Input signal Vin ′ and output signal V _O
Relationship with Becomes Assuming that Rf = Rs, V _O = −Vin (2), and the gain −1 operates as an inverting amplifier.

When the input control signals SH and ▲ ▼ are “L” and “H”, respectively, that is, when the transistors Q14 and Q17 are both in the cutoff state and the transistors Q15 and Q16 are both in the conduction state, this circuit is in the hold mode. And an emitter follower operation in sample mode, to stop the charging and discharging operation of the hold capacitor G _H, the instantaneous value of the potential of the hold capacitor G _H is held. In this case, conditions for the transistor Q13 to the blocking state, the transistors Q11, Q13, Q18 of the base-emitter voltage of the respective _{V BE11, V BE13, V BE20} , a diode D11
Assuming that the forward voltage of V _D is V _D , V _O + V _BE18 + V _BE13 > −V _BE11 −V _D ……… (3). Therefore, V _BE11 + V _BE13 + V _BE18 + V _D > −V _O = Vin ... (4)

In the hold mode, the operating currents of the transistors Q15 and Q16 in the conductive state are as follows: for the transistor Q15, the current of the transistor Q11 is through the diode D11 and the current of the constant current source I14 is its operating current. Supplied directly from line 15.

In the above description, it was assumed that Rf = Rs, but it is naturally possible to use Rf ≠ Rs and use a gain in the sample mode other than −1.

In the first embodiment shown in FIG. 1, the hold capacitance G _H
Assuming that the leakage current of the transistor Q18 is negligible,
If the current amplification factor of is _FE , then the druprate dV _O / dt
Is Becomes On the other hand, in the conventional example, the transistor
Assuming the current gain of Q3 and Q8 is h _FE Therefore, assuming that the value of each constant current source is I1 = I2 = I3 = I13,
If I1 = 2 · I4 is set Becomes In the druprate of the embodiment shown in FIG. 1, since the transistor Q13 can be turned off by the conduction of the diode D11, the transistor Q3 of the conventional example can be omitted. Therefore, the droop rate can be greatly reduced to 2/5 of the conventional example.

FIG. 2 is a circuit diagram showing a second embodiment according to the present invention.

Referring to FIG. 2, the second embodiment is an example in which an element Q19 in which a collector and a base of a transistor are connected is used as a diode instead of the diode D11 in FIG. Although a detailed description of the structure and operation of the same parts as those of the first embodiment is omitted, parasitic capacitance can be reduced when integrated into an integrated circuit by using a diode-connected transistor instead of a diode. ,
Higher speed can be obtained as a sample hold circuit.

EFFECTS OF THE INVENTION As described above, according to the present invention, in a sample hold circuit that samples an instantaneous value of an analog signal and further holds the instantaneous value, particularly considering integration into an integrated circuit,
The standard manufacturing process eliminates the need for a complicated or expensive integrated circuit manufacturing process for simultaneously forming a special element such as a junction field effect transistor without impairing the follow-up speed during sampling. It is possible to obtain the effect that the holding characteristic can be improved more than twice as compared with the conventional circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention,
FIG. 2 is a circuit diagram showing a second embodiment of the present invention,
FIG. 3 is a circuit diagram of a conventional example. 1, 11 …… Input terminals, 2,12 …… Output terminals, 3,4,1
3, 14 ... Control input terminals 5, 6, 15, 16 ... Power line, Q1
~ Q8, Q11 ~ Q19 ... Transistor, D1 ~ D4, D11 ... Diode, C _H ... Hold capacitance, Rs, Rf ... Resistor, I1 ~
I4, I11 to I14 ... Constant current source

Claims (1)

(57) [Claims] 1. A first current source comprising a constant current source and one transistor whose collector is connected to the constant current source and the other transistor whose base is biased to a constant voltage and whose collector is connected to a power source. Differential circuit of
A first transistor having a base connected to the constant current source, a collector connected to the power supply, and an emitter connected to a hold capacitor; and an anode side connected to a common emitter section of the first differential circuit and a cathode side connected to the constant current source. A single or a plurality of diodes connected to the current source, and a second transistor in which the collector of one transistor is connected to the common emitter of the first differential circuit and the collector of the other transistor is connected to the constant current source. A differential circuit, a third differential circuit in which the collector of one transistor is connected to the power supply and the collector of the other transistor is connected to the emitter of the first transistor, and the base receives the voltage of the hold capacitor. An emitter follower that operates, wherein the output of the emitter follower is the collector of the first differential circuit and the constant current. Is fed back to the base of the transistor connected to the first resistor via the first resistor, and a signal is input to the base of the transistor connected to the constant current source via the second resistor, and the second difference A base of a transistor whose collector is connected to the constant current source,
The collector of the third differential circuit uses the base of the transistor connected to the power supply as a control input terminal, and the bases of the other transistors of the second and third differential circuits use the inverting control input terminal. A sample and hold circuit characterized in that