JPH061639B2 - Sample-hold circuit - Google Patents

Description

The present invention relates to a sample and hold circuit that samples and holds an instantaneous value of an analog signal, and is particularly effective when handling a high speed analog signal and applying it to an integrated circuit. Regarding technology.

(Prior Art) Conventionally, as a sample hold circuit of this type, there is a circuit as shown in FIG. 2, and its operation will be described below.

Now, in FIG. 2, sample hold control input terminals 3 and 4 (normally, an inverted input of a rectangular wave whose phase is 180 degrees different from the input terminal 3 is input to the input terminal 4).
When the control input voltages SH, ▲ ▼ of the above are in the high level state “H” and the low level state “L” (hereinafter simply referred to as “H” and “L”), the differential transistor pair Q ₄ , Q. ₅ and the transistor Q _4, Q ₇ are both conducting state of the differential transistor pair Q _6, Q _7, the state of the transistor Q _5, Q ₆ is the circuit both become cut off is the sample mode. That is, the analog input signal V _in input from the input terminal 1 is applied to the base of the transistor Q ₁ , and Q ₁ operates as an emitter follower. The diodes D ₁ to D ₃ connected to the emitter of Q ₁ operate as a level shift circuit, the current of which is supplied by the constant current source I ₄ . Assuming that the base-emitter voltage of Q ₁ is V _BE1 and the forward voltages of the diodes D ₁ to D ₃ are all equal, and V _D is set, the voltage applied to the base of the transistor Q ₂ is V _in −V _BE1 + 3V. It becomes _D. The current obtained by adding the current of the constant current source I ₄ and the operating current of Q ₁ becomes the current of the constant current source I ₁ via Q ₄ . Q _{2 which} operates as an emitter follower with the hold capacitor C _H connected to the emitter is V _in −V _BE1.
The voltage of + 3V _D is used as a base to charge C _H. If the base-emitter voltage of Q ₂ at this time is V _BE2 , the potential of C _H becomes V _in − (V _BE1 + V _BE2 ) + 3V _D , and the potential is 3 V _D − (V _BE1 + V _BE2 ) with respect to V _in . It is level-shifted and follows. Further, as shown in FIG. 2, an emitter follower circuit composed of a transistor Q ₈ whose base is connected to the emitter of Q ₂ and a constant current source I ₃ is connected, and an output signal V is output from the emitter of Q ₈ , that is, the output terminal 2. _{When 0} is taken out, the base-emitter voltage of Q ₈ is V
_{When BE8} , V ₀ is V _in − (V _BE1 + V _BE2 + V _BE8 ) + 3V _D
Becomes Here, if the current densities of the elements Q ₁ , Q ₂ , Q ₈ , D ₁ to D ₃ are set to be equal, V _BE1 + V _BE2
+ V _{BE8 ≈3V D} , which results in V _in ≈V ₀
It becomes possible to That is, in the sample mode, the output signal V ₀ follows the input signal V _in equally.

Next, SH, ▲ ▼ respectively "L", when the _{"H", Q 4, Q} 7 are both cut off, Q _5, Q ₆ becomes both conductive, the circuit goes into the hold mode. That is,
Since Q ₇ and Q ₂ are cut off, the charging operation of C _H is stopped, the transistor Q ₃ whose base is connected to one end of C _H that is not the ground side starts operating, and the potential of C _H is V _in + V _D
The value of is retained. At this time, the currents of the constant current sources I ₁ and I ₂ are supplied from the constant current source I ₄ via the diodes D ₄ and Q ₅ and Q ₆ and from the power supply line 5 via Q ₃ and Q ₅ and Q _6. To be done.

As described above, according to FIG. 2, in the sample mode, the output signal V ₀ follows the input signal V _in (V ₀ =
V _in ), and when the state is switched to the hold mode, the function of the sample hold circuit that holds the instantaneous value of V _in is executed.

(Problems to be Solved by the Invention) In the conventional sample hold circuit described above, in the hold mode, the output signal V ₀ is caused by the bias current (base current) I _{B of} the transistor connected to the hold capacitor C _H. Shows a so-called droop characteristic in which the value gradually decreases at a rate of I _B / C _H.

When handling a high-speed input signal, it is generally necessary to set the operating current of the device to a large value, so that the bias current also increases, and the droop becomes too large in the conventional example shown in FIG. You will lose functionality.

Further, in order to reduce droop, the bias current I _B
In order to reduce the capacitance, a junction field effect transistor or a transistor having a large current amplification factor is often used as the transistor connected to the hold capacitor C _H. However, if a transistor of a type different from that of other parts is adopted, even though it is a very small part, a process for simultaneously manufacturing the above-mentioned special transistor is required in addition to the standard integrated circuit process in the integrated circuit. Therefore, there is a disadvantage that the integration process becomes complicated and expensive.

In order to improve the droop characteristic, the transistor connected to the hold capacitance C _H has a Darlington connection type, or circuit technology such as newly providing a bias current compensation circuit is used, or the value of the hold capacitance C _H is increased. A measure that does not require a complicated and expensive integrated circuit process is conceivable. However, the adoption of such a circuit is essentially not suitable for speeding up the circuit response, and causes a problem that the circuit response cannot follow an input signal that changes rapidly in the sample mode.

(Means for Solving Problems) A sample-hold circuit of the present invention includes a first transistor having a base to which an analog input signal to be sampled and held is input, and a collector connected to a power supply; A first diode element comprising a single or a plurality of diodes whose cathode side is connected to the emitter or a diode-connected transistor;
A constant current source connected to the anode side of the diode element, and a second diode or a diode-connected transistor whose anode side is connected to the emitter of the first transistor and whose cathode side is connected to the constant current source; A first differential circuit in which the collector of the transistor is connected to the emitter of the first transistor and the collector of the other transistor is connected to the anode side of the first diode element; and the base is the first diode element. A second transistor connected to the anode side of the collector of which the collector is connected to the power supply and the emitter of which is connected to the hold capacitor, and the collector of one transistor is connected to the power supply and the collector of the other transistor is connected to the emitter of the second transistor. A second differential circuit connected thereto.

(Operation) In the present invention, an analog switch of a type in which an operating current is controlled by a differential switch is used as an input circuit to switch between the sample mode and the hold mode. Then, as the operating current of the differential pair in the hold mode, the current is directly supplied from the path from the first transistor to the second diode (or the diode-connected transistor), the constant current source, and the power supply line, so that the second current is supplied. The transistor (holding capacity charging transistor) is cut off to eliminate the droop caused by the bias current.

(Example) Next, this invention is demonstrated with reference to drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention. Now, when the input voltages SH and ▲ ▼ of the sample hold control input terminal 13 and its inverting input terminal 14 are “H” and “L” respectively, that is, when the state of this circuit is the sample mode, the differential transistor pair Q _14, the transistors Q _14, Q ₁₇ are both conductive state of Q ₁₅ and the differential transistor pair Q _16, Q _17, transistors Q _15, Q ₁₆ are both cut off. The analog signal V _in input from the input terminal 11 is applied to the base of the transistor Q ₁₁ , and the transistor Q ₁₁ operates as an emitter follower. Diodes D ₁₁ , D ₁₂ , and D ₁₃ connected to the emitter of the transistor Q ₁₁ are supplied with current from the constant current source I _{14 and} operate as a level shift circuit. At this time, the current of the constant current source I ₁₁ is equal to the current of I ₁₄ and Q ₁₁
Operating current is added. The transistor Q ₁₂ having the hold capacitor C _H connected to the emitter operates as an emitter follower and charges C _H. Q _11, the base-emitter voltage of Q ₁₂ each V _BE11, V _BE12, a diode D ₁₁
To the potential of the C _H if the forward voltage can be assumed that all equal V _D of D _{13 is, V in - (V BE11 +} V BE12) +
It is possible to put a 3V _D, 3V with respect to V _{in D} - (V _BE11
+ V _BE12 ) level shifts and follows the input. Further, as shown in FIG. 1, an emitter follower circuit consisting of a transistor Q ₁₈ whose base is connected to the emitter of Q ₁₂ and a constant current source I ₁₃ is added to output an output signal V from the emitter of Q ₁₈ , that is, the output terminal 12. If they were taken out to _0, the base when the emitter voltage is assumed to be V _BE18 V ₀ = V _in the Q ₁₈ - a _{(V BE11 + V BE12 + V} BE18) -3V D. Here _{Q 11, Q 12, Q 18} , when to D ₁₁ not set equal to the current density of each element of _{D 13 V BE11 + V BE12 ≒} 2
_{V D, V BE11 + V BE12} + V BE18) it is possible to ≒ 3V _D, therefore C _H potentials V _in + V _D, the output voltage V ₀
= V _in , which follows the input signal V _{in in} each sample mode.

When SH and ▲ ▼ are “L” and “H”, respectively, that is, when both Q ₁₄ and Q ₁₇ are in the cutoff state and Q ₁₅ and Q ₁₆ are both in the conduction state, this circuit is in the hold mode. In the sample mode, the emitter follower operates and C _H
Q ₁₂ that has performed the charging becomes cut off by the conduction of the diode D _14, and stops the charging operation, the potential of the C _H V
The instantaneous value of _in + V _D is retained. That is, the operating currents of Q ₁₅ and Q _{16 in} the conductive state are the same as the power supply line 15 with respect to Q _16.
Supplied from, also with respect to Q ₁₅ is obtained by adding the current flowing in the current path and the power supply line 15 of _{I 14, Q 11, D 14} . Therefore, the bias current is not supplied for Q _12, Q ₁₂ becomes cut off.

As shown in FIG. 1, in an example in which an emitter follower is added to the output portion for driving a load in practice, the leakage current of the transistor Q ₁₈ and the hold capacitor C _H is negligible and the current amplification factor of Q ₁₈ is neglected. Assuming that the current amplification factor of the transistors Q ₃ and Q ₈ is h _FE , Therefore, assuming that the value of each constant current source is I ₁ = I ₂ = I ₃ = I
Assuming ₁₃ , I ₁ = 2 · I ₄ Becomes The druprate of the embodiment shown in FIG. Therefore, according to the circuit of this embodiment, the droop rate can be greatly reduced to 2/5 of that of the conventional example.

(Effects of the Invention) As described above, according to the present invention, in a circuit for sampling an instantaneous value of an analog signal and holding it, that is, a sample hold circuit, particularly when an integrated circuit is taken into consideration, tracking at the time of sampling is performed. A standard process is used to maintain the retention characteristics of a conventional circuit without sacrificing speed and without requiring a complicated or expensive integrated circuit process for simultaneously forming a special element such as a junction field effect transistor. There is an effect that it can be improved more than twice as compared with.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional example. 1, 11 ... Input terminal, 2, 12 ... Output terminal, 3, 4, 13,
14 ... Control input terminal, 5, 6, 15, 16 ... Power supply line, Q ₁ ~
Q _8, Q ₁₁ ~Q ₁₈ ... _{transistor, D 1 ~D 4, D 11} ~D
₁₄ ... Diode, C _H ... Hold capacitance, I _{1 to} I ₄ , I ₁₁
~ I ₁₄ ... constant current source.

Claims (1)

[Claims] 1. An analog input signal to be sampled and held is input to a base and a collector is connected to a power supply.
Connected to the anode side of the first diode element, and a first diode element composed of a single or a plurality of diodes whose cathode side is connected to the emitter of the first transistor or a diode-connected transistor A constant current source, a second diode or a diode-connected transistor whose anode side is connected to the emitter of the first transistor and whose cathode side is connected to the constant current source, and the collector of one of the transistors is the first transistor. A first differential circuit connected to the emitter of the transistor and the collector of the other transistor connected to the anode side of the first diode element; and a base connected to the anode side of the first diode element and a collector connected to the power supply. Connected to the emitter and a hold capacitor connected to the second A sample-hold circuit comprising a transistor and a second differential circuit in which the collector of one transistor is connected to the power supply and the collector of the other transistor is connected to the emitter of the second transistor. .