JP2544838B2 - Switching circuit for magnetic disk read amplifier - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read amplifier switching circuit for a magnetic disk, and more particularly to a magnetic disk read amplifier switching circuit for switching a plurality of read amplifiers for reading from a magnetic disk.

[0002]

2. Description of the Related Art A conventional switching circuit for such a magnetic disk read amplifier is connected to a plurality of magnetic heads and is read out to control the read amplifier by an inverter circuit.

FIG. 3 is a switching circuit diagram of a magnetic disk read amplifier showing such a conventional example. As shown in FIG.
The switching circuit of the conventional magnetic disk read amplifier switches the current output type differential amplifiers 1 and 2 as the read amplifiers in which the magnetic heads 3A and 3B are connected to the input side. That is, the non-inverting output terminals and the inverting output terminals of the differential amplifiers 1 and 2 are connected and connected to the output terminals O1 and O2, respectively, and also connected to the voltage source 5 via the load resistors R1 and R2. To switch between the differential amplifiers 1 and 2, a switching control circuit including an inverter circuit (hereinafter referred to as INV) 11 connected to a switching signal input terminal IN for inverting the switching signal A, a voltage source 4, and an NPN transistor Q3. And a constant current source 1a and 2a for switching the constant currents of the differential amplifiers 1 and 2 depending on the voltage of the switching signal input terminal IN and the output voltage of INV11. Current switching NPN transistor Q1,
And Q2. The emitters of the transistors Q1 and Q2 are commonly connected to the constant current source 10, and the transistor Q1
A constant current I0 of 1 and Q2 is supplied. The current I01 is I
11 + I21, the current I02 is I12 + I22, and the current I0 is I1 + I2.

FIG. 4 is a timing chart of signals at various parts of the circuit shown in FIG. As shown in FIG. 4, in the switching circuit of the conventional read amplifier, first, the switching signal A from the switching signal input terminal IN is input.
The transistors Q1 and Q2 are driven by supplying the terminal voltage and the output signal E of INV11 to the bases of the constant current switching transistors Q1 and Q2. Here, the voltage of the switching signal A and its inverted signal E has a high level of 2VF.
(VF is the same as the base-emitter voltage VBE of Tr), and the low level is GND. Therefore, the collector voltage Q3 (c) of the constant current setting transistor Q3 becomes a constant voltage with the high level being VF, but the rising time (tr) and the falling time (tf) of the switching signal A and the delay time (tpd) of the INV11. ), The delay time difference Δtd (= tp
The larger d) is, the L → H, H of the switching signal A is increased.
The high level (VF) of the collector voltage Q3 (c) of TrQ3 drops when L changes. Therefore, TrQ3
The collector-emitter voltage VCE of
Since Q3 is saturated, the constant current I0 decreases in synchronization with the collector voltage Q3 (c) of TrQ3. This current change amount is ΔI0. Since this constant current I0 changes by ΔI0, the current output type differential amplifiers 1 and 2 that make the collector currents I1 and I2 of the constant current switching transistors Q1 and Q2 constant currents.
The output currents I01 and I02 of the differential amplifiers 1 and 2 are
When the potential difference between the input terminals is 0, I1 = I11 + I12 I2 = I21 + I22 I01 = I02 = I0 / 2
2). Therefore, the change amount ΔI of the output currents I01 and I02
01 and ΔI02 are ΔI01 = ΔI02 = ΔI0 / 2, and voltage conversion is performed by the load resistors R1 and R2.
The output voltages of the output terminals O1 and O2 are the differential amplifiers 1 and 2
Is output as voltage fluctuations G1 and G2 called glitches.

[0005]

The switching circuit of the above-mentioned conventional magnetic disk read amplifier has the switching signals tr and tf.
Since there is a delay time due to INV and INV, there is a drawback that a delay time Δtd occurs in the operation of the pair of constant current switching transistors, and a glitch occurs when switching the read amplifier composed of the differential amplifier. Further, in the conventional read amplifier switching circuit, since the glitch is input as a signal to the automatic gain control circuit (AGC circuit) connected to the next stage of the differential amplifier which is the magnetic disk read device, the AGC circuit operates and the differential The response of the magnetic disk reading device at the time of switching the amplifier becomes slow.
Therefore, there is a drawback that the speedup and the capacity increase of the magnetic disk device are hindered.

It is an object of the present invention to prevent the occurrence of glitches during switching of the read amplifier, and to eliminate the influence on the next stage to realize high speed and large capacity of the magnetic disk device. It is to provide a switching circuit of a read amplifier.

[0007]

A switching circuit of a magnetic disk read amplifier according to the present invention comprises a plurality of currents each having an input terminal connected to a plurality of magnetic heads and having inverting / non-inverting output terminals and a constant current terminal. An output type differential amplifier, a load connected to each of the inverting / non-inverting output terminals of the plurality of differential amplifiers, and a differential connection for supplying a signal based on the switching signal to the bases, and collectors connected to each other. A pair of transistors connected to the constant current terminal of the differential amplifier, and a constant current source commonly connected to the emitters of the pair of transistors, the base voltage of each of the pair of transistors by the switching signal. In a switching circuit of a magnetic disk read amplifier for controlling and selecting the differential amplifier, the rising time and falling time of the switching signal and the switching signal are Of a differentially connected one that changes from a non-selected state to a selected state at the time of constant current switching, and a delay circuit that delays the switching signal by a time sufficiently longer than the delay time difference before it is transmitted to the bases of a pair of dynamically configured transistors. A switching control circuit is provided that includes a transistor and gate means that simultaneously sets the other differentially connected transistor that changes from the selected state to the non-selected state to the differential state for a predetermined time.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a switching circuit diagram of a magnetic disk read amplifier showing an embodiment of the present invention. As shown in Figure 1,
In this embodiment, the same elements are assigned the same numbers as in the conventional example shown in FIG. Here, the magnetic head 3
A and 3B, current output type differential amplifiers 1 and 2, load resistors R1 and R2, and constant current switching transistors Q1 and Q.
2 and the constant current source 10 composed of the constant voltage source 4 and the NPN transistor Q3 have the same configuration as the conventional example. That is, the base voltage of each of the pair of transistors Q1 and Q2 is controlled by the switching signal A supplied to the input terminal IN, and I1 or I2 based on the current I0 of the constant current source 10 is controlled.
To the differential amplifier 1 or 2 to select the differential amplifier 1 or 2. Particularly, in this embodiment, the rising time (tr) and the falling time (tf) of the switching signal A and the NPN transistor Q1, in which the switching signal A is differentially configured.
A switching control circuit 9 including an OR circuit 6 and a NAND circuit 7 and a delay circuit 8 that delays the switching signal A for a time t1 (t1> tr + tf + Δtd) sufficiently longer than the delay time difference (Δtd) before being transmitted to the base of Q2. Be prepared. The switching control circuit 9 switches the differentially connected transistor Q1 or Q2 which changes from the non-selected state to the selected state and the differentially connected transistor Q2 or Q1 which changes from the selected state to the non-selected state at the time of constant current switching. This is to set the differential state at the same time by t (t≈t1-Δtd-tr-tf). That is, the switching control circuit 9
Is a switching input signal A from a switching terminal IN for switching the differential amplifiers 1 and 2 for a fixed time t1 (t1> Δtd + tr +).
delay circuit 8 for delaying by tf) and switching terminal IN
Of the input signal A and the output B of the delay circuit 8 from the OR circuit 6 and the NAND circuit 7 from the NAND circuit. The output D of the OR circuit 6 is supplied to the base of the constant current switching transistor Q2. , The output C of the NAND circuit 7
Is supplied to the base of the constant current switching transistor Q1.

FIG. 2 is a timing chart of signals at various parts of the circuit shown in FIG. As shown in FIG. 2, when the switching input signal A from the switching terminal IN in the switching control circuit 9 is switched in the order of L → H → L, the output B of the delay circuit 8 becomes a signal delayed by the time t1. This time t1 is the gate circuit (NAND
7, OR6) delay time difference (tpd1, tpd2) delay time difference Δtd (Δtd = 1tpd1-tpd21)
Since it is set to be sufficiently longer than TR, and tr, tf, OR
Both the output D of the circuit 6 and the output C of the NAND circuit 7 simultaneously have a high level for the switching time t (t≈t1-tr-tf) of the switching signal A. Therefore, the collector voltage Q3 (c) of the transistor Q3 forming the constant current source 10 becomes a constant voltage and the transistor Q3 does not saturate, so that the constant current I0 does not change. Therefore, the constant currents I1 and I2 supplied to the constant current terminals 1a and 2a of the differential amplifiers 1 and 2 when the current source is switched are I1 = I2 = I0 /
2, the current I01 flowing through the load resistors R1 and R2,
I02 does not change, and the voltage of the output terminals O1 and O2 does not change. In short, in the present embodiment, the constant currents I1 and I2 based on the switching signal A are not switched at once, but are switched step by step to prevent the output voltage from glitching, and to prevent the next stage of the read circuit. Has stabilized.

[0011]

As described above, according to the present invention, when a read amplifier of a magnetic disk constituted by a differential amplifier is switched, a pair of constant current switching transistors are simultaneously turned on so that a constant current source Since the current value is not changed, there is an effect that it is possible to prevent load voltage fluctuation called glitch. Further, according to the present invention, when the read amplifier of the magnetic disk is switched, the glitch at the time of switching is not output to the AGC circuit connected to the next stage. Therefore, the AGC circuit can quickly respond when the read amplifier is switched, and the magnetic disk can be quickly responded. There is an effect that it is possible to realize high speed and large capacity of the device.

[Brief description of drawings]

FIG. 1 is a switching circuit diagram of a magnetic disk read amplifier showing an embodiment of the present invention.

FIG. 2 is a timing chart of signals at various parts of the circuit shown in FIG.

FIG. 3 is a switching circuit diagram of a magnetic disk read amplifier showing a conventional example.

FIG. 4 is a timing chart of signals of various parts of the circuit shown in FIG.

[Explanation of symbols]

 1, 2 Current output type differential amplifier (readout amplifier) 3 Magnetic heads 1a, 2a Constant current terminals 4, 5 Voltage source 6 OR circuit 7 NAND circuit 8 Delay circuit 9 Switching control circuit 10 Constant current source R1, R2 Load resistance Q1 ~ Q3 NPN / transistor IN switching signal input terminal O1, O2 output terminal

Claims (2)

(57) [Claims] 1. A plurality of current output type differential amplifiers each having an input terminal connected to each of a plurality of magnetic heads and provided with inverting / non-inverting output terminals and a constant current terminal, and the inverting of the plurality of differential amplifiers. A load connected to each of the non-inverting output terminals, and a pair of transistors differentially connected to each of the bases for supplying a signal based on the switching signal and each collector connected to the constant current terminal of the differential amplifier. ,
A switching circuit for a magnetic disk read amplifier, which has a constant current source commonly connected to the emitters of the pair of transistors and controls the base voltage of each of the pair of transistors by the switching signal to select the differential amplifier. At
A delay circuit and a constant current switch for delaying the switching signal by a time sufficiently longer than the rise time and the fall time of the switching signal and the delay time until the switching signal is transmitted to the bases of the pair of differentially configured transistors. And a gate means for simultaneously making one of the differentially connected transistors changing from the non-selected state to the selected state and the other differentially connected transistor changing from the selected state to the non-selected state simultaneously for a predetermined time. A switching circuit for a magnetic disk read amplifier, comprising a switching control circuit provided. 2. A switching circuit for a magnetic disk read amplifier according to claim 1, wherein said gate means is composed of an OR circuit and a NAND circuit.