JP2548396B2 - Potential control circuit - Google Patents

Description

The present invention relates to a potential control circuit that pulls up the potential of a certain line, and provides a potential control circuit capable of reducing power consumption, improving responsiveness, and preventing an occupied area from increasing. For that purpose, a large number of drivers are connected to a predetermined line, one or more of the drivers are driven to lower the potential of the line to a low level, and when the driver driving is stopped, In a potential control circuit for raising the potential of a line to a high level, the pull-up element is composed of a MOS transistor, and control means for controlling the gate potential of the MOS transistor is provided, and the control means performs at least pull-up. The MOS transistor is applied with a potential corresponding to each state of a non-existence state, a weak pull-up state and a strong pull-up state. It is configured to supply to the gate of.

[Industrial applications]

The present invention relates to a potential control circuit, and more particularly to a potential control circuit that pulls up a potential on a certain line.

The potential control circuit is used, for example, when the bit line of SRAM is kept at a predetermined potential, and in practice, a load transistor is provided in each bit line to do this. Also, LSI
When there is a bus line in the chip of, the potential control circuit is used when pulling up the potential of this bus line,
In this case, the transistor is connected to the bus line by wired OR, and the transistor is also connected to the pull-up load. Such a potential control circuit tends to require lower power consumption and a smaller mounting area.

[Conventional technology]

As a conventional potential control circuit, for example, there is one as shown in FIG. 6, in which 1 is a bus line in a chip, 2 is a pull-up element, and 3 is an inverter for extracting an output from the bus line 1. , 4a to 4n are drivers. When a MOS transistor is used as the load pull-up element 2, for example, as shown in FIG.
When the S transistor Q ₁ is used, its gate potential is dropped to GND and fixed at “L” level, and the MOS transistor Q ₁ is used as a resistance component. Alternatively, as shown in FIG. 7B, a binary signal of “H” level (≈Vcc) and “L” level (≈GND) is applied to the gate of the MOS transistor Q ₁ to switch pull-up invalid / valid. In some cases. However, in either case, when used as a pull-up, the gate potential is one of the binary signals.

On the other hand, the driver 4a to 4n, for example 8 using the MOS transistor Q ₂ of N-channel as shown in FIG, an input signal at its gate addition, bus line is turned on even one of the driver 4a to 4n 1 Is set to "L" level (≈ GND).

[Problems to be Solved by the Invention]

However, in such a conventional potential control circuit, as shown in FIG.
When the transistor Q ₁ is on, the MOS transistor Q ₂ as a driver is off, and the bus line 1 is at the “H” level in the pull-up state (Ci is a parasitic capacitance in the figure),
As shown in FIG. 2B, the MOS that is the driver of the bus line 1
When the transistor Q ₂ is turned on (when the gate potential becomes L → H), a through current i flows through the load as shown by the arrow in the figure, and especially the number of bus lines 1 is large and pull-up occurs. If there are many places, the power consumption becomes unnecessarily large. In FIG. 9B, when the MOS transistor Q ₂ is on, the discharge current i _C also flows from the parasitic capacitance Ci, and the bus line 1 changes from H to L. At this time, the "L" level is shown in the figure. As shown by the change characteristic, the time delay τ ₁ of level change is relatively large, and the responsiveness deteriorates. Then, in the steady state, as shown in FIG. 9 (c), the bus line 1 becomes "L" level, and a large through current i always flows. This is also one of the reasons for the large power consumption.

On the other hand, in order to reduce the through current i, it is conceivable to increase the resistance of the MOS transistor Q _1. However, in this case, the MOS transistor Q ₂ is turned off and the bus line is turned off as shown in FIG. 9 (d). When pulling up the potential of 1 from L to H, it takes a long time to charge up the parasitic capacitance C, and a large time delay τ ₂ as shown in the change waveform in the figure.
Is present, and the responsiveness becomes extremely poor. Therefore, the through current i cannot be made too small.

Therefore, if the through current i remains large, the bus line 1
It is necessary to use a transistor having a large driving capability for the driver of, and eventually the occupied area increases.

Therefore, an object of the present invention is to provide a potential control circuit capable of reducing power consumption, improving responsiveness, and preventing an occupied area from increasing.

[Means for solving the problem]

In order to achieve the above object, the potential control circuit according to the present invention connects a large number of drivers to a predetermined line, drives one or more of the drivers to lower the potential of the line to a low level, and drives the drivers. When stopped, in a potential control circuit that pulls up the potential of the line to a high level by a pull-up element, the pull-up element is composed of a MOS transistor, and a control means for controlling the gate potential of the MOS transistor is provided. The means is configured to supply a potential corresponding to at least a pull-up state, a weak pull-up state, and a strong pull-up state to the gate of the MOS transistor.

[Action]

According to the present invention, in the normal pull-up (weak pull-up) state, the gate potential of the MOS transistor, which is the pull-up element, is kept at the intermediate potential, and when the parasitic capacitance of the line needs to be charged up, the gate potential is strong. The line is kept up and the line is rapidly charged up. The gate potential is maintained so that the MOS transistor is completely turned off when pull-up is not required.

Therefore, when there is no pull-up, a through current does not flow, at the start of pull-up, the response is improved by rapid charge-up, and only one MOS transistor having a different pull-up state is required. There is no increase in occupied area. Further, when the line is pulled down, a weak shoot-through current is sufficient, so the power consumption is also reduced.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

1 to 5 are diagrams showing an embodiment of the potential control circuit according to the present invention. FIG. 1 is an overall configuration diagram of the potential control circuit. In this figure, Q ₁₁ is a P-channel MOS transistor as a pull-up element, and 11 is a MOS transistor Q.
Control circuit for controlling gate potential of ₁₁ (corresponding to control means)
Others are the same as in the conventional example and are denoted by the same reference numerals.

The control circuit 11 is shown in detail in Figure 2, is constituted by MOS transistors Q ₁₂ to Q ₁₄ and N-channel MOS transistors Q ₁₅ to Q ₁₇ of the P-channel, MOS transistor
The control signal A is applied to the gates of Q ₁₂ and Q ₁₇ , and the control signal B is applied to the gates of the MOS transistors Q ₁₃ and Q ₁₆ . The control signals A and B are for controlling the gate potential of the MOS transistor Q ₁₁ , and are generated by an external command (for example, an external circuit) to change the pull-up mode. The control signal C is applied to the gate of the MOS transistor Q ₁₁ and is generated by the control circuit 11. The MOS transistor Q ₁₁ has three modes of weak on, strong on and off depending on the control signal C applied to the gate, which corresponds to weak pull-up, strong pull-up and no pull-up (pull-up disabled) respectively. ,
Regarding the relationship with the shoot-through current, the shoot-through current is small, the shoot-through current is large (rapid charge-up), and there is no shoot-through current. The relationship between the control signals A to C and the above items is as follows.
It is shown as in the following table.

Incidentally, in the state without pull-up, it has nothing to do with the potential of the control signal B. A weak pull-up is a case where the MOS transistor Q ₁₁ is in the ON state, but its resistance is large, and a strong pull-up is a case where its resistance is small.

 In the above configuration, the operation will be described for each mode.

When not a pull-up (disabled equivalent) when the potential of the control signal A is at the "L" level, MOS transistor Q ₁₂ is turned on, the MOS transistor Q ₁₇ is turned off, M
The signal C is pulled up to V _CC through the OS transistor Q ₁₂ and becomes "H" level. This allows the MOS transistor Q
_{When 11} is off, bus line (corresponding to line) 1 is not pulled up. Further, since the MOS transistor Q ₁₁ is off at this time, naturally no through current flows. In this state, regardless of whether the potential of the control signal B is "H" or "L", it becomes irrelevant and is determined only by the potential of the control signal A.

Weak pull-up When the control signal A is set to "H" level and B is set to "H" level,
MOS transistor Q ₁₂ , MOS transistor Q ₁₆ are off, MOS
Since the transistors Q ₁₃ , Q ₁₄ , Q ₁₅ , and Q ₁₇ are turned on, if the potential of the signal C is made to be stronger than that of the MOS transistor Q ₁₃ and MOS transistor Q ₁₇ , the MOS transistor Q ₁₄ and
It becomes a value obtained by dividing V _{CC according} to the capacity ratio of the MOS transistor Q ₁₅ , and becomes the intermediate potential M. Actually, the potential of the signal C is determined by the current flowing by the capacity ratio of the MOS transistor Q ₁₄ and the MOS transistor Q ₁₅ , and the current flowing in the MOS transistor Q ₁₁ is the ratio of the current amplification factors β of the MOS transistor Q ₁₄ and the MOS transistor Q _11. Depends on Since the signal C of the intermediate potential to the gate of the MOS transistor Q ₁₁ is supplied, MOS transistor Q ₁₁ although turned on, the resistance of the large passing current becomes weak pull-up state is reduced. This state is shown in FIG. 3 (a), and the state when the gate potential (input signal) of the MOS transistor Q ₂ which is the driver changes in the weak pull-up state is shown in FIG. 3 (b) (c). As shown.

FIG. 3B shows the gate potential of the MOS transistor Q ₂ as L.
→ a case where the changing to H, the MOS transistor Q ₂ is but through current i flows through the MOS transistor Q ₁₁ is turned on, a large resistance of the MOS transistor Q ₁₁ with a weak pull-up state, the value of i Is small.

At this time, the discharge current i _c from the parasitic capacitance C flows to GND through the MOS transistor Q ₂ . In this case, the driving capability of the MOS transistor Q ₂ is the same as that of the conventional one, but since the value of the through current i is small, the change waveform of the bus line 1 quickly changes from “H” to “L” as shown in the figure. However, the time delay τ ₁ is extremely small and the responsiveness can be improved. And
A stable state in which the bus line ₁ shifts to the “L” level is shown in FIG. 3 (c). Although the through current i flows, its value is small, so the power consumption is reduced compared to the conventional case. To do.

Strong pull-up control signal A, when B in the both "H" level, MOS transistor Q _12, MOS transistor Q ₁₃ is but off, the potential of the signal C the MOS transistor Q ₁₅ to Q ₁₇ is turned on "L"
The MOS transistor Q ₁₁ is completely turned on, its resistance is small, the passing current is large, and a strong pull-up state is set. This state is shown in Fig. 3 (d), and MO
When the gate potential of the S transistor Q ₂ is changed from H to L, the MOS transistor Q ₂ is turned off and a large charging current for the parasitic capacitance Ci rapidly flows through the MOS transistor Q ₁₁ to rapidly charge the parasitic capacitance Ci. As a result, the bus line 1 is quickly pulled up as shown by the waveform in the figure, and the time delay τ ₂ thereof can be made much shorter than in the conventional case. The state where the charge-up is completed is shown in FIG.

From the above operations, in the present embodiment, the through current i can be reduced as necessary to reduce the power consumption, and on the other hand, when the rapid charge-up is required, the through current i can be increased to respond. It is possible to improve the sex. This effect can be obtained by providing two MOS transistors Q ₁₁ as shown in FIG. 4, one corresponding to a weak pull-up state and the other corresponding to a strong pull-up state, but this increases the occupied area of the element. Resulting in.

Therefore, in this embodiment, one MOS transistor Q ₁₁ is sufficient as shown in FIGS. 5A and 5B, and instead, the gate potential is set to “L” as shown in FIG. 5A. By doing so, a strong pull-up state is created, and by setting the gate potential to the intermediate potential “M”, a weak pull-up state is created, and as a result, an increase in the occupied area can be prevented.

The above embodiment is an example in which the number of bus lines and pull-up elements is one, but the number of bus lines is not limited to this,
In addition, even if there are many places where pull-ups are performed, the same effect as in the above-described embodiment can be obtained, and if there are many places, the effect becomes more remarkable.

〔The invention's effect〕

According to the present invention, since the pull-up states have different capacities, it is possible to reduce the power consumption and improve the responsiveness while preventing the occupied area from increasing.

[Brief description of drawings]

1 to 5 are diagrams showing an embodiment of a potential control circuit according to the present invention, FIG. 1 is an overall configuration diagram thereof, FIG. 2 is a detailed circuit diagram of the control circuit, and FIG. )-(D) are diagrams for explaining the operation, FIG. 4 is a diagram for explaining the form of the pull-up element, and FIGS. 5 (a) and 5 (b) are diagrams for explaining the operation of the pull-up element. 6 to 9 are diagrams for explaining a conventional potential control circuit, FIG. 6 is an overall configuration diagram thereof, FIGS. 7 (a) and 7 (b) are diagrams for explaining the pull-up element, and FIG. The figure illustrates the driver, and FIGS. 9A to 9D are diagrams illustrating the operation. 1 ...... bus line (line), 3 ...... inverter, 4a to 4n ...... driver, 11 ...... control circuit (control means), Ci ...... parasitic capacitance, Q ₁₁ ...... MOS transistor (pull-up element), Q _{12 to} Q ₁₇ …… MOS transistors.

Claims (1)

(57) [Claims] 1. A number of drivers are connected to a predetermined line,
A potential control circuit that drives one or more of the drivers to pull down the line potential to a low level, and when driving of the driver is stopped, pulls up the line potential to a high level by a pull-up element. And a control means for controlling the gate potential of the MOS transistor, wherein the control means is at least not pulled up,
A potential control circuit configured to supply a potential corresponding to each of a state of performing a weak pull-up and a state of performing a strong pull-up to a gate of the MOS transistor.