JP2550337B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2550337B2 JP2550337B2 JP62049112A JP4911287A JP2550337B2 JP 2550337 B2 JP2550337 B2 JP 2550337B2 JP 62049112 A JP62049112 A JP 62049112A JP 4911287 A JP4911287 A JP 4911287A JP 2550337 B2 JP2550337 B2 JP 2550337B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- wiring
- silicon nitride
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000000034 method Methods 0.000 title description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 238000002161 passivation Methods 0.000 description 9
- 230000002411 adverse Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- -1 hydrogen ions Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005546 reactive sputtering Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001552 radio frequency sputter deposition Methods 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特にAl配線上
に形成するパッシベーション膜の形成方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a passivation film formed on an Al wiring.
従来、半導体装置に使用されるパッシベーション膜と
しては、第２図に示す様に、常圧CVD法により形成され
るシリコン酸化膜（以下CVD酸化膜と記す）４およびプ
ラズマCVD法によるシリコン窒化膜（以下、Ｐ−SiN膜と
記す）５からなる２層構造のものもしくは、CVD酸化膜
又はＰ−SiN膜の単独膜からなる１層構造のものがあ
る。尚、第２図において、１はシリコン基板、２はシリ
コン酸化膜、３はシリコン窒化膜である。Conventionally, as a passivation film used for a semiconductor device, as shown in FIG. 2, a silicon oxide film (hereinafter referred to as a CVD oxide film) 4 formed by an atmospheric pressure CVD method and a silicon nitride film formed by a plasma CVD method ( Hereinafter, there is a two-layer structure consisting of a P-SiN film) 5 or a one-layer structure consisting of a CVD oxide film or a single film of a P-SiN film. In FIG. 2, 1 is a silicon substrate, 2 is a silicon oxide film, and 3 is a silicon nitride film.
しかしながら、上述した従来のパッシベーション膜に
は以下の欠点がある。However, the above-mentioned conventional passivation film has the following drawbacks.
CVD酸化膜１層構造においては、CVD酸化膜形成時の温
度（約350〜400℃）によってAl配線６にAlヒロック８を
発生させる。このヒロック発生部は次のホトレジスト工
程において完全にホトレジストに覆われないため、Alヒ
ロック８上のCVD酸化膜にピンホールを発生させ、耐湿
性を低下させる欠点がある。In the CVD oxide film single layer structure, Al hillocks 8 are generated in the Al wiring 6 by the temperature (about 350 to 400 ° C.) at the time of forming the CVD oxide film. Since this hillock generation portion is not completely covered with the photoresist in the next photoresist process, there is a drawback that pinholes are generated in the CVD oxide film on the Al hillock 8 and the moisture resistance is lowered.
Ｐ−SiN膜１層構造においては、Ｐ−SiN膜形成時の温
度（約250〜350℃）によって発生するAlヒロック８によ
るピンホール発生の欠点および、Ｐ−SiN膜中に混在す
る過剰の水素イオンが、素子特性に悪影響をおよぼす欠
点がある。この対策としては、Al配線６下に低圧CVD法
によるシリコン窒化膜３を設ける方法が一般に用いられ
ている。In the P-SiN film single-layer structure, there is a defect that pinholes are generated by Al hillocks 8 caused by the temperature (about 250 to 350 ° C.) at the time of forming the P-SiN film and excess hydrogen mixed in the P-SiN film. Ions have the disadvantage that they adversely affect the device characteristics. As a countermeasure against this, a method of providing the silicon nitride film 3 by the low pressure CVD method under the Al wiring 6 is generally used.
CVD酸化膜４およびＰ−SiN膜５の２層構造において
は、耐湿性の低下や水素イオンの悪影響は除かれるもの
の、構造が複雑となり、更にパッシベーション膜の膜厚
が厚くなるため、クラックが発生しやすくなり、またAl
ヒロック８によるピンホールの発生が除けない欠点があ
る。In the two-layer structure of the CVD oxide film 4 and the P-SiN film 5, although the deterioration of moisture resistance and the adverse effect of hydrogen ions are eliminated, the structure becomes complicated and the passivation film becomes thicker, so that cracks occur. Easier to do, Al
There is a drawback that the generation of pinholes due to hillocks 8 cannot be excluded.
本発明の目的は、耐湿性に勝れ、素子特性に悪影響を
与えずしかもAlヒロックによるピンホールの発生を防止
することのできるパッシベーション膜を有する半導体装
置の製造方法を提供することにある。An object of the present invention is to provide a method of manufacturing a semiconductor device having a passivation film, which has excellent moisture resistance, does not adversely affect element characteristics, and can prevent generation of pinholes due to Al hillocks.
本発明の半導体装置の製造方法は、半導体基板上に絶
縁膜を介してAl配線を形成する工程と、前記Al配線を含
む全面にスパッタ法により成膜温度200℃以下で厚さ200
0〜5000Åのシリコン窒化膜を形成する工程とを含むも
のである。A method for manufacturing a semiconductor device of the present invention comprises a step of forming an Al wiring on a semiconductor substrate via an insulating film, and a film formation temperature of 200 ° C. or less by a sputtering method over the entire surface including the Al wiring to a thickness of 200.
And a step of forming a silicon nitride film of 0 to 5000 Å.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を説明するための半導体チ
ップの断面図である。FIG. 1 is a sectional view of a semiconductor chip for explaining one embodiment of the present invention.
第１図において、素子形成のための拡散工程等が終了
したシリコン基板１上に、シリコン酸化膜２を介してAl
配線６を電子ビーム蒸着法およびフォトリソグラフィ技
術で形成する。次でAl配線６とシリコンのコンタクトを
とるための400〜460℃の熱処理前に、SiのN2による反応
性スパッタ法によって厚さ2000〜5000Åのシリコン窒化
膜７を形成する。In FIG. 1, Al is formed on the silicon substrate 1 on which the diffusion process for forming elements has been completed with the silicon oxide film 2 interposed therebetween.
The wiring 6 is formed by the electron beam evaporation method and the photolithography technique. Next, before the heat treatment at 400 to 460 ° C. for making contact with the Al wiring 6 and silicon, a silicon nitride film 7 having a thickness of 2000 to 5000 Å is formed by a reactive sputtering method using N 2 of Si.
このスパッタ法で形成されるシリコン窒化膜７は、膜
形成時の温度が200℃以下と、他のパッシベーション膜
の形成時の温度（300〜400℃）に比較して低温であるた
め、Alヒロックの高さは、他のパッシベーション膜では
5000Å以上であるのに対し、1000Å以下となる。このた
めAlヒロックによりパッシベーション膜に形成されるピ
ンホールを防止することができる。また、シリコン窒化
膜７はN2のスパッタリングにより形成されることによ
り、膜中に素子に悪影響を与える過剰な水素イオンを含
んでいないため、特にその対策は必要ではない。Since the silicon nitride film 7 formed by this sputtering method has a temperature of 200 ° C. or lower during film formation, which is lower than the temperature (300 to 400 ° C.) during formation of other passivation films, Al hillock The height of other passivation films
While it is over 5000Å, it is under 1000Å. Therefore, pinholes formed in the passivation film due to Al hillocks can be prevented. Further, since the silicon nitride film 7 is formed by N 2 sputtering and does not contain excessive hydrogen ions which adversely affect the element in the film, no particular countermeasure is required.
尚、上記実施例においてはシリコン窒化膜７を反応性
スパッタ法で形成した場合について説明したが、RFスパ
ッタ法を用いることもできる。Although the case where the silicon nitride film 7 is formed by the reactive sputtering method has been described in the above embodiment, the RF sputtering method can also be used.
以上説明したように本発明は、Al配線上にスパッタ法
でシリコン窒化膜を形成することにより、耐湿性に勝
れ、素子特性に悪影響を与えず、しかもAlヒロックによ
るピンホールの発生を防止できるパッシベーション膜を
有する半導体装置が得られるという効果がある。As described above, according to the present invention, by forming the silicon nitride film on the Al wiring by the sputtering method, the moisture resistance is excellent, the device characteristics are not adversely affected, and the generation of pinholes due to Al hillocks can be prevented. There is an effect that a semiconductor device having a passivation film can be obtained.
第１図は本発明の一実施例を説明するための半導体チッ
プの断面図、第２図は従来の半導体装置の断面図であ
る。 １……シリコン基板、２……シリコン酸化膜、３……シ
リコン窒化膜、４……CVD酸化膜、５……Ｐ−SiN膜、６
……Al配線、７……シリコン窒化膜、８……Alヒロッ
ク。FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional semiconductor device. 1 ... Silicon substrate, 2 ... Silicon oxide film, 3 ... Silicon nitride film, 4 ... CVD oxide film, 5 ... P-SiN film, 6
...... Al wiring, 7 ... silicon nitride film, 8 ... Al hillock.
フロントページの続き (56)参考文献 特開 昭58−206166（ＪＰ，Ａ) 特開 昭60−103625（ＪＰ，Ａ) 特開 昭60−249333（ＪＰ，Ａ) 特開 昭61−154171（ＪＰ，Ａ) 特開 昭62−137855（ＪＰ，Ａ) 特開 昭62−166530（ＪＰ，Ａ)Continuation of front page (56) Reference JP-A-58-206166 (JP, A) JP-A-60-103625 (JP, A) JP-A-60-249333 (JP, A) JP-A-61-154171 (JP , A) JP-A-62-137855 (JP, A) JP-A-62-166530 (JP, A)
Claims (1)
成する工程と、前記Al配線を含む全面にスパッタ法によ
り成膜温度200℃以下で厚さ2000〜5000Åのシリコン窒
化膜を形成する工程とを含むことを特徴とする半導体装
置の製造方法。1. A step of forming an Al wiring on a semiconductor substrate via an insulating film, and a silicon nitride film having a thickness of 2000 to 5000 Å at a film forming temperature of 200 ° C. or less by a sputtering method on the entire surface including the Al wiring. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62049112A JP2550337B2 (en) | 1987-03-03 | 1987-03-03 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62049112A JP2550337B2 (en) | 1987-03-03 | 1987-03-03 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63213934A JPS63213934A (en) | 1988-09-06 |
| JP2550337B2 true JP2550337B2 (en) | 1996-11-06 |
Family
ID=12821985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62049112A Expired - Fee Related JP2550337B2 (en) | 1987-03-03 | 1987-03-03 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2550337B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02103936A (en) * | 1988-10-13 | 1990-04-17 | Mitsubishi Electric Corp | Semiconductor device |
| JP2859288B2 (en) * | 1989-03-20 | 1999-02-17 | 株式会社日立製作所 | Semiconductor integrated circuit device and method of manufacturing the same |
| JP3177436B2 (en) * | 1996-03-21 | 2001-06-18 | 株式会社日立製作所 | Semiconductor integrated circuit device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58206166A (en) * | 1982-05-26 | 1983-12-01 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor element |
| JPS60103625A (en) * | 1983-11-11 | 1985-06-07 | Nec Corp | Semiconductor device |
| JPH0614523B2 (en) * | 1984-05-25 | 1994-02-23 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| JPS61154171A (en) * | 1984-12-27 | 1986-07-12 | Toshiba Corp | Insulated gate type field effect semiconductor device |
| JPS62137855A (en) * | 1985-12-12 | 1987-06-20 | Sumitomo Electric Ind Ltd | Semiconductor device with multilayer wiring structure |
| JPS62166530A (en) * | 1986-01-20 | 1987-07-23 | Toshiba Corp | Manufacture of semiconductor device |
-
1987
- 1987-03-03 JP JP62049112A patent/JP2550337B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63213934A (en) | 1988-09-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |