JP2551331B2 - Memory circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit, and more particularly to an N word.times.M bit (N, M is a positive integer) FIFO.
The present invention relates to a memory circuit in which two or more (first-in first-out) memories are arranged in parallel to form a FIFO having (M + 1) bits or more and used.

[0002]

2. Description of the Related Art Conventionally, in this type of memory circuit,
As shown in FIG. 4, the memory cells 50 of the FIFOs 5 and 6,
The write counters 51 and 61 and the read counters 52 and 62 for controlling the writing and reading of the respective 60 are reset by reset pulses from the counters 7 and 8, respectively. As a result, the write counters 51 and 61 are synchronized with each other, and the read counters 52 and 62 are synchronized with each other.

In FIG. 4, the memory circuit uses 4 words × 4 bits × 8 bits FIFOs 5 and 6 to form 4 words × 16 bits.
It constitutes a bit FIFO. The FIFOs 5 and 6 are 4 words each composed of memory cells 50 and 60, write counters 51 and 61, and read counters 52 and 62.
It is an 8-bit memory.

Each 8-bit data signal (MSB1 to L
SB1, MSB2 to LSB2) are input, the FIF
O5 and 6 are 8 by a 4-phase clock obtained by dividing the write clock (W CLK) by the write counters 51 and 61, respectively.
The bit parallel signal is transferred to the memory cells 50, 6 of 4 words.
Write to 0 periodically.

8 written in the memory cells 50 and 60, respectively
Bit parallel signal is read clock (R CLK)
Is read by a four-phase clock divided by the read counters 52 and 62, and an 8-bit data signal (MSB1 to L
SB1, MSB2 to LSB2) are output.

Further, the counter 7 inputs a write clock, divides the write clock by 4 or divides it by an integer multiple of 4, and outputs a reset pulse to the write counters 51 and 61 to synchronize these two counters. .

Further, the counter 8 inputs a read clock, divides the read clock by 4 or an integer multiple of 4, and outputs a reset pulse to the read counters 52 and 62 to synchronize these two counters. .

As described above, by simultaneously resetting the write counters 51 and 61 and the read counters 52 and 62 of the two FIFOs 5 and 6, respectively, the writing and reading of the 8-bit data signal to the FIFOs 5 and 6 are synchronized. There is.

[0009]

In the above-mentioned conventional memory circuit, the write counter and the read counter of each of the two FIFOs are simply reset at the same time in order to synchronize the two FIFOs. It cannot be confirmed from outside the FIFO (LSI) whether or not they are synchronized.

Therefore, an object of the present invention is to solve the above problems and to provide a memory circuit capable of confirming the actual synchronization from the outside of the FIFO.

[0011]

In a memory circuit according to the present invention, first and second FIFOs in which a common delay time confirmation signal for specifying the write data is written in 1 bit of each write data. memory and, comparing means for comparing the delay time confirmation signal read from the first and second FIFO memories, the read clock to the second FIFO memory for each mismatch is discovered by the comparing means A means for suppressing the supply for one clock ,
Each time the comparing means detects a mismatch, the second FIFO
The supply of the read clock to the memory is performed by the suppressing means.
By suppressing one clock, the first and second FIFOs
It is configured to synchronize the memory .

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Referring to the figure, a memory circuit according to an embodiment of the present invention includes two 4 word × 9 bit FIFOs 1 and 2.
Is used to form a 4-word × 16-bit FIFO.

FIFOs 1 and 2 are memory cells 10 and 2, respectively.
0, write counters 11 and 21, read counters 12,
It is a memory of 4 words × 9 bits composed of 22 and 22. 8-bit data signals (MSB1 to LSB1, MSB2 to L are included in 8 bits out of 9 bits of the FIFOs 1 and 2).
SB2) is input, and the delay time confirmation signal (CHK in) is input to the remaining 1 bit.

The above-mentioned 9-bit parallel signals are respectively supplied with a write clock (W CLK) and write counters 11 and 21.
The four-phase clock divided by 4 is periodically written in the memory cells 10 and 20 of 4 words.

The 9-bit parallel signal written in the memory cells 10 and 20 is read by a 4-phase clock obtained by dividing the read clock (R CLK) by the read counters 12 and 22.

Of the 9-bit parallel signals, 8 bits are data signals (MSB1 to LSB1, MSB2 to LS).
B2), and 1 bit is output to the comparison circuit 3 as a delay time confirmation signal (CHK 1 out, CHK 2 out).

The comparison circuit 3 compares the delay time confirmation signals output from the FIFOs 1 and 2 and outputs the comparison result to an inhibition circuit (INH: Inhibit) 4. The inhibition circuit 4 inhibits the supply of the read clock to the read counter 22 of the FIFO 2 and stops the frequency dividing operation of the read counter 22.

FIG. 2 is a block diagram showing a configuration example of the comparison circuit 3 and the inhibition circuit 4 of FIG. In the figure, the comparison circuit 3 is composed of an inverting circuit 31 and a 2-input OR gate 32, and the inhibition circuit 4 is composed of an AND circuit 41.

The inverting circuit 31 inverts the delay time confirmation signal (CHK2 out) read from the memory cell 20 and outputs it to the 2-input OR gate 32. The 2-input OR gate 32 ORs the delay time confirmation signal (CHK 1 out) read from the memory cell 10 and the delay time confirmation signal from the memory cell 20 inverted by the inverting circuit 31 and compares the results. Suppression circuit 4 as a result (COMP)
Output to.

In the inhibition circuit 4, the AND circuit 41 ANDs the comparison result of the comparison circuit 3 and the read clock (RCLK in), and the result is read clock (R CLK in).
2) is output to the read counter 22.

FIG. 3 is a time chart showing the operation of one embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS. Here, the delay time confirmation signal (CHK in) is a repetitive signal having a cycle of the word number 4 of the memory cells 10 and 20, as shown in FIG. That is, 1 bit of the delay time confirmation signal is "L".
The remaining 3 bits are a 4-bit repetitive signal of "H".

Now, assuming that the delay time confirmation signal is read from the FIFO1 with a 2-bit delay and the delay time confirmation signal is read from the FIFO2 with a 4-bit delay, the delay time confirmation signal from the FIFO1 is The delay time confirmation signal from the FIFO 2 is shifted by 2 bits at the position of the read clock (4).

In this case, the comparison result of the comparison circuit 3 (COM
Since P) becomes "L" at the position of the read clock (4), the read clock (R CL to the read counter 22
The supply of K2) is suppressed by the suppression circuit 4. Therefore, the read clock to the read counter 22 is missing one bit.

When the read clock to the read counter 22 is missing one bit, the read counter 22 of the FIFO 2 is stopped for one clock, so that the delay time confirmation signal from the FIFO 2 becomes "L" next time. It is the position of the read clock (7) after 5 bits.

On the other hand, since the delay time confirmation signal from the FIFO1 becomes "L" at the position of the read clock (8),
The delay time confirmation signal from the FIFO1 and the delay time confirmation signal from the FIFO2 are shifted by 1 bit at the position of the read clock (8).

For this reason, the comparison result of the comparison circuit 3 becomes "L" again at the position of the read clock (8), so that the read clock to the read counter 22 is missing one bit again.

When the read clock to the read counter 22 is missing one bit again, the read counter 22 of the FIFO2 is stopped for one clock, so that the delay time confirmation signal from the FIFO2 becomes "L" next. Is the position of the read clock (12) after 5 bits.

On the other hand, since the delay time confirmation signal from the FIFO1 becomes "L" at the position of the read clock (12), the delay time confirmation signal from the FIFO1 and the FIFO2.
Signal for delay time confirmation from the read clock (12)
There is 0 bit shift at the position.

Therefore, the comparison result of the comparison circuit 3 becomes "H" at the position of the read clock (12), so that the FIFO.
It can be seen that 1 and 2 are synchronized. That is, it can be confirmed from the outside of the FIFOs 1 and 2 that they are actually synchronized. Here, the above-mentioned processing is performed at the time of starting up or resetting the device in which the data read from the FIFOs 1 and 2 is deviated.

In this way, the comparator circuit 3 constantly monitors the time shift when the delay time confirmation signal passes through the two FIFOs 1 and 2, and when the time shift is detected, the inhibition circuit 4 is used. FIFO by suppressing supply of read clock
By stopping the frequency division operation of the read counter 22 of No. 2, the FIFO 1 and 2 (L
It can be confirmed from outside SI).

In the embodiment of the present invention, two FIFOs are used.
Although the case where 1 and 2 are used is described, two or more FIs are used.
Obviously, it is also applicable when using FO. Further, the logic elements of the comparison circuit 3 and the inhibition circuit 4 can be replaced with other logic elements, and the invention is not limited to these.

[0033]

As described above, according to the present invention, the first and second FIFOs in which a common delay time confirmation signal for specifying the write data is written in 1 bit of each write data. The delay time confirmation signal read from the memory is compared, and when a mismatch is detected in this comparison, the supply of the read clock to the second FIFO memory is suppressed, and the frequency dividing operation for dividing the read clock is performed. By stopping the operation, it is possible to confirm that the synchronization is actually performed from the outside of the first and second FIFO memories.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a comparison circuit and a suppression circuit of FIG.

FIG. 3 is a time chart showing the operation of the embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1, 2 FIFO 3 Comparator circuit 4 Suppression circuit 10, 20 Memory cell 11, 21 Write counter 12, 22 Read counter 31 Inversion circuit 32 2 Input OR gate 41 AND circuit

Claims (2)

(57) [Claims] 1. A first and second FIFO memory in which a common delay time confirmation signal for specifying the write data is written in one bit of each write data, and the first and second FIFO memories. Yes comparing means for comparing the delay time confirmation signal read from the memory, and inhibition means for mismatch is one clock inhibit the supply of the read clock to the second FIFO memory for each Ru is detected by the comparing means However, each time the comparing means detects a mismatch, the second
Of the read clock supply to the FIFO memory of the above
By suppressing one clock by means, the first and second
A memory circuit configured to synchronize the FIFO memories of the above . 2. The second FIFO memory has a frequency dividing means for dividing the read clock and stopping the dividing operation by one clock by suppressing the supply of the read clock. The described memory circuit.