JP2551387B2 - Square root circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a square root circuit, and more particularly to a square root circuit composed of an operational amplifier and a square law circuit.

[0002]

2. Description of the Related Art Conventionally, a square root circuit of this type is, for example,
It is a square law circuit that is formed on a semiconductor integrated circuit and includes a transistor circuit that operates in a saturation region.

The square root circuit of this type needs to have a wide input voltage range because the transistors forming the square law circuit operate in the saturation region.

FIG. 4 is a circuit diagram showing a conventional square root circuit.

In the figure, the square root circuit has an input voltage V _I
An input terminal 10 for supplying the one end connected to the input terminal 10, the other end, and a resistor R _S connected to the negative terminal of the operational amplifier 2. One end of the resistor R ₁ is grounded, the other end is connected to the positive terminal of the operational amplifier, and the resistor R ₂ is connected to the output terminal of the operational amplifier 2. The MOS transistor M5 constitutes a square law circuit, the gate terminal thereof is grounded, the drain terminal thereof is connected to the resistor R _S , and the source terminal thereof is connected to the other end of the resistor R ₂ . The diode D ₁ has a positive terminal connected to the resistor R ₂ and a negative terminal connected to the drain terminal of the MOS transistor M5. Further, the resistor R ₂ is connected to the output terminal 11.

Next, the operation will be described.

The drain current I _D5 of the MOS transistor M5 operating in the saturation region is given by the following equation, where V _GS is the gate-source voltage and V _TH is the threshold voltage, ignoring channel length modulation and the substrate effect. _D = β (V _GS −V _TH ) ² (V _GS ≧ V _TH ) (1) I _D = 0 (V _GS ≦ V _TH ) (2)

Β is a transconductance parameter, where μ is the effective mobility of carriers, C _OX is the gate oxide film capacity per unit volume, and W and L are the gate width and gate length, respectively, β = μ It can be represented by (C _OX / 2) (W / L) (3).

The input current I _I is input to the negative terminal of the operational amplifier 2, and the output current of the operational amplifier 2 has a value obtained by taking the square root of the input current due to the feedback action of the operational amplifier 2. Since the input current I _I is equal to the drain current I _D5 , the output current of the operational amplifier is the square root of the drain current.

That is, by taking the square root of both sides of the equation (3) showing the drain current, the output current I _O can be obtained. Further, by rearranging the equation and obtaining the gate-source voltage, V _GS = ( I _D / β) ^1/2 + V _TH (4)

The output voltage V _O appearing at the output terminal is MO
Since the gate terminal of the S-transistor M5 is grounded, it is equal to the inversion value of the gate-source voltage and V _O = −V _GS (5).

Therefore, by substituting the equation (5) into the equation (4) and obtaining the output voltage V _O , it becomes V _O = − ( _ID / β) ^1/2 −V _TH (6) and the drain current I _The output voltage V _O has a square root characteristic with respect to _D , that is, the input current I _I.

[0013]

However, since the output voltage depends on the threshold voltage of the MOS transistor, this conventional square root circuit has a problem of variations in temperature characteristics and manufacturing characteristics.

An object of the present invention is to solve the above problems and to provide a square root circuit whose output voltage does not depend on the threshold voltage of a MOS transistor.

[0015]

In order to achieve the above-mentioned object, a square root circuit according to the present invention comprises a feedback path of an operational amplifier and a square law circuit, and the square law circuit constitutes a differential pair circuit. Of the first and second transistors,
It is composed of a differential pair circuit driven by a sum current of a current equal to the drain current of the first transistor and a constant current.

[0016]

The present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of a square root circuit showing an embodiment of the present invention.

In the figure, the square root circuit according to the invention is
A differential pair circuit composed of MOS transistors M1 and M2 and a source terminal of the MOS transistor M2 are connected,
It is composed of a square law circuit composed of a constant current source 5 whose other end is grounded, and current mirror circuits 3 and 4 connected to the drain terminal and the source terminal of the MOS transistor M2, respectively. . The input voltage V _I is input from the input terminal 1 of the square root circuit, and the input terminal 1 is
The resistor R _S is connected. The negative terminal of the operational amplifier 2 is connected to the other end of the resistor R _{S and} the other end of the current mirror circuit 3. The positive terminal of the operational amplifier 2 is connected to the power source 6 and is connected to M
It is connected to the gate terminal of the OS transistor M2.
Further, the output terminal of the operational amplifier 2 is connected to the gate terminal of the MOS transistor M1 and also to the output terminal 6 of the square root circuit to output the output voltage V _O.

The differential pair circuit forming the square law circuit is MO
It is driven by the sum current of the drain current I _D1 of the S transistor M1 and the constant current I ₀ output from the constant current source circuit 5.

Next, the operation will be described.

Generally, a MOS driven by a tail current I _SS
The output current ΔI _D of the differential pair circuit composed of transistors is
If the element matching and the substrate effect are ignored, the relationship between the drain current _ID of the MOS transistor forming the differential pair circuit operating in the saturation region and the gate-source voltage V _GS is
(1) Since according to the square characteristics shown in _{equation, ΔI D = βV I (2I} SS / β 1/2 -V i 2) 1/2 , _{however, (| V i | ≦ (} I SS / β) 1/2 ) (7) Note that V _i is a differential input voltage of the differential pair circuit composed of the MOS transistors M1 and M2.

Here, in the square root circuit of FIG. 1, assuming that the drain currents of the MOS transistors M1 and M2 are I _D1 and I _D2 , the output current ΔI _{D of} the differential pair circuit composed of the MOS transistors M1 and M2, and, the tail current I _SS for driving the differential pair circuit is a _{ΔI D = I D1 -I D2 =} I D1 -I 0 (8) I SS = I D1 + I 0 (9).

Therefore, by substituting the equations (8) and (9) into the equation (7), the output current ΔI _D of the differential pair circuit of the square root circuit of FIG. 1 is obtained, and the equations are rearranged. When the drain current I _D1 of the MOS transistor M1 is obtained, I _D1 = β {V _i + (I ₀ / β) ^1/2 } ² (V _i ≧ − (I ₀ / β) ^1/2 ) (10) I _D1 = 0 - a _{(V i ≧ (I 0 /} β) 1/2) (11).

The input current I _I from the input terminal 1 is input to the negative electrode of the operational amplifier 2 and by the feedback action of the operational amplifier,
The output current I ₀ is a value obtained by taking the square root of the input current. The input current I _I is the same as the MOS transistor M1.
For equal drain currents I _D1, the output current I _o of the operational amplifier, the drain current I _{D 1} of the MOS transistor M1
The square root of is taken.

That is, by taking the square root of both sides of the equation (10) showing the drain current of the MOS transistor M1, I _o = I _D ^1/2 = β ^1/2 {V _i + (I ₀ / β) ^{1 / 2} } (12)

Therefore, the drain current I _D1 of the MOS transistor M1 has a square root characteristic with respect to the differential input voltage V _i of the differential pair circuit.

FIG. 2 is a circuit diagram of a square law circuit showing another embodiment of the present invention. That is, it is another embodiment of the square law circuit, which constitutes the square root circuit shown in FIG. 1, and which includes a differential pair circuit including MOS transistors M1 and M2, a constant current source circuit, and a current mirror circuit.

In the figure, MOS transistors M3 and M4 form the current mirror circuit 3 of FIG.
The S transistors M5 and M6 form the current mirror circuit 4 of FIG. Further, the gate terminal of the MOS transistor M1 is connected to the positive terminal of the operational amplifier 2 of FIG. 1, and the gate terminal of the MOS transistor M2 is connected to the output terminal of the operational amplifier of FIG. MOS
The transistors M8 and M9 form a differential pair circuit 8, and the differential pair circuit 8 and the constant current source circuit 9 form the constant current source circuit 5 of FIG. That is, the constant current source 5 of FIG. 2 applies a dynamic bias to the MOS transistor M1, and the constant current I ₀ of FIG. 2 corresponds to the constant current I ₀ of FIG.

Therefore, the square law circuit of FIG. 2 is one MO of the differential pair circuit to which the dynamic bias technique is applied.
The drain current of the S transistor M1 has a squared characteristic.

In the square law circuit of FIG. 2, the relational expression between the gate voltage and the drain current of a MOS transistor is calculated by using the gate-source voltage as a differential input V _i , and the threshold voltage V _TH as V _TH = (I _O / Β) ^1/2 (13) and all can be represented by only electrically programmable parameters.

That is, since the drain current I _D1 of the MOS transistor M1 having the square characteristic does not depend on the threshold voltage V _TH , it is possible to solve the problem of variations in temperature characteristics and manufacturing characteristics.

When the square law circuit shown in FIG. 2 is applied to the square law circuit of FIG. 1, the output of the square root circuit of FIG. 1 is V _O = (V _I / R _S β) ^1/2 − (I ₀ / Β) ^1/2 (14), and the square root characteristic can be obtained.

From equation (14), it can be seen that the input / output characteristics of the square root circuit of FIG. 1 do not depend on the threshold voltage V _TH .

Since the transconductance parameter β is proportional to −3/2 of the absolute temperature T and has a constant temperature dependence, the square root circuit of FIG. 1 can easily perform temperature compensation.

FIG. 3 shows the differential input voltage V _{i of the} square law circuit shown in FIG. 2 and the drain current I of the MOS transistor M1.
FIG. 6 is an electrical characteristic diagram showing the relationship of _D1 .

In the figure, for the differential input voltage V _i , M
It can be seen that the drain current I _D1 of the OS transistor M1 exhibits a squared characteristic.

[0037]

As described above, in the square root circuit according to the present invention, the output voltage does not depend on the threshold voltage and the square law circuit inserted in the feedback path of the operational amplifier can be electrically programmed. Therefore, it is possible to solve the problem of variations in temperature characteristics and manufacturing characteristics of the square root circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a square root circuit showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of a square law circuit forming a square root circuit according to another embodiment of the present invention.

FIG. 3 is an electrical characteristic diagram of the square law circuit shown in FIG.

FIG. 4 is a circuit diagram of a conventional square root circuit.

[Explanation of symbols]

1 ... Input terminal 2 ... Operational amplifier 3, 4 ... Current mirror circuit 5, 9 ... Constant current source circuit 6 ... Output terminal 7 ... Operational amplifier negative terminal 8 ... Differential Pair circuit 10 ・ ・ ・ Input terminal 11 ・ ・ ・ Output terminal M1 to M9 ・ ・ ・ MOS transistors R _S , R ₁ , R ₂・ ・ ・ Resistor D ₁ diode VDD ・ ・ ・ Power supply line

Claims (5)

(57) [Claims] 1. A square root circuit composed of a feedback path of an operational amplifier and a square law circuit, wherein the square law circuit is a first transistor of the first and second transistors forming a differential pair circuit. A square root circuit characterized by comprising a differential pair circuit driven by a sum current of a current equal to the drain current of a constant current and a constant current. 2. The first and second transistors are MO
The square root circuit according to claim 1, wherein the square root circuit is an S transistor. 3. The square root circuit according to claim 2, wherein first and second current mirror circuits are connected to a source terminal and a drain terminal of the first transistor. 4. The square root circuit according to claim 2, wherein a first constant current source circuit is connected to a source terminal of the second transistor. 5. A third current mirror circuit is connected to a source terminal of the second transistor, a second constant current source circuit is connected to a drain terminal of the second transistor, and the third current mirror circuit is connected. The square root circuit according to claim 2, wherein a drain terminal of a third transistor forming the circuit is connected to the second constant current source circuit.