JP2551391B2 - Exposure apparatus and exposure method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure method in a photolithography process during a semiconductor device manufacturing process, and more particularly, it divides a circuit pattern region formed on a semiconductor wafer into a plurality of partial regions and corresponds to each partial region. The present invention relates to a so-called screen combining (or screen joining) exposure method in which a new circuit pattern portion is exposed by overlapping.

[0002]

2. Description of the Related Art In recent years, in a photolithography process, a reduced (or equal size) projection type exposure apparatus has been widely used as an apparatus for exposing a reticle pattern onto a wafer. This type of apparatus exposes a reticle pattern onto a resist-coated wafer through a projection lens. However, since the area that can be projected by one exposure is smaller than the entire surface of the wafer, the step-and-repeat method is usually adopted in which the wafer is stepped at a constant pitch and then exposed.

In the projection lens in such an apparatus, the minimum line width that can be resolved is determined by the wavelength of illumination light for exposure, the numerical aperture (NA) of the projection lens, and the like. The shorter the wavelength of the illumination light, the higher the resolution, and the larger the numerical aperture, the higher the resolution.
However, both of them have practical limitations. There 1
One way of thinking is to reduce the area that can be projected and exposed to increase the projection magnification (reduction rate) to increase the resolution. This ensures a large projection area and a larger N.V. A. This is because it is difficult to design and manufacture the projection lens of.

For example, if the projection area is reduced by 1/10, the projection area is 10 mm ×
10 mm, N. A. When a resolution of 1 μm can be achieved over the entire projection area by using a projection lens with an aperture of 0.35, this lens is A. Designed to increase only the resolution to increase resolution,
Manufacturing is extremely difficult. However, the projection area is narrowed down to, for example, 5 mm × 5 mm, and N. A. Increasing the size is relatively easy to design and manufacture. In this case, N. A. Can be set to 0.5, and with such a projection lens, a submicron resolution can be stably obtained over the entire surface (5 mm × 5 mm) in the projection area. According to the experiment, a resolution of about 0.8 μm is obtained on the entire surface, and a resolution of up to 0.6 μm is obtained under the best conditions. Of course, the illumination wavelength is the same as before.
It is a line (436 nm). The fact that a submicron resolution is stably obtained in this manner was not expected when a reduction projection exposure apparatus, a so-called stepper, began to be used in a production line in earnest.

By the way, a projection lens with such a high resolution is
Even if obtained, because of its small projected area,
Circuit pattern to be built on the c (for one chip as a product
The size of the corresponding pattern) is limited. So
In order to eliminate this limitation, we will use screen synthesis or screen splicing.
A method of exposing is considered. Figure 2 (a) is for screen composition
FIG. 4 is a perspective view showing an example of an exposure method according to
Each of the circuit pattern portions A ', B', C ', D'of
4 reticle R made₁, R₂, R₃, R _Fouruse
I shall. One chip on the exposed wafer W
Circuit pattern area (hereinafter referred to as the chip area)
DC) Matrix line across the scribe line
Shall be formed in. One chip area DC is shown in FIG.
It is divided into four as shown in FIG.
Each of B, C and D is a reticle R₁~ R_FourEach pattern area
It corresponds to each of the areas A ', B', C ', D'. Chi
Areas A, B, C, D in the area DC are connected to each other.
Is patterned so as to be electrically connected at the section CL
There is. The joint CL is, for example, a wiring made of aluminum.
Formed when making layers.

Now, as shown in FIG. 2A, for example,
Chickle R₂The pattern area B'of the field of view of the projection lens PL
Set at a predetermined position inside, and step and repeat method
Wafer W with arrow e₂Move in X and Y direction like
The reticle for area B in each chip area DC.
R₂Exposure is performed by aligning with (pattern B ′).
After the pattern B ′ is exposed on the entire surface of the wafer W, the arrow e₁
Reticle R ₂R₃(Pattern C ')
Replace. And similarly, the step-and-repeat method
Area C in each chip area DC of the wafer W sequentially
Reticle R₃Align with (pattern C ') and expose
To do. Similarly, reticle R₁(Pattern A '), ret
Curu R_Four(Pattern D ') is exposed and one wafer
The exposure process for W is completed.

[0007]

The exposure by the screen synthesis (or screen joining) is an application of the characteristics of the conventional step-and-repeat method as it is, but the difference from the conventional method is that the exposure is performed once on the wafer. That is, it is necessary to control the alignment of the pattern image printed in step 1 and the pattern image adjacent to it in the X and Y directions very strictly. This is because if an alignment error occurs in the joint CL, a defect such as a disconnection of wiring will eventually occur in all of the joint CL, and it will be almost impossible to repair the chip region DC. is there.

Therefore, in order to accurately align (position) the pattern image of the reticle and the exposed region on the wafer, the alignment marks formed on the reticle and the wafer are directly selected from the conventionally known alignment methods. Die-by-die (hereinafter referred to as D / D) of a TTR (through-the-reticle) or TTL (through-the-lens) method that detects and finely moves one of the reticle and the wafer so as to eliminate the positional deviation between the marks. It is possible to adopt the alignment method. This TTR / D / D alignment method is the projection of marks provided around the reticle circuit pattern area (on the scribe line, etc.) and marks provided around the corresponding area on the wafer (on the scribe line, etc.). It is a method of observing or automatically detecting the superimposition with the back projection image on the reticle side by the lens, and performing the exposure immediately when the desired superposition state is achieved. The advantage of this method is that the relative position itself between the reticle and the wafer when the alignment is achieved is the exposure position. In an exposure apparatus capable of such an alignment method, an alignment microscope or an alignment optical system for the above-mentioned alignment is arranged above a reticle. Usually, the arrangement is determined in a few places around the circuit pattern area of the reticle, and in the case of two locations, TTR / D / D alignment is performed by simultaneously detecting the two areas sandwiching the pattern area. .

However, when considering the screen composition as shown in FIG. 2B, there is a problem in the alignment mark arrangement or the alignment optical system arrangement due to the TTR / D / D alignment method. That is, in the reticles R ₁ , R ₂ , R ₃ , and R ₄ shown in FIG. 2A, the portions where alignment marks cannot be arranged are different from each other. For example, no mark can be provided on the left side and the lower side in the figure for the area A in the chip area DC, and no mark can be provided on the right side and the upper side in the figure for the area C. This means that the same exposure apparatus arrangement of the alignment optical system is predetermined and can not be used in common and the reticle R ₂ with 'reticle R ₁ and pattern C with' pattern A, that can not be D / D Alignment I will end up. Therefore, although not a conventional technique, it is conceivable to arrange a plurality of sets of alignment optical systems, each of which may be originally two, on each side, and to switch and use as needed. However, in this case, the number of alignment optical systems becomes too large, and the configuration of the apparatus, particularly the way of assembling the optical path of the alignment optical system, becomes complicated, and the stability of the system will be a problem. Further, since the marks are arranged differently according to the area within the chip area DC, the relative positional error of the marks when forming the marks will directly affect the splicing accuracy of the areas A, B, C and D.

The above problem can be solved if a prohibited area of the wiring pattern is set in the joint CL and the alignment mark is formed there. Normally, the prohibited area is 50 μm × 100 μm or more depending on the mark shape. However, if the marks are to be transferred, the area will be increased by the number of times. This is joint C
This is not preferable because it imposes a large limit on the design of L, and thus the internal circuit pattern.

Further, in the exposure sequence based on the alignment in which the overlay accuracy is emphasized as in the conventional art, the alignment is completely independent (for example, TTL / D / D alignment) in each of the areas A, B, C and D in the chip area DC. However, it is not always the optimum alignment and exposure sequence in view of the splicing accuracy.

[0012]

In [SUMMARY OF] The present invention, a plurality of masks (R ₁ ~R ₄₎ of the pattern (a'-d ') respectively the projection optical system (PL) substrate photosensitive via the (W) A mask stage (RS) for placing at least one of a plurality of masks and selectively positioning it with respect to a projection optical system in an exposure apparatus that splices each other and exposes them in an overlapping manner, and the positioned mask First position detecting means (12) for detecting the position of the photosensitive substrate and a predetermined area (SA _{1 to} SD ₁ , SA ₂ to SA ₂
The substrate stage (2) for positioning SD ₂ ) with respect to the projection optical system, the second position detecting means (14, 16) for detecting the position of a predetermined area, and the position of the predetermined area on the photosensitive substrate. Based on the control means (20) for determining the position (AMa, AMb) to be detected according to
Selection means (21) for selecting a sequence of detecting the position of the mask and the position of a predetermined region by the first and second position detecting means depending on whether the accuracy of joining is emphasized or the accuracy of overlapping is emphasized. The mask stage and the substrate stage are positioned based on the position of the mask detected according to the selection of the selection unit and the position of the predetermined area.

Further, the first mask (R ₁ ) of the plurality of masks (R _{1 to} R ₄ ) is positioned to form the image (A) of the pattern of the first mask on the photosensitive substrate in the first region. (S
A ₁ ), the second mask (R ₂ ) of the plurality of masks is positioned instead of the first mask, and the image (B) of the pattern of the second mask is formed on the photosensitive substrate (W). Second area (SB ₁ ) having a predetermined positional relationship with the first area of
Exposure method in which the patterns on the plurality of masks are spliced to each other on the photosensitive substrate in a predetermined positional relationship and the image of the pattern is further overlapped on each of the first and second regions. In the step of selecting at least one of placing importance on splicing precision and placing precision on superimposing precision, and selecting the image of the splicing pattern or the image of the superposing pattern depending on the selection result. Positioning with respect to one of the areas.

Further, the selection is to select a positioning sequence. Further, in the positioning sequence, when importance is attached to the joining accuracy, the position of the center point (Ca ₁ ) of the first region is obtained, and the position of the center point is set to the first position.
Is determined as the position (SA ₂ ) of the image of the pattern to be overlapped with the area, and the position (Cb ₂ ) separated from the center point by the designed distance between the first area and the second area is determined as the second position. It is determined as the position (SB ₂ ) of the image of the pattern to be superimposed on the area, and when importance is attached to the superimposition, the position (Ca ₁ ) of the first area is obtained and the position of this first area is determined as the first position. Position of the image of the pattern to be superimposed on the area 1 (S
A ₂ ), the position of the second area (Cb ₁ ) is obtained, and the position of this second area is determined as the position (SB ₂ ) of the image of the pattern to be superimposed on the second area. .

Further, in the above-mentioned exposure method, the positions of the first and second masks with respect to a predetermined reference ((XR ₁ , YR ₁ ),
(XR ₂ , YR ₂ )) and the difference (XR ₁ −XR ₂ , YR ₁ −) between the positions with respect to a predetermined reference.
It was decided to further include the step of obtaining YR ₂ ) and the step of correcting the position of the second region (SB ₁ ) based on this difference.

[0016]

According to the present invention, for each of a plurality of divided areas forming one chip area, it is selected whether importance is attached to the joining accuracy or the overlay accuracy, and the photosensitive substrate is selected according to the result of the selection. The position of the area formed above is obtained, and based on the obtained position, a new pattern is spliced or formed on the formed area to form a screen composite exposure with improved splicing accuracy. This can be achieved and the production yield of chips can be improved.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an exposure method according to an embodiment of the present invention will be described. Before that, a schematic configuration of a projection type exposure apparatus suitable for carrying out this method will be described with reference to FIG. FIG.
As shown in FIG. 2, the apparatus of this embodiment uses, for example, four reticles R ₁ , R ₂ , R ₃ and R ₄ similar to those in FIG. In FIG. 1, the reticle R ₁ is vacuum-sucked on the reticle stage RS of the exposure apparatus, and the other reticles are stored in a predetermined reticle storage unit (hereinafter referred to as a library). Reticle replacement is the reticle autoloader unit 1
Is done automatically by. The reticle stage RS holds the reticle and can be finely moved two-dimensionally (including rotation) in the horizontal plane, and is used for positioning the reticle with respect to the reference of the apparatus, for example, the optical axis AX of the projection lens PL. Now, place the wafer W under the projection lens PL and
A wafer stage 2 that moves dimensionally is provided and driven by a motor 3. The wafer stage 2 is used for both fine movement for alignment, which will be described later, and stepping movement during exposure in a step-and-repeat method. At the end of the wafer stage 2 is provided a movable mirror for vertically reflecting a laser beam from a laser light wave interferometer (hereinafter simply referred to as an interferometer) 4, and the interferometer 4 measures the position of the wafer stage 2. I do. In FIG. 1, only one set of the motor 3 and the interferometer 4 is shown, but it goes without saying that another set is provided for the other axial direction. The movement itself of the wafer stage 2 is controlled by the stage controller 5. Stage controller 5
Drives the motor 3 optimally based on the position information (current position) from the interferometer 4 and the target position information.

The apparatus of this embodiment is provided with four alignment systems. One is a reticle alignment system 10 for aligning only the reticle with respect to the apparatus, and one is a reticle mark and a mark attached to an exposed area on the wafer which are simultaneously detected to directly align the reticle and the wafer W. TTR alignment system 12 for adjusting the projection lens P without using a reticle.
T for detecting a mark on the wafer W via L and aligning the wafer W with respect to the apparatus (in particular, the optical axis AX)
The TL wafer alignment system 14, and the other is an off-axis type wafer for detecting the mark on the wafer W regardless of the projection lens PL and aligning the wafer W with respect to the apparatus. The alignment system 16. Of these four, the wafer alignment systems 14 and 16 and the TTR alignment system 12 are used in particular in this embodiment.

The sequence controller 20 outputs a reticle exchange instruction to the reticle autoloader section 1 so that a predetermined reticle is set in the apparatus, and the mode selector 21 determines which divided area on the screen combination to perform exposure. Output instructions. The mode selector 21 selects one of a plurality of predetermined alignment modes based on the instruction, and the design coordinate position information of the alignment mark on the wafer W required in the alignment mode is the alignment mark design. An instruction to be selected from the coordinate unit (storage device) 22 is output. The mode selector 21 also outputs a predetermined instruction to the alignment data capturing unit 23, and which alignment system (specifically, one of the wafer alignment systems 14 and 16 is used) is used for the mark position information (this is used). (Also called alignment data) is selected. The data acquisition unit 23 creates alignment data based on the mark detection information from the selected alignment system and the position information of the wafer W from the interferometer 4. The coordinate calculation unit 24 determines the position of the wafer stage 2 (wafer W), that is, the exposure, such that the divided area on the wafer W to be exposed overlaps the pattern projection image of the reticle based on the alignment data created by the data acquisition unit 23. Calculate the position. In this coordinate calculation unit 24, all shot array maps (maps based on the chip array on the wafer) of the divided areas to be exposed on the wafer W are stored in advance, and the maps are also referred to when necessary. It

The alignment sequence (alignment operation for determining the exposure position, calculation algorithm, etc.) is determined according to an instruction from the mode selector 21. The changeover switch unit 25 switches to send either the mark position information from the mark design coordinate unit 22 or the exposure position information from the coordinate calculation unit 24 to the stage controller 5. In the changeover switch unit 25 shown in FIG. 1, the data acquisition unit 23 creates alignment data, and in the changed state, the exposure method by step-and-repeat screen combination is performed.

Of the various alignment systems shown in FIG. 1, the wafer alignment systems 14 and 16 irradiate a wafer W with a laser spot light of an alignment mark level, and scatter or diffract light from the step edge of the mark. A photoelectric detection method is desirable. Further, it is also desirable that the laser spot light has a wavelength that does not expose (or makes it difficult to expose) the resist on the wafer W.

The TTR alignment system 12 also forms a laser spot light on the reticle and the wafer, and
A method is preferred in which the spot light is scanned so as to cross the alignment mark, and similarly scattered light and diffracted light from each mark are photoelectrically detected. Since this TTR alignment system 12 directly detects the positional deviation between the reticle mark and the wafer mark (to detect the relative deviation between the reticle and the wafer), only the mark position on the wafer W can be known. TTR alignment system 12 for the mark
The mark of the wafer W is positioned within a predetermined range that can be detected by the interferometer 4, and the position of the wafer W is detected by the interferometer 4, and the relative deviation amount between the reticle mark and the wafer mark is calculated by TT.
If determined by the R alignment system 12, the position of the mark on the wafer W can be specified.

Next, an exposure method as the first embodiment of the present invention will be described. In the first embodiment, it is assumed that two different patterns are spliced by screen synthesis and one chip area is overlapped and exposed. Therefore, of the reticles shown in FIG. 1, reticles R ₁ and R ₂ are used.
FIG. 3 is a flowchart showing the operation at the time of first printing (baking of the first layer) on the wafer W according to the first embodiment. Although the arrangement of the circuit pattern portions formed on each of the reticles R ₁ and R ₂ and various alignment marks is not particularly shown, it is similar to the arrangement of the patterns and marks formed on the wafer W as described below. You can think.
However, it is preferable that the reticle alignment mark detected by the reticle alignment system 10 be provided at a position common to all the reticles. Each step of FIG. 3 will be described below.

First, a resist-coated wafer is loaded and placed on the wafer stage 24 with a predetermined pre-alignment (mechanical) accuracy (step 100). Then, the reticle R ₁ (having the pattern A ′) is loaded and held on the reticle stage RS by the operation of the reticle autoloader unit 1 in response to the command from the sequence controller 20 (step 102). Next, using the reticle alignment system 10, the reticle R ₁ is precisely positioned with respect to the reference position (for example, the optical axis AX) of the apparatus (step 104). The alignment of this reticle is 2
In addition to positioning in each direction (x, y) of the dimension, rotation (rotation) is strictly corrected. As a method of correcting the reticle rotation, that is, a method of aligning the reticle with respect to each moving axis of the wafer stage 2 in the x direction and the y direction without rotating the reticle, for example, Japanese Patent Laid-Open No. Sho 56-56
The technique disclosed in Japanese Patent Laid-Open No. 102823 can be used.

Next, in response to a command from the sequence controller 20, it is set in the mode selector 21 that the exposure using the reticle R ₁ is the first print of the pattern A ', and the mode selector 21 causes the coordinate calculation unit 2 to perform the printing.
4 is used to output the position of the wafer stage 2, that is, the shot position where the pattern A ′ is exposed on the entire surface of the wafer according to the arrangement map (step 10).
6). At this time, the changeover switch unit 25 is switched from the position in FIG. 1 to prepare for the exposure operation. Then, the stage controller 5 successively inputs each shot position from the coordinate calculation unit 24 as a target position, and prints the pattern A ′ of the reticle R ₁ on the wafer by the step-and-repeat method (step 108). Thus, only the area A of the chip area is aligned and exposed in a matrix on the wafer as shown in FIG. At this time, in the present embodiment, the reticle R ₁ is provided with a mark pattern so that the y-direction alignment mark Sy and the x-direction alignment mark Sx are formed at two locations on the scribe line in contact with the region A. It is supposed to be. When the exposure of the pattern A'on one wafer is completed, it is judged whether or not the reticle should be replaced (step 110). Since we must expose the pattern B 'of the next reticle R _2, reticle R ₁ is unloaded, the reticle R ₂ is loaded (step 112). Thereafter, similarly, the exposure of the pattern B 'is executed by the step-and-repeat method. However, for this second reticle, the mode select in step 106
It is set to be the first print of pattern B ',
The shot position (design value) of pattern B'is pattern A '
The shot position (design value) is offset by a certain pitch. Further, in this embodiment, it is assumed that the second reticle R ₂ has no alignment mark to be imprinted on the wafer. When the pattern B ′ is exposed on the entire surface of the wafer as described above, as shown in FIG. 4, the area B of the chip area is in a predetermined positional relationship with the previously exposed area A (screen joining in the first layer). When performing, the position error is within the range that guarantees the splicing accuracy).

Next, at step 110, it is judged if the reticle needs to be replaced. Since two reticles have already been used here, it is determined whether or not to expose a new wafer (step 114). When exposing a new wafer, steps 100 to 110 are similarly repeated. By this, the first-printed chip regions (regions A and B) are formed on the wafer, and when the wiring is spliced from the first layer, the spliced portion CL of the regions A and B is formed, for example, as shown in FIG. Is formed as shown in FIG. The wiring pattern La associated with the pattern in the area A and the wiring pattern Lb associated with the pattern in the area B are precisely aligned with each other in the y direction, and are positioned so that a slightly overlapping portion Dab is generated in the x direction. Exposed. Wiring pattern La is reticle R
₁ , the wiring pattern Lb is formed on the reticle R ₂ .

Next, the sequence for performing the second and subsequent layers of overprinting (hereinafter referred to as second printing) on the wafer on which the first printing has been performed will be described. In this second printing, a new circuit pattern portion is precisely aligned (overlapped) with respect to each of the areas A and B on the wafer for exposure, and a new shot for the area A is formed. The mutual positional relationship with a new shot in the area B, that is, the splicing accuracy must be emphasized. It is often a seam CL as shown in Figure 5 on either layer of the second print.
Is formed (exposure). Therefore, first, a case where the splicing accuracy is emphasized and a case where the splicing accuracy is not emphasized will be described with reference to FIG.

FIG. 6 shows the area A in one chip area,
B design shot arrays PA ₀ and PB ₀ and a shot array S actually formed by first printing, for example.
A ₁ shows the positional relationship with SB _1, and Ca ₀ ,
Cb ₀ is the center point of each of the design shot arrays PA ₀ and PB ₀ ,
Ca ₁ and Cb ₁ are the center points of the real shot arrays SA ₁ and SB ₁ (broken line). In FIG. 6, the actual shot array S
A ₁ and SB ₁ are exaggerated and shown, assuming the worst case that is the most deviated from the design shot arrays PA ₀ and PB ₀ , respectively. The amount of deviation from the actual design position is ± 0.05
μm or less. This depends on the positioning (stepping) accuracy of the wafer stage 2, but, for example, 0.01 μ
If an interferometer 4 having a measurement resolution of m is used, it is possible to easily guarantee accuracy of ± 0.05 μm or more as a whole. However, as is clear from FIG. 6, the actual shot array SA ₁ (pattern area of the first layer) and the actual shot array S
Looking at the mutual arrangement with B ₁ (the pattern area of the first layer), it can be seen that the relative displacement is large. In this embodiment, the main purpose is not to solve the splicing error between the screens when the screen composite exposure is performed during such a first print (printing without any pattern or mark on the wafer). Although the solution to this problem will not be described in detail, most of the factors of the joint error are a reticle alignment error (particularly reproducibility) at the time of reticle exchange, lens distortion, and stepping accuracy. This is because the position of the wafer itself (that is, the wafer stage 2) is controlled by the same coordinate system (coordinate value) with an accuracy of, for example, 0.01 μm during the exposure operation by screen synthesis. Thus, for example, during exposure by reticle R _1, stores measured by using the reference marks provided projected position of reticle alignment mark of the reticle R ₁ a (XR _1, YR ₁₎ on the wafer stage 2, the reticle Similarly, when replacing the R ₂ reticle R ₂
Reticle alignment mark projection position (XR ₂ , Y
R ₂ ) is measured, and when the reticle R ₂ is exposed (XR ₁ −
If the wafer stepping positions are corrected by (XR ₂ , YR ₁ -YR ₂ ), the positions of the actual shot arrays SA ₁ and SB ₁ can be easily aligned accurately. In addition, the previous application by the same applicant as the present invention, Japanese Patent Application No. 60-207
The method described in JP-A No. 276 or the method disclosed in JP-A-59-74625 can also be used in the same manner. Further, the reticle alignment mark and the reference mark of the wafer stage 2 are positively detected simultaneously by the TTR alignment system 12, so that the reference mark is always fixed at a predetermined position and the reticle alignment mark is aligned with the TTR alignment mark. The same applies when a reticle alignment sequence (step 104 in FIG. 3) that drives the reticle stage RS based on the mark detection signal from the alignment system 12 is executed.

Now, returning to the explanation of FIG. 6, in the case where the wafer on which the actual shot arrays SA ₁ and SB ₁ are formed is subjected to overlay exposure by screen synthesis, the actual shot array SA ₁ ( Since the alignment marks Sx and Sy are formed in association with the area A), the image of the new pattern A ₂ ′ to be superimposed on the area A is almost accurately realized by the alignment by the wafer alignment systems 14 and 16. Exposure can be performed by superimposing it on the shot array SA ₁ . Similarly, if an alignment mark is also formed on the real shot array SB ₁ and the alignment mark is detected to perform wafer alignment, the image of the new pattern B ₂ ′ can also be exposed by superimposing it on the real shot array SB _1. . Although this is the conventional method of emphasizing superposition, it will be apparent from FIG. 6 that the joint error will inevitably increase if this is done.

Therefore, in this embodiment, the actual shot array SA
Alignment marks Sx and Sy of ₁ are detected, the center point Ca ₁ thereof is specified, a point Cb ₂ is obtained by shifting the center point Ca ₁ by a design pitch, and a new pattern B to be superposed The shot array SB ₂ of the pattern B ₂ ′ is positioned and exposed so as to be the center point of the ₂ ′ image. If the shot array S of a new pattern A ₂ ′ is overlaid on the actual shot area SA ₁ .
Suppose that A ₂ is exactly overlaid. The splicing accuracy between the shot arrays SB ₂ and SA ₂ is the best, and this is the idea that emphasizes splicing accuracy. A sequence for executing this method will be described with reference to the flowchart of FIG. The basic sequence is the same as that shown in FIG. 3, and only steps 106 and 108 are changed as shown in FIG. The new pattern A ₂ 'is formed, a new pattern B ₂ to the reticle R _2' is the reticle R ₁ is assumed to be formed.

In FIG. 7, the previous step 106 is changed to step 116, and the mode selector 21 receives a command from the sequence controller 20 to the effect that it is the second print screen composite exposure. The mode selector 21 declares to the alignment data acquisition unit 23 which alignment system to use, and the data acquisition unit 23 is set to a predetermined state in response to this. Further, the mode selector 21 also declares that the alignment mark design coordinate unit 22 and the coordinate calculation unit 24 perform wafer alignment. At the same time, the mode selector 21 uses the two reticles R ₁ and R ₂ to perform a sequence for screen exposure (that is, FIG. 3 and FIG. 7).
A combination of) and).

Now, as in the sequence of FIG. 3, the reticle is
Alignment and mark at a specific position on the wafer
The used wafer global alignment, etc. are completed and the
After step 116 is executed, step 108 in FIG.
Instead, the following steps 120-125 are performed.
First, the reticle aligned is R₁And R ₂
(Pattern A₂'And pattern B₂′)
Is determined (step 120). Reticle R here₁
If it is determined that the wafer alignment system 14, 16 or
Overlay exposure using the TTR alignment system 12
Marks Sx, S attached to the area A in one chip area
The position of y is measured and the coordinate value is stored (step 1
21). In this embodiment, the TTL wafer alignment system 14 is used.
The mark position is detected by. Because of this,
The selector switch unit 25 is set to the position shown in FIG.
Overlay exposure from the alignment mark design coordinate unit 22
The marks Sx and Sy in one area A
Information on the mark position in the design as detected by the dot system 14
Is output to the stage controller 5. This makes
The wafer stage 2 moves to align the TTL wafer.
The marks Sx, Sy are displayed on the data acquisition unit 23 via the system
The respective positions (X direction and Y direction) are captured. This
The lower layer as shown in FIG. 6 (actual shot array SA₁)of
Center point Ca of pattern area A₁Via the coordinate calculation unit 24
Coordinate value (XA, YA)
(Or mark position itself) is a predetermined storage device in the device
Are stored in correspondence with the chip array map.

Next, the changeover switch section 25 is replaced by the coordinate calculation section 24.
To the side, and the wafer stage 2 is positioned, that is, the shot is positioned so that the detected coordinate values (XA, YA) and the image center of the new pattern A ₂ ′, that is, the center point of the shot, exactly coincide with each other. (Step 122). Then, the area A in the chip is exposed (step 123), and it is determined whether or not to perform stepping toward the next chip (step 124). The operation of steps 120 to 124 is the pattern A ₂ ′.
The same process is repeated until the overlay exposure on the entire wafer surface is completed.

In step 121, when the global alignment of the wafer is completed, the positions of the marks Sx and Sy that should exist in the design can be obtained from the chip arrangement design map.
The difference between the positions of x and Sy and the designed position, that is, FIG.
It may be stored only shift of the center point Ca ₀ and Ca ₁ in.

Next, when exposing overlay a new pattern B ₂ 'for region B of the chip area, since it is determined not reticle R ₁ in step 120 as shown in FIG. 7, above the reticle R ₁ The coordinate values (XA, YA) or the shift amounts of the center points Ca ₀ , Ca ₁ sequentially stored during the exposure operation are read from the storage device based on the array map of the chips to be exposed with the pattern B ₂ ′. , The position where the image of the pattern B ₂ ′ is to be exposed, that is, the shot position is calculated by the coordinate calculator 24 (step 125). Then, as in the previous case, steps 122, 123, 124
Is executed and area B of all chip areas on the wafer
Overlay exposure is performed on the (actual shot array SB ₁ ). This step 125 is a design interval between the regions A and B, that is, a difference (XCa ₀ -X) between the center points in the x and y directions.
Cb ₀ , YCa ₀ −YCb ₀ ) and coordinate values (XA, YA)
The sum or difference between and will be calculated.

As described above, in the first embodiment of the present invention, 2
Since the importance is placed on the joining between the two shots, the overlay accuracy in each area divided in the chip is not so severe, but when the joining accuracy of the joint is conversely severe, for example, the bonding pad part or the internal wiring, And very efficiently in the process of the wiring layer that makes the wiring for connection,
High precision exposure is achieved. Further, only the first shot (exposure pattern for the area A) to be combined with the screen is aligned with the corresponding position on the wafer, and the alignment (mark detection) operation is not necessary for the other shots (exposure pattern for the area B). Therefore, the decrease in throughput can be avoided.

Further, in the first embodiment, since the joining as shown in FIG. 5 is performed, the joining accuracy is more severe in the y direction than in the x direction. For example, if the wiring patterns La and Lb have the same thickness, all joint errors in the y direction will affect the direction in which the width of the joint portion Dab in the y direction is reduced. Therefore, in step 121 of FIG. 7, of the marks Sx and Sy associated with the area A of the chip area, only the position of the mark Sy is measured, and when the overlay exposure is performed on the area B, the shot position of the pattern B ₂ ′ is determined. , Y direction may be determined based on the measured position of the mark Sy, and x direction may be defined by a design value based on an array map in the design of the chip. In this case x
With respect to the direction, the splicing accuracy deteriorates, but the mark position measurement time is halved, the throughput is improved, and the storage device capacity is halved.

Next, a second embodiment of the present invention will be described.
Basically, it is a system in which two shots are combined to form one chip pattern as in the first embodiment. However, the second
In the embodiment, two areas A and B (for example, actual shot areas SA ₁ and SB) on the wafer to be superimposed and exposed by screen synthesis are used.
The first embodiment differs from the first embodiment in that the alignment marks are formed in a predetermined positional relationship in each of ₁ ), and an alignment sequence and various calculations corresponding to the alignment marks are adopted.

FIG. 8 shows an arrangement of one chip area formed on the wafer by, for example, first printing. Each of the two divided areas A and B is accompanied by a circuit pattern portion and an alignment mark Sx. Sy is formed. In the area A, the marks Sxa and Sya are provided in the same arrangement as shown in FIG. 4, and in the area B, the marks Sxb and Syb are positioned so as to be located on the scribe line.
Is provided. When a new pattern A ₂ ′ is superimposed and exposed on the area A in such a chip area arrangement, first, the marks Sxa and Sya and the marks Sxb and Syb are first exposed.
Both positions of the real shot arrays SA ₁ and SB in the areas A and B are detected by the wafer alignment systems 14 and 16 and the like.
Each center points Ca ₁ of _1, Cb ₁ checks whether the place with what relative error in the coordinate system.

Then, the shot position of the pattern A ₂ ′ with respect to the area A is set to the overlay accuracy, the splicing accuracy, and the actual shot array SA required in the adjacent actual shot array SB ₁ .
Determine the splicing accuracy so that it does not decrease in consideration of the overlay accuracy required by ₁ itself. Therefore, the shot center of the pattern A ₂ ′ is not always the actual shot array SA ₁
May not be coincident with the center point Ca _{1 of the} pattern S ₁ and may deviate within a range satisfying the desired overlay accuracy of the array SA ₁ and the pattern A ₂ ′. The determination of the shot position of the pattern B ₂ ′ with respect to the area B is also performed with the marks Sxa, Sya,
The same processing is performed by referring to Sxb and Syb respectively.

In this embodiment, the alignment mark measurement time and the calculation processing time are increased in the overlay exposure of the areas A and B, but the average overlay accuracy in the chip area is reduced as compared with the first embodiment. It is possible to improve the splicing accuracy without doing so. Further, in the present embodiment, whichever of the regions A and B has a higher overlay precision, the overlay can be performed with good precision and the second region A and B can be overlapped as in the first embodiment. There is no limit to the order of printing. Further, there is an advantage that the capacity of the storage device does not have to be large as in the first embodiment.
However, the marks Sxa, Sya, and Sx are aligned during the alignment of the area A and B that is to be printed first.
When the positions of b and Syb are detected and the shot position of the second print next is also calculated in advance, a storage device having a certain capacity is required.

FIG. 9 is a plan view for explaining the mark arrangement according to the third embodiment of the present invention. As in the first and second embodiments, two shots are combined to form one chip area. Overlay exposure is performed. In this embodiment, a cross-shaped mark AMa is formed in the upper left corner of the area A, and a cross-shaped mark AMb is formed in the upper left corner of the area B. These marks are, for example, at the same time when the real shot arrays SA ₁ and SB ₁ are formed at the time of first printing,
That is, the mark pattern additionally provided in each reticle for first printing is exposed simultaneously with the circuit pattern. The distance M between the marks AMa and AMb
D is a predetermined value in design, and each center point Ca ₁ ,
This matches the interval of Cb ₁ . In this embodiment, these marks AMa and AMb are detected by the TTR alignment system 12 in FIG. 1 to detect the reticle and each real shot array S.
Direct alignment with A ₁ and SB ₁ shall be performed.

First, when a new pattern A ₂ ′ is superimposed and exposed on the area A, the pattern A ₂ ′ is
The mark RAa to be aligned with the mark AMa is formed on the reticle R ₁ ′ having a mark. After the reticle R ₁ ′ is aligned with the device, the mark RAa of the reticle R ₁ ′ and the mark AMa of the actual shot array SA ₁ are almost aligned based on the design map of the chip. Wafer (wafer stage 2)
To move. Then, the mark RAa and the mark AMa are aligned by the TTR alignment system 12, and the coordinate values of the wafer are aligned such that the pattern center of the reticle R ₁ ′ and the center point Ca _{1 of the} area A coincide (hereinafter, in the present embodiment,
The shot position to the area A) is obtained. Conventional TT
In the R / D / D alignment method, the exposure is immediately performed at the shot position. However, in this embodiment as well, in order to improve the joining accuracy, the marks AMb of the adjacent real shot array SB ₁ are arranged as in the second embodiment. Shall be referred to. In this case, the TRA alignment system 12 simultaneously detects the mark RAa of the reticle R ₁ ′ and the mark AMb of the actual shot array SB ₁ which are overlaid and exposed in the area A. This state is as shown in FIG. 10, in which the wafer is precisely spaced MD in the x direction with respect to the shot positions in the area A.
The mark RAa and the mark AMb may be aligned by moving the mark RAa. In FIG. 10, a circle If centering on the optical axis AX is an image field of the projection lens PL,
The center point of the new pattern A ₂ ′ (reticle R ₂ ′) is assumed to coincide with the optical axis AX. In this embodiment, the mark RAa is a simple square window surrounding the marks AMb and AMa, and the edge of this window is treated as a mark. Now, when the wafer is precisely moved by the distance MD and the joint accuracy of the actual shot arrays SA ₁ and SB ₁ is as designed, it means that the mark RAa and the mark AMb are accurately aligned. Become. Therefore, the positional deviation (alignment error) between the mark RAa and the mark AMb is obtained to estimate the splicing state of the actual shot arrays SA ₁ and SB ₁ , and the shot position to the area where the new pattern A ₂ ′ is detected first. Then, the calculation is performed to determine whether to perform the exposure as it is or to perform the exposure at a position where the shot position is slightly shifted in consideration of the joining accuracy and the overlay accuracy. Since this calculation can be handled in the same manner as in the second embodiment, further description is omitted.

As described above, in this embodiment, since the marks are provided at the common positions (upper left corner) of the actual shot arrays SA ₁ and SB ₁ on the wafer to be screen-synthesized, the TTR alignment common to the two shots is performed. It can be aligned by the system 12. Also, a mark is formed in the vicinity of the joint, but since it is also located at the end of the joint, there is little restriction on the location design of the joint wiring and the like.
Note that the cross-shaped alignment marks and their arrangement as in the present embodiment can be similarly applied to the first embodiment.

Further, in the above-mentioned first embodiment, second embodiment, and third embodiment, two shots are combined, but three shots are combined or four shots are combined as shown in FIG. It goes without saying that the same can be applied to the above. Needless to say, the methods of the above embodiments may be appropriately combined. Next, a fourth embodiment of the present invention will be described with reference to FIG. 11. This embodiment is particularly good when shots (divided areas) to be screen-combined are two-dimensionally arranged. It is possible to obtain splicing accuracy.

In FIG. 11A, new patterns A ₂ ′, B ₂ ′, C ₂ ′ and D ₂ ′ are added to each of the four divided real shot arrays SA ₁ , SB ₁ , SC ₁ and SD _1. When performing overlay exposure, only the alignment mark AMa associated with the actual shot array SA _{1 is referred} to by the same method as in the first embodiment, and the shot position of the pattern A ₂ ′ is the mark AM.
Based on the position of a, the patterns B ₂ ′, C ₂ ′, D ₂ ′
The position of each shot is managed by a design value (chip array map). In this case, in order to form one chip area on the wafer, the patterns A ₂ ′, B ₂ ′,
Four reticles having C ₂ ′ and D ₂ ′ are prepared. In this FIG. 11 (a), the order marks AMa is formed in the upper left corner of the actual shot array SA ₁ only joint portion between each actual shot arrangement _{SA 1, SB 1, SC 1} , SD 1 mark region Not regulated by. In the method of FIG. 11A, after the alignment of the real shot array SA ₁ and the overlay exposure of the pattern A ₂ ′ are completed, the other real shot arrays SB ₁ , SC ₁ ,
It does not matter which of SD _{1 is used} for exposure. In addition, the same splicing accuracy can be obtained between shots to be combined.

In this embodiment, when the pattern A ₂ ′ is superimposed and exposed on the actual shot array SA ₁ , the mark AMa is naturally detected and aligned.
Overlay exposure of pattern B ₂ ′ to real shot array SB ₁ , overlay exposure of pattern C ₂ ′ to real shot array SC ₁ , and pattern D ₂ ′ of real shot array SD.
Even during each operation of overlay exposure to ₁ , mark AM
The same effect can be obtained by adding an alignment operation for detecting a.

FIG. 11B is a two-dimensional extension of the second embodiment described above, in which four real shot arrays SA ₁ , SB ₁ , SC ₁ , SD ₁ on the wafer to be screen-synthesized are respectively arranged. Has a cross-shaped alignment mark AMa, A in the upper left corner.
Mb, AMc, and AMd are formed. In this embodiment, for example, when a new pattern A ₂ ′ is superimposed and exposed on the real shot array SA ₁ , the real shot array SA ₁ is exposed.
Mark A of the real shot array SB ₁ adjacent to _{1 in} the x direction
Actual shot array SD ₁ adjacent to the position of Mb in the y direction
And the position of the mark AMd of
_The shot position for the 2'actual shot array SA ₁ is determined. Of course, if the shot position of the pattern A ₂ ′ is determined by also referring to the position of the mark AMa, the overlay accuracy and the splicing accuracy in the actual shot array SA ₁ can be appropriately balanced. Regarding the alignment at the time of exposure with respect to each of the other real shot arrays SB ₁ , SC ₁ , SD ₁ , alignment marks are mutually referred to in the same manner as indicated by arrows in FIG. 11B.

FIG. 11C shows the above-mentioned FIGS. 11A and 11B.
In it is obtained by mix the method shown, where the actual shot array SA _1, SB _1, SC ₁ of the three regions of the respective mark AMa, AMb, AMC is provided, especially for real-shot sequence SD ₁ It is assumed that the mark to be referred to is not formed. Here, the superposition of the pattern A ₂ ′ on the real shot array SA _1, the superposition of the pattern B ₂ ′ on the real shot array SB ₁ , and the superposition of the C ₂ ′ on the real shot array SC ₁ are both the real shot array SA. Only the position of the mark AMa of ₁ is referenced, and each shot position is exposed by being managed by the design value. This is the same as the method of FIG. Next, the real shot array S
When the pattern D ₂ ′ is superposed on D ₁ , the adjacent real shot arrays S are arranged in the same manner as in FIG. 11B.
The shot position of the pattern D ₂ ′ is determined by referring to the two marks AMb and AMc of B ₁ and SC ₁ . Of course, the design distance from the mark AMa (actual shot array SA ₁ ) may also be referred to when determining the shot position of the pattern D ₂ ′.

11 (a), 11 (b) and 11 (c), the TTR alignment system 12, the TTL wafer alignment system 14, and the off-axis type wafer alignment are performed as in the previous embodiments. The alignment mark is appropriately detected by any one of the systems 16 or a combination thereof. According to this fourth embodiment,
In order to refer to each mark of two adjacent divided areas in the x direction and the y direction on one divided area on the wafer to be subjected to the overlay exposure, in particular, the pattern of the base (actual shot arrays SA ₁ , SB ₁ , SC ₁ , SD ₁ ) is effective in terms of improving the splicing accuracy and securing the throughput when the array error from the design position is random.

FIG. 12 shows the fifth embodiment of the present invention.
Will be described with reference to. In this embodiment, exposure for screen synthesis is performed on nine divided areas arranged in a matrix of 3 × 3, and an actual shot array SA ₁ ,
SB ₁ , SC ₁ , SD ₁ , SE ₁ , SF ₁ , SG ₁ , S
H ₁ and SI ₁ are formed respectively. Consider, for example, the case where a new pattern E ₂ ′ is superimposed and exposed on the actual shot array SE ₁ at the center. In this case, the maximum number of marks in the adjacent area referred to in order to determine the shot position of the pattern E ₂ ′ is four. That is, the marks AMb and AMh of the shot arrays SB ₁ and SH _{1 that} are adjacent to the real shot array SE _{1 in} the y direction.
And marks AMd and AMf of shot arrays SD ₁ and SF _{1 which} are adjacent to each other in the x direction. Of course shot array SE
_{If one} also refers to his own mark AMe, a total of five marks will be detected. In the case of FIG. 12, the shot position of the pattern E ₂ ′ in the x direction is the mark AM.
The shot position in the y direction is obtained from the intermediate position of the detected position in the x direction between d and AMf.
It may be obtained from an intermediate position with respect to the detected position in the y direction with respect to Mh. In addition, in this embodiment, it is apparent that the first, second, and third embodiments can be appropriately combined.

Although the respective embodiments of the present invention have been described above, the splicing exposure method of each of the above embodiments is stored in advance in the sequence controller 20 and the mode selector 21 in FIG. 1 by a program or the like. The operator simply instructs which alignment mode is to be used according to the number of shots to be combined in the screen and the shot position in one chip area, and the others are automatically executed.

In each of the embodiments, the plurality of actual shot arrays formed on the wafer by the first printing are exposed by the screen synthesis as shown in FIGS. 3 and 4, but they are formed on the wafer. It is the same even if each chip area is collectively exposed by an ordinary step-and-repeat method with an exposure apparatus having a large image field. In addition to the semiconductor wafer, the substrate to be exposed can be similarly applied to the screen synthesis method for patterning a large area such as a liquid crystal display plate.

[0054]

As described above, according to the present invention, splicing between a plurality of exposure shots (new pattern images) to be screen-synthesized does not significantly deteriorate the partial overlay accuracy in a large chip area. It can be achieved with the desired splicing accuracy. Further, the present invention is exactly the same in an exposure apparatus, such as an X-ray exposure apparatus, which sequentially exposes a mask pattern on a wafer by a step-and-repeat (step-and-scan) method in a state where a mask and a wafer are close to each other. It can be applied and has an advantage of not lowering the production yield of manufactured semiconductor elements or electronic components (large-area liquid crystal display panels, etc.).

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an exposure apparatus suitable for applying a method according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a conventional screen synthesis exposure method.

FIG. 3 is a flowchart showing a sequence at the time of first printing by screen synthesis.

FIG. 4 is a plan view showing a pattern arrangement on a wafer at the completion of first printing to which the first embodiment of the present invention is applied.

FIG. 5 is a plan view showing an example of seaming.

FIG. 6 is a plan view showing a pattern arrangement for comparing splicing emphasis and non splicing emphasis.

FIG. 7 is a flowchart showing a sequence at the time of superposition exposure of screen synthesis according to the first embodiment.

FIG. 8 is a plan view showing a mark arrangement applied to a screen compositing method according to a second embodiment of the present invention.

FIG. 9 is a plan view showing mark arrangement applied to the screen compositing method according to the third embodiment.

FIG. 10 is a plan view showing a state during alignment in the third embodiment.

FIG. 11 is a plan view illustrating a screen compositing method according to a fourth embodiment.

FIG. 12 is a plan view for explaining a screen compositing method according to the fifth embodiment.

[Explanation of symbols]

R ₁ , R ₂ , R ₃ , R ₄ reticle W wafer SA ₁ , SB ₁ , SC ₁ , SD ₁ , SE ₁ , SF ₁ , SF ₁ , S
G ₁ , SH ₁ , SI ₁ Screen area on wafer (real shot array) Sx, Sy, Sxa, Sxb, Sya, Syb, AM
a, AMb, AMc, AMd, AMe, AMf, AMh
Alignment mark on wafer RAa Alignment mark on reticle CL Joint part PL Projection lens 2 Wafer stage 4 Interferometer 12 TTR alignment system 14 TTL Wafer alignment system 16 Wafer alignment system 20 Sequence controller 21 Mode selector

Claims (6)

(57) [Claims] 1. An exposure apparatus which exposes each of a plurality of mask patterns on a photosensitive substrate by splicing each other on the photosensitive substrate via a projection optical system, and exposing at least one of the plurality of masks, A mask stage that selectively positions with respect to the projection optical system, a first position detection unit that detects the position of the positioned mask, and a predetermined area on the photosensitive substrate on which the photosensitive substrate is placed. With respect to the projection optical system, a second position detecting means for detecting the position of the predetermined area, and a position for detecting the predetermined area according to the position of the predetermined area on the photosensitive substrate. Based on the determination of the control means and the determination of the control means, depending on whether the splicing accuracy or the superposition accuracy is important, the first and second Selection means for selecting a sequence of detecting the position of the mask and the position of a predetermined area by the position detection means, based on the position of the mask and the position of the predetermined area detected according to the selection of the selection means An exposure apparatus which positions the mask stage and the substrate stage. 2. A first mask of a plurality of masks is positioned to form an image of a pattern of the first mask on a first region on a photosensitive substrate, and the first mask is replaced with the first mask. A second mask of the plurality of masks is positioned, and an image of the pattern of the second mask is placed on the photosensitive substrate.
Is formed in the second area having the predetermined positional relationship with respect to the area of 1), the patterns on the plurality of masks are spliced to each other on the photosensitive substrate in the predetermined positional relationship, and In an exposure method for forming a pattern image on each of the two areas by further overlapping, a step of selecting at least one of importance of the joining accuracy and importance of the overlapping accuracy, and a result of the selection. Accordingly, positioning the image of the stitched pattern or the image of the superimposed pattern with respect to one of the first and second regions. 3. The exposure method according to claim 2, wherein the selection is to select the positioning sequence. 4. The pattern of the positioning, wherein the position of the center point of the first region is obtained and the position of the center point is superposed on the first region when the splicing accuracy is emphasized. Position of the image of the pattern which is determined as the position of the image of the pattern, and the position separated from the center point by the designed distance between the first region and the second region is overlapped with the second region. When placing importance on the overlay, the position of the first region is obtained and the position of the first region is determined as the position of the image of the pattern to be overlaid on the first region. 4. The exposure according to claim 3, wherein the position of the second area is obtained and the position of the second area is determined as the position of the image of the pattern to be superimposed on the second area. Method. 5. A step of measuring positions of the first and second masks with respect to a predetermined reference, a step of obtaining a difference between positions with respect to the predetermined reference, and the second region based on the difference. The method according to claim 2, further comprising the step of correcting the position of. 6. The exposure method according to claim 2, wherein the mask is a reticle.