JP2551395B2 - MOS4 quadrant multiplier - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier for multiplying analog signals, and more particularly to a MOS 4-quadrant multiplier formed on a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, a MOS4 quadrant multiplier of this type has been disclosed in, for example, IEEE Journal of So.
lid-State Circuits, VOL. SC
-21, NO. 3, pp. 430-435, June
Buff and Walling in 1986 (reference 1)
The MOS4 quadrant multiplier proposed by K.K.

However, the MOS4 quadrant multiplier described in Document 1 has a problem that it is difficult to apply an input signal because the source is grounded although it performs a linear operation.

In order to solve the above-mentioned problems, a MOS 4-quadrant multiplier described in Japanese Patent Application No. 6-130470 (filed on June 13, 1994) by the same applicant as the present applicant has been proposed.

FIG. 4 is a circuit diagram of the MOS4 quadrant multiplier described in the above-mentioned application specification.

In the figure, the drain currents of the transistors M1 to M8 having the same characteristics are: I _D1 = I _D3 = β (1 / 2V _x + V _R1 −V _S −V _TH ) ² (1) I _D2 = I _D4 = β (−1 / 2V _x + V _R1 −V _S −V _TH ) ² (2) I _D5 = β (−1/2 V _x +1/2 V _y −V _R1 + V _R2 −V _TH ) ² (3) I _D6 = β (1 / 2V _x +1/2 V _y −V _R1 + V _R2 −V _TH ) ² (4) I _D7 = β (−1/2 V _x −1/2 V _y −V _R1 + V _R2 −V _TH ) represented by _{^{2 (5) I D8 = β}} (1 / 2V x -1 / 2V y -V R1 + V R2 -V TH) 2 (6). Here, β is a transconductance parameter, V _x and V _y are input voltages, V _TH is a threshold voltage of each MOS transistor, and V _S is a constant current source I.
_O potentials, V _R1 and V _R2 are reference DC voltages (reference voltages).

From the condition of the tail current, the relationship of I _D1 + I _D2 + I _D3 + I _D4 + I _D5 + I _D6 + I _D7 + I _D8 = I _O (7) holds.

Here, if the equations (1) to (7) are solved, 4
The differential output current ΔI of the quadrant multiplier is ΔI = (I _D6 + I _D7 ) − (I _D5 + I _D6 ) = 2βV _x V _y (8).

As described above, it is possible to obtain a CMOS four-quadrant multiplier which operates linearly in the input voltage range in which none of the transistors forming the octtail cell are cut off. Therefore, the fluctuation of the transconductance β of the MOS transistor can be suppressed, and the fluctuation of the differential output current ΔI can also be suppressed. Therefore, a linear input voltage range and a floating input system are provided.
It is possible to obtain a MOS 4-quadrant multiplier that can easily apply an input signal.

[0010]

However, in the circuit shown in FIG. 4, the constant current I _O is made up of eight MOS transistors.
However, the current flowing through the MOS transistors M1, M2, M3 and M4 related to the multiplication function cannot be uniquely determined.

That is, the linear input range of the multiplier is determined by the sum of the currents flowing through the MOS transistors M1, M2, M3 and M4, but if the constant current I _O is quadrupled, the linear input voltage range becomes 2 Doubled and M
The current flowing through the OS transistors M5 to M12 is also quadrupled.

An object of the present invention is to solve the above-mentioned problems,
It is to provide a MOS4 quadrant multiplier with a linear input voltage range and a floating input system.

[0013]

In order to achieve the above-mentioned object, the MOS4 quadrant multiplier according to the present invention has a tail current in which four sources of two pairs of transistors whose drains are commonly connected are commonly connected. The quadritail cell, which is driven by, forms a multiplier core circuit.

In the input circuit for generating the gate input voltage of each transistor constituting the multiplier core circuit, two transistors are cascode-connected, and four transistors in the lower stage are commonly connected and driven by one tail current. It is composed of cascode and quadritail cells.

Two pairs of the first input signals are differentially input to the gates of the four cascode-connected lower transistors, and two pairs of the first input signals are input to the gates of the four upper transistors. A second input signal having a reverse phase is differentially input.

An input voltage is supplied to the gates of the four transistors forming the multiplier core circuit from between the cascode-connected transistor stages, and the output current of the multiplier core circuit and the cascode connection forming the input circuit are connected. A differential output current is output by adding the drain currents of the four upper transistors.

[0017]

Since the MOS4 quadrant multiplier according to the present invention includes two sets of octo-tail cells by adopting the above-mentioned configuration, if the constant current is quadrupled, the linear input voltage range is doubled. Can be decided.

[0018]

The present invention will be described in detail with reference to the drawings.

FIG. 1 shows a MOS4 showing an embodiment of the present invention.
It is a circuit diagram of a quadrant multiplier.

In the figure, the input voltage to the multiplier core circuit driven by the tail current I _O is the sum voltage of the two signals and the difference voltage, and the MOS transistors M1, M
2, each drain currents of M3 and _{M4, I D1 = β {V R} +1/2 (V x + V y) -V S -V TH} 2 (V GS1 ≧ V TH) (9) I D2 = β { V _R −1/2 (V _x + V _y ) −V _S −V _TH } ² (V _GS2 ≧ V _TH ) (10) I _D3 = β {V _R +1/2 (V _x −V _y ) −V _{S ^{-V TH} 2 (V GS3 ≧}} V TH) (11) I D4 = β {V R -1/2 (V x -V y) -V S -V TH} 2 (V GS4 ≧ V TH) (12 ) Is represented.

From the condition of the tail current, the relationship of I _D1 + I _D2 + I _D3 + I _D4 = I _O (13) holds.

Here, from equations (9) to (12), MO
When the differential output current ΔI of the S4 quadrant multiplier is calculated,

[0023]

It becomes

In the equation (14), since the MOS transistor has the square law, the ideal multiplier characteristic is obtained in the input voltage range where none of the MOS transistors in the circuit cut off, and the input voltage is As the size becomes larger, the MOS transistor in the circuit starts to cut off and deviates from the ideal multiplier characteristic.

FIG. 2 is a transfer characteristic diagram showing the characteristics of the MOS 4-quadrant multiplier with V _y as a parameter.

In the figure, as described above, M in the circuit
An ideal multiplier characteristic is obtained in the input voltage range in which none of the OS transistors are cut off, and as the input voltage increases, the MOS transistors in the circuit start to cut off and deviate from the ideal multiplier characteristic. I can see it coming.

Further, based on the equation (14), the transfer characteristics of the multiplier are shown in FIG. 2 with V _y as a parameter. It is also shown to have limiting characteristics for large signals.

The transconductance characteristic of the multiplier is equal to both V _x and V _y , and the transconductance characteristic is obtained by differentiating the equation (14) with respect to V _x .

[0030]

## EQU1 ##

FIG. 3 is a characteristic diagram showing the transconductance characteristic shown in the equation (15) with V _y as a parameter.

As is clear from FIGS. 2 and 3,
The quadritail cell constitutes the multiplier core circuit.

Next, the input voltage to the gates of the four transistors of the multiplier core circuit composed of quadritail cells is changed from equations (9) to (12) by the input circuit composed of cascode quadritail cells. Showed (±
V _x ± V _y ) / 2.

In the cascode quadritail cell shown in FIG. 1, four transistors M5A, M5B and M6 are used.
A and M6B have the same tail current I _b , but the transistors M5A and M5B, and the transistor M6A.
The gates of M6B and M6B are commonly connected to form a differential pair to which the first input signal is differentially input. That is,

[0036]

Also, transistors M5A and M8A, transistors M5B and M7A, transistors M6A and M8.
The same drain current flows through B and the transistors M6B and M7B, the gate-source voltages become equal, and V _GS5A = V _GS5B = V _GS7A = V _GS8A = 1 / 2V _x (18) V _GS6A = V _GS6B = V _GS7B = V _GS8B = -1 / 2V _x (19) Therefore, the input voltages to the gates of the four transistors of the multiplier core circuit composed of the _quadritail cell are respectively V _G1 = V _R2 + 1 / 2V _y −V _GS7B = 1 / 2V _x + 1 / 2V _y + V _R1 + V _R2 −V _S1 (20) V _G2 = V _R2 −1 / 2V _y −V _GS8A = −1 / 2V _x −1 / 2V _y + V _R1 + V _{R2 -V S1 (21) V G3} = V R2 -1 / 2V y -V GS8B = 1 / 2V x -1 / 2V y + V R1 + V R2 -V S1 (22) V G4 = V R2 + 1 / 2V y - _{V GS7A = -1 / 2V x +} 1 / 2V y + V R1 + V R2 -V S ₁ (23) is obtained.

However, V _S1 is the common source voltage of the cascode quadritail cell. Therefore, the formula (2
By substituting 0) to (23) into the equations (9) to (12), the equation (14) can be similarly derived.

That is, the cascode quadritail cell shown in FIG. 1 is an input circuit of a multiplier core circuit composed of quadritail cells.

[0040]

Since the MOS4 quadrant multiplier according to the present invention includes two sets of octtails, it can uniquely determine the linear input voltage range.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a MOS 4-quadrant multiplier showing a first embodiment of the present invention.

FIG. 2 is a transfer characteristic of the multiplier core circuit of the present invention.

FIG. 3 is a transconductance characteristic of the multiplier core circuit of the present invention.

FIG. 4 is a conventional circuit diagram of a MOS 4-quadrant multiplier.

[Explanation of symbols]

M1 to M8 MOS transistors I _b , I _O constant current source

Claims (4)

(57) [Claims] 1. A quadritail cell, in which four sources of two pairs of transistors whose drains are commonly connected are commonly connected and which is driven by one tail current, forms a multiplier core circuit, and the multiplier core circuit comprises: An input circuit for generating a gate input voltage of each transistor constituting the circuit is composed of two sets of oct tail cells, and by adding an output current of the multiplier core circuit and an output current of the input circuit, A MOS 4-quadrant multiplier characterized by outputting a differential output current. 2. The input circuit is configured by a cascode quadritail cell in which two transistors are cascode-connected and the lower transistor is driven by one tail current with four sources connected in common. A MOS4 quadrant multiplier according to claim 1 characterized. 3. The gates of the four cascode-connected lower transistors are differentially input with two pairs of the first input signals, and the cascode quadritail cells are connected to the upper four gates of the transistors. 2 pairs of second input signals are differentially input so that they are in opposite phase to the first input signal, and four transistors forming the multiplier core circuit are respectively provided between the cascode-connected transistor stages. 3. The MOS4 quadrant multiplier according to claim 2, wherein an input voltage is supplied to the gate of the MOS4 quadrant. 4. A differential output current is output by adding the output current of the multiplier core circuit and the drain currents of the four cascode-connected upper transistors forming the input circuit. A MOS4 quadrant multiplier according to claim 1 characterized.