JP2551601B2 - Memory check circuit - Google Patents

Description

The present invention relates to a memory check circuit for performing a functional test of a memory circuit such as a static random access memory circuit (hereinafter referred to as RAM) in a data processing device or the like. It is about.

(Prior Art) Conventionally, a memory check circuit of this type has been disclosed in
There are those described in JP-A-61-54550, JP-A-61-67162 and the like. The configuration will be described below with reference to the drawings.

FIG. 2 is a block diagram of a conventional memory check circuit disclosed in Japanese Patent Laid-Open No. 61-67162.

This memory check circuit is for performing a function test of the memory circuit 1 including a RAM having a decoder for decoding the address signal ADR and a memory cell array,
An address switching circuit 2 and a write data switching circuit 3 which are switched and controlled by a test mode signal TM are provided, and an output side of the address switching circuit 2 is connected to an address register 4 for inputting the output of the address switching circuit 2 by a clock signal. The output side of the address register 4 is connected to the address input section of the memory circuit 1 and also connected to the input side of the address switching circuit 2 via the +1 addition circuit 5. The address switching circuit 2 is a circuit for switching the address signal ADR externally applied by the test mode signal TM to the output signal of the +1 addition circuit 5 and applying the output signal to the address register 4. Write data switching circuit 3
The output side of is connected to the write data input section of the memory circuit 1, and is also connected to the input side of the write data switching circuit 3 via the write data register 6. Here, the write data switching circuit 3 is a circuit for switching the write data signal WTD externally supplied by the test mode signal TM to the output signal of the write data register 6.
The write data register 6 is a circuit which inputs the output signal of the write data switching circuit 3 based on the write pulse WP and gives a complement signal of the output signal to the input side of the write data switching circuit 3. An error determination circuit 7 is connected to the output section of the memory circuit 1. The error judgment circuit 7 is composed of an exclusive OR circuit and has a control signal CT.
It is a circuit that determines the quality of the read signal RD from the output section of the memory circuit 1 based on the above, and outputs the signal Sout of the determination result.

 Next, the operation of FIG. 2 will be described.

First, the test mode signal TM is set to logic “0” and the write data signal WTD is input to the write data switching circuit 3 and the address signal ADR is input to the address switching circuit 2. By advancing the clock signal CLK by one, the address signal ADR enters the address register 4 through the address switching circuit 2 and one write pulse signal WP is sent to the memory circuit 1.
The write data WTD is written in the memory circuit 1 through the write data switching circuit 3 by inputting the data into the memory circuit 1. At this time, the output of the memory circuit 1 is set to the read enable signal RE “0” so that the error determination circuit 7 does not cause an error.

When the write data signal WTD and the address signal ADR have been externally fetched, the test mode signal TM is set to "1" and one more write pulse signal WP is input. After that, the clock signal CL
The initial value is written in each address of the memory circuit 1 by repeating the input of one K and the input of two write pulse signals WP. When all addresses have been written, the read enable signal RE is set to "1" so that the error judgment circuit 7 can be effectively operated, and two write pulse signals WP are input for one clock signal again. repeat. When an error exists in the memory circuit 1 on the way, the error determination circuit 7 outputs a signal Sout indicating an error state. As a pattern as write data, a checkerboard pattern of 1010 or 0101 is most suitable when the bit width of generally known data is 4 bits.

As described above, in the test mode, the address register 4 and the +1 adder circuit 5 sequentially advance the address to the memory circuit 1 one by one, and the write pulse WP input into each address is repeated twice. The initially applied data pattern and the complement signal passing through the write data register 6 are written in each memory cell of the memory circuit 1. Then, the output of the memory circuit 1 reads the two data patterns, and the error judgment circuit 7 checks the exclusive OR to thereby output the memory circuit 1
Error that each memory cell of "0" turns into "1", and "1"
Both errors that erroneously set to "0" are checked.

(Problems to be Solved by the Invention) However, in the memory check circuit having the above configuration,
There were the following problems.

Memory circuit 1 having decoder and memory cell array
If the data bit length is large, it is necessary to increase the bit length of the write data register 6, so that the circuit scale of the memory check circuit is significantly increased. Further, since the checkerboard pattern is used as the inspection algorithm, it is difficult to detect the multiple selection failure of the decoder or the like caused by a rudimentary mistake in the memory mask pattern design,
There is also a problem that the failure detection capability of the memory circuit 1 is low.

The present invention provides a memory check circuit that solves the problems that the above-mentioned conventional techniques have, that the circuit scale of the memory check circuit increases significantly as the data bit length of the memory circuit increases, and that the fault detection capability is low. To do.

(Means for Solving Problems) In order to solve the above problems, the present invention provides a clock in a memory check circuit for testing a readable and writable memory circuit having an address input terminal, a data input terminal and a data output terminal. It is composed of a multi-bit counter for counting signals and a plurality of exclusive OR gates, and inputs the output signal and the address control signal of the lower bits except the most significant bit of the counter, and outputs the maximum in response to the address control signal. A complement circuit that outputs an output signal of a lower bit and an inverted signal thereof and outputs an output signal of each lower bit except the least significant bit and an inverted signal thereof according to the output signal of the least significant bit, and a test The address signal supplied from the outside according to the mode signal is switched to the output signal of the complement circuit To the address input terminal, and a data input signal supplied from the outside in accordance with the test mode signal to the output signal of the most significant bit of the counter, and the data applied to the data input terminal. An input switching circuit and a comparison circuit for comparing the read signal output from the data output terminal with the inverted signal of the most significant bit of the counter are provided.

(Operation) According to the present invention, since the memory check circuit is configured as described above, “0” or “1” is written in the memory circuit by using the most significant bit of the counter, whereby the memory circuit Even if the bit length increases, it is only necessary to increase the bit length of the data input switching circuit and the comparison circuit, and the increase in circuit scale can be suppressed. Further, the complement circuit functions to complement the address, and the counter and the data input switching circuit function to generate the marching pattern, thereby causing a memory read / write operation failure, an address multiple selection failure, and It becomes possible to detect failures in a larger number of memory circuits such as a memory data holding operation failure. Therefore, the above problems can be eliminated.

(Embodiment) FIG. 1 is a configuration block diagram of a memory check circuit showing an embodiment of the present invention.

This memory check circuit is for performing a function test of the memory circuit 10 provided in a data processing device or the like, and the memory circuit 10 is composed of, for example, a static RAM of m bits × 2 ⁿ words, a memory cell array, In addition to a decoder for decoding the address signal ADR and selecting the memory cell, an address input terminal 10a for inputting the address signal ADR, a write enable input terminal for inputting a write enable signal WE enabling writing to the memory cell.
10b, data input terminal 10 for inputting data input signal Din
c and a data output terminal 10d for outputting the read data output signal Dout.

The memory check circuit for checking the memory circuit 10 is reset by the reset signal RESET and sequentially counted up by the clock signal CLK (n
+1) has a counter 11 bits, low-order n bits 2 ⁰ to 2 ^n-1 of the output signal complement circuit 12 of the counter 11
Is connected to the input side, and the output side of the complement circuit 12 is connected to the address switching circuit 13. The output signal of the most significant bit 2 ⁿ of the counter 11 is connected to the data input switching circuit 14 and also to the comparison circuit 16 via the signal inverting inverter 15.

Here, the complement circuit 12 receives the address control signal.
AC by a circuit that outputs an output signal or 1's complement signal that the lower n bits 2 ⁰ to 2 ^n-1 of the counter 11, for example n-number of exclusive OR gates (hereinafter referred to as ExOR) 12-1
.About.12-n. Least significant bit of counter 11
2 ⁰ and the address control signal AC is the least significant bit ExOR12-1
Is connected to the input side, also lower bits 2 ¹ ~ counter 11
2 ^n-1 and the least significant bit 2 ⁰ of the lower bits each ExOR12-2~
They are connected to the input side of 12-n. The address switching circuit 13 complements the n-bit address signal ADR supplied from the outside by the test mode signal TM with the complement circuit 1.
It is a circuit that switches to an output signal of 2 and applies the output signal to the address input terminal 10a of the memory circuit 10. The data input switching circuit 14 switches the data input signal Din supplied from the outside by the test mode signal TM to the output signal of the most significant bit 2 ⁿ of the counter 11, and outputs the output signal.
This is a circuit which is given to the data input terminal 10c of. Further, the comparison circuit 16 uses the data output signal Do read from the memory circuit 10.
It is a circuit that compares ut with a signal obtained by inverting the output signal of the most significant bit 2 ⁿ of the counter 11 by the inverter 15 and outputting an error signal Pass / fail according to the comparison result.

FIG. 3 is a time chart of FIG. 1, and the operations (1) to (6) of FIG. 1 will be described with reference to this time chart.

In this embodiment, a marching pattern that marches in time is used as a tester pattern, and an address complement is used as an address sequence.

(1) Operation at startup When the address control signal AC is set to logic "0", the test mode signal TM is enabled (= "1"), and the reset signal RESET is input to the counter 11 to reset the counter 11, The address of the memory circuit 10 is shown at address 0.

(2) Initial setting operation When a pulse of the write enable signal WE is input to the write enable terminal 10b of the memory circuit 10, the signal “0” of the most significant bit 2 ⁿ of the counter 11 is written to the address (address 0) of the memory circuit 10. Get caught. Next, the clock signal to the counter 11
When one pulse of CLK is input, the address (2 ⁿ -1) of the memory circuit 10 is shown. After that, the clock signal CLK of one pulse of the write enable signal WE for all addresses
By repeatedly inputting 1 pulse of
All “0” 6 is written to each address of 10, and the initial setting is completed.

Since no error is detected in this step, the error signal Pass / Fail and the data output signal Dout are don't
Just take care. The address sequence is the address (0)
→ (2 ⁿ -1) → (2) → (2 ⁿ -3) → (4) → (2 ⁿ −
5) → ... → (2 ⁿ -4) → (3) → (2 ⁿ −2) → (1) →
(0), the clock pulse is input 2 ⁿ times, and the most significant bit 2 ⁿ of the counter 11 becomes “1”.

(3) Operation of "0" read and "1" write By the operation of (2), "0" is written in all bits of the memory circuit 10, and the address (0 The contents of the address) are read in the form of the data output signal Dout. Then, the comparison circuit 16 outputs the signal “0” in which the signal “1” of the most significant bit 2 ⁿ of the counter 11 is inverted by the inverter 15.
And the data output signal Dout are compared with each other to determine whether they match or not, and output an error signal Pass / Fail. If all m bits of the data output signal Dout read from the memory circuit 10 are "0", the data output signal Dout and the inverter
Since the output of 15 matches, the error signal Pass of "1" indicating the normal state is output, and if any one of the m bits of the data output signal Dout is "1",
An error signal Fail of "0" indicating a mismatched state (abnormal state) is output.

Next, one pulse of write enable WE is applied to the memory circuit 10
When input to the write enable terminal 10b of, the write enable pulse “0” writes all “1” to the m-bit address (address 0) in the memory circuit 10, and outputs “1”.
The data output signal Dout of is output and the error signal pass / Fai
l becomes “0”. Then, when one pulse of the clock signal CLK is input to the counter 11, the address of the memory circuit 10 becomes (2 ⁿ
-1) Shows the address. After that, one pulse of the write enable signal WE and one pulse of the clock signal CLK for all addresses.
By repeatedly inputting a pulse and a pulse, the contents of each address are read by the write enable signal WE of "1", and all "1" are written by the write enable signal WE of "0". Test read and "1" write.

By this operation, the pulse of the clock signal CLK is input to the counter 11 2 ⁿ times, whereby all the bits of the counter 11 become “0”.

(4) Operation of "1" read and "0" write "1" is written in all bits of the memory circuit 10 by the operation of (3), and "1" is written by the same operation as (3). "Read," 0 "write test.

(5) "0" read and "1" write operations "0" is written in all the bits of the memory circuit 10 by the operation of (4). Next, set the address control signal AC to "1".
Then, the output of the complement circuit 12 is given to the address input terminal 10a of the memory circuit 10 through the address switching circuit 13, and the address of the memory circuit 10 indicates the address (1). After that, one pulse of the write enable signal WE and one pulse of the clock signal CLK are repeatedly input, and the "0" read and "1" write tests are performed as in (2) above. At this time, the address sequence is address (1) → (2 ⁿ
-2) → (3) → (2 ⁿ -4) → ... → (2 ⁿ -3) → (2)
→ (2 ⁿ -1) → (0) → (1), and the address sequence performed in the above (2) is traced in reverse.

(6) "1" read and "0" write operations "1" is written in all bits of the memory circuit 10 by the operation of (5), and "1" read by the same operation as (5). , "0" write test, memory circuit
10 tests are over.

 This embodiment has the following advantages.

(A) “0” or “1” is written in the memory circuit 10 by using the signal of the most significant bit 2 ⁿ of the counter 11, so that even if the bit length of the memory circuit 10 increases, data input It is only necessary to increase the bit lengths of the switching circuit 14 and the comparison circuit 16, and it is possible to suppress an increase in circuit scale.

(B) The complement circuit 12 complements the address, and the counter 11 and the data input switching circuit 14
Since the marching pattern is generated by, the instability of the operation of the address decoder in the memory circuit 10 (address multiple selection failure) and the malfunction at the time of address switching, which cannot be found by the periodic address selection, can be detected. Further, inspection of an address decoder in the memory circuit 10 (address multiple selection failure inspection), inspection of influence of noise at writing on memory characteristics (memory data holding operation failure inspection), and memory read / write operation Since defect inspection and the like can be performed, it becomes possible to detect failures in more memory circuits.

(C) Since it can be activated by the memory check circuit with a simple operation, it can also be used for a aging test (aging test) of the memory circuit 10.

Note that the present invention is not limited to the illustrated embodiment, for example, the complement circuit 12 may be configured by a circuit other than ExOR 12-1 to 12n, the memory circuit 10 may be configured by a memory other than the static RAM, or the like. Deformation is possible.

(Effects of the Invention) As described in detail above, according to the present invention, the most significant bit of the counter is used to add "0" or "1" to the memory circuit.
Therefore, even if the bit length of the memory circuit is increased, it is only necessary to increase the bit length of the data input switching circuit and the comparison circuit, and thereby the increase in the circuit scale can be suppressed as much as possible.

Moreover, since the memory check circuit using the marching pattern is provided with a complement circuit for inverting or not inverting the output signals of the bits except the most significant bit and the least significant bit output from the counter, this complement circuit An address can be provided to the compliment based on the output signal of to test each fault. Further, this complement circuit applies the output signal of the least significant bit or its inverted signal to the address input terminal via the address switching circuit according to the address control signal, so that the address signal is generated by the inverted signal of the least significant bit. Since the sequence given to the complement can be controlled in the reverse order, the defect of the decoder due to the address transition can be detected. As a result, more memory circuit failures such as memory read / write operation failure, address multiple selection failure, and bit interference can be detected.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory check circuit showing an embodiment of the present invention, FIG. 2 is a block diagram of a conventional memory check circuit, and FIG. 3 is a time chart of FIG. 10 …… Memory circuit, 10a …… Address input terminal, 10b ……
Write enable terminal, 10c ... Data input terminal, 10d ...
… Data output terminal, 11 …… Counter, 12 …… Complement circuit, 13 …… Address switching circuit, 14 …… Data input switching circuit, 15 …… Inverter, 16 …… Comparison circuit, AC ……
Address control signal, ADR ... Address signal, CLK ... Clock signal, Din ... Data input signal, Dout ... Data output signal, RESET ... Reset signal, TM ... Test mode signal, WE ... Write enable signal.

Claims (1)

(57) [Claims] 1. A memory check circuit for testing a readable / writable memory circuit having an address input terminal, a data input terminal and a data output terminal, wherein a multi-bit counter for counting a clock signal and a plurality of exclusive OR gates are provided. And inputting the output signal and the address control signal of the lower bit excluding the most significant bit of the counter, and outputting the output signal of the least significant bit and its inverted signal according to the address control signal,
A complement circuit for outputting the output signal of each lower bit except the least significant bit and its inverted signal according to the output signal of the least significant bit, and an address signal supplied from the outside in response to a test mode signal. An address switching circuit that switches to an output signal of a complement circuit and supplies the output signal to the address input terminal, and a data input signal that is externally supplied according to the test mode signal and switches to the output signal of the most significant bit of the counter. A data input switching circuit for applying the output signal to the data input terminal; and a comparison circuit for comparing the read signal output from the data output terminal with the inverted signal of the most significant bit of the counter. And a memory check circuit.