JP2551939B2 - IC test equipment - Google Patents

Description

TECHNICAL FIELD The present invention relates to an IC test device for testing the quality of operation of a manufactured IC.

(Prior Art) Conventionally, as shown in FIG.
A plurality of pin electronics PE ₁ , PE ₂ , PE ₃ , ... are connected to the common section CP via the bus BUS, and the device under test DUT is input from these pin electronics PE ₁ , PE ₂ , PE ₃ ,. output pins _{P 1, P 2, P 3} , with providing the test signal to ..., input and output pins _{P 1, P 2, P 3} , was supposed to input signals that occur ....... Also, pin electronics PE ₁ , PE
₂ , PE ₃ , ... is composed of a test unit group TU ₁ , TU ₂ , TU ₃ , ... containing a plurality of test units, and each test unit has a test pattern sequence as a test signal as a test cycle. Pattern memory T that occurs in synchronization with
U _1a , TU _2a , TU _3a , ... and a timing generation circuit TU _1b , TU _2b , TU for generating predetermined timing information to be given to the test signal
_{, 3b} , ..., driver circuits TU _1c , TU _2c , TU _3c , ..., which give predetermined level information to the test signal, and the device under test D.
Compare the output signal of UT with a predetermined reference level signal,
Alternatively, further, the comparison result may be used as the timing generation circuit TU.
Comparison circuits TU _1d , TU _2d , TU _3d , ... for comparing and collating with expected value data at the comparison timings from _1b , TU _2b , TU _3b , ... and this comparison circuit TU _1d , TU _2d , TU _3d , ... Test data memory TU _1e , TU that sequentially stores the output signal of ... in synchronization with the test cycle
_{There were 2e} , TU _3e , and so on. On the other hand, the common part CP is the IC during the test execution according to the contents of the test program.
A controller C for controlling the operation of the entire test apparatus,
The pin electronics PE ₁ , PE ₂ , PE ₃ , ... consisted of a common unit CU that supplies common signals (common signals), such as test rate signals and signals under test, which are required during test execution. .

Therefore, the test is executed by first writing in the controller C a test program that describes the test conditions for each of the test units (TU _{1a to} TU _3d ) created in advance and the method of processing and outputting the test result. Then
According to the contents of the test program, the controller C firstly shares the common unit CU and all pin electronics PE ₁ , PE.
₂ Set the test conditions for each test unit in PE ₃ ,. For example, pattern memory TU _1a , TU _2a , T
Test patterns for U _3a , ..., Timing data generated for timing generation circuits TU _1b , TU _2b , TU _3b , ......, driver circuits TU _1c , TU _2c , TU _3c , ...... Is the level value of the test signal, and the comparison circuits TU _1d , TU _2d ,
Set comparative reference level values for TU _3d , .... Then, after all the condition settings have been completed, the controller C activates the common unit CU and gives an instruction to start the test. During test execution, each test unit synchronizes with the common signal from the common unit CU, and the pattern memory TU
Test patterns are generated from _1a , TU _2a , TU _3a , ..., a test signal converted to a predetermined timing and a predetermined level is applied to the device under test DUT, and a response circuit from the device under test DUT is compared. TU _1d , TU _2d , TU _3d ,…
Is compared with the expected value data at the level comparison or comparison timing, and the output is sequentially tested data memory.
Stores in TU _1e , TU _2e , TU _3e , .... And
When the controller C receives the end signal from the common unit CU, the test results are sequentially read from the test data memories TU _1e , TU _2e , TU _3e , ... Within the pin electronics PE ₁ , PE ₂ , PE ₃ ,. Various calculations and processing for failure diagnosis are performed according to the contents of the test program to complete a series of tests.

(Problems to be Solved by the Invention) By the way, when evaluating an LSI, various operation margin tests called SHMOO PLOT are often used. This SHMO
As shown in Fig. 7, O PLOT assigns arbitrary parameters (t _A and V _{IN in the} figure) to the vertical and horizontal two axes, and changes each parameter in sequence with a predetermined step value. The test results (PASS / FAIL) are displayed together. Note that in this example, a total of 20 tests have been executed.

In such a test, the set value of the test unit assigned to t _A or V _IN must be changed to a predetermined value, for example, 20 times during a series of tests. In this case, the number of test units (number of pin electronics) assigned to the vertical axis or horizontal axis to change the set value is not limited to one pin electronics, but all test units assigned as parameters of each axis. Will cover multiple pin electronics.

In this regard, in the conventional IC test apparatus shown in FIG. 6, when changing the set values of all the pin electronics test units to be changed, one controller C sequentially accesses each pin electronics in series. Therefore, in a test that requires, for example, 20 changes (usually at least several times as many times) as a result, the condition change time as a whole becomes enormous, and an efficient test can be performed. There was a problem of not having.

On the other hand, the following can be considered as the calculation / processing contents for failure diagnosis with respect to the test results stored in the test data memory.

Presence / absence of failure Counting the number of failure bits Pattern address of failure location Correspondence between failure bit and expected value Others In order to realize such a failure diagnosis function, conventionally,
Basically, the following two methods were adopted. The first is a method realized by software processing of the controller, and the second is a method having individual dedicated hardware. Specifically, the first method is to read all the test results stored in the test data memory with the controller after the test is completed.
The failure diagnosis of the above items 1 to 3 is performed on the read data according to the contents of the test program. Therefore, although there is flexibility regarding the failure diagnosis method, the time required for failure diagnosis will increase as a result of the large amount of data that is read out of all test results (over all pin electronics), resulting in an efficient test. There was a problem that I could not.

The second method is to prepare dedicated hardware for each of the pin electronics to perform the above calculations and processing, and operate that hardware after the test is completed or during the test execution to calculate and process the test results. It is something to do. Further, after the completion of the calculation / processing, the controller reads only the calculation / processing results of all pin electronics and recalculates / processes. For that calculation
Although there is an advantage that efficient testing can be performed because processing can be performed at high speed and the amount of transferred data is small, basically the problem is that the amount of hardware increases in functional units.
There was a problem that there was no flexibility in adding new functions. The current mainstream of IC test equipment is this second method.

By the way, recent LSIs include those with more than 200 pins and gates with 20 to 30k gates. Future LS like this
An IC test apparatus that can handle the I test needs to have a performance of about 300 to 500 in the number of pins (number of pin electronics) and several hundreds of kilobits to several megabits in the depth of the pattern memory. When such an IC test apparatus is realized by a conventional method, the following problems may be considered.

(I) In one test, the setting conditions for the test unit must be changed frequently. In this case, the pin electronics to be changed may cover almost all pin electronics in an extreme example. Therefore, in the conventional configuration method, it is necessary to replace the data of the test unit, which is sequentially and serially deflected with respect to all pin electronics, during the test, and the test takes a long time to change the condition. Become.

(Ii) As the device under test increases in size, the test pattern length increases in proportion to it. Therefore, a capacity of several hundred k to several M bits is required as the depth of the pattern memory. At the same time, the capacity of the test data memory for storing the test results is basically required to be the same as that of the pattern memory. Therefore, when performing a fault diagnosis, for example, assuming that the number of faulty bits is counted, the conventional configuration method newly provides dedicated hardware for faulty bit counting, or the contents of the test data memory are changed. It is necessary to move to the main memory of the controller, where the counting is performed. But in the former case,
In this example, the counter function is required, and considering other examples, an increase in the amount of hardware is unavoidable,
There are many problems. On the other hand, in the latter case, although there are few problems when the number of pin electronics that stores the test results is small, in actual LSIs, the output terminals often exceed 100 pins, and as a result, the number of pins is 100 or more. It is necessary to sequentially transfer the test data from the pin electronics to the main memory. Therefore, as in the case of (i), there is a problem that the test takes a long time due to the time to transfer the test result.

As described above, the conventional IC test device uses a single controller to perform all the control such as condition setting for each test unit, reading of test results and calculation / processing of test results. Has become serial, and there is a problem that a large amount of time is spent for test preparation and post-processing. Therefore, when the pin electronics of the IC test device is increased to increase the number of pins, or when the test functions in the pin electronics are increased to achieve higher functionality, the overhead prevents the efficient test. There was a problem.

(Object of the Invention) The present invention has been proposed in view of the above points, and it is an object of the present invention to reduce the test time in the case of realizing an IC test device having a high function and a large number of pins. The purpose is to provide an IC test device that can perform tests efficiently.

(Means for Solving Problems) In order to achieve the above-mentioned object, the present invention sets conditions for each test unit, reads test results, and It is intended to increase the efficiency of the test by making the sub-controllers newly provided in each pin electronics share the calculation and processing and perform various execution controls in parallel.

(Example) Next, the Example of this invention is described. Needless to say, the embodiment is merely an example, and various modifications and improvements can be made without departing from the spirit of the present invention.

FIG. 1 shows an embodiment of the IC test apparatus of the present invention. The IC test apparatus according to the present invention includes a common unit CP including a main controller MC and a common unit CU, a test unit group TU ₁ including sub-controllers SC ₁ , SC ₂ , SC ₃ , ... And various test units. TU ₂ , TU ₃ , ... and a plurality of pin electronics PE ₁ , PE ₂ , PE ₃ , ... are connected by a bus BUS as shown in the figure, and each pin electronics PE ₁ , PE ₂ , PE ₃ , ... give a test signal to the input / output pins P ₁ , P ₂ , P ₃ , ... of the device under test DUT, and
The signals generated at the input / output pins P ₁ , P ₂ , P ₃ , ... Are input. Also, the test unit group TU ₁ , TU ₂ , TU ₃ ,…
The individual test units that make up ... include pattern memories TU _1a , TU _2a , TU _3a , ... that generate test pattern sequences as test signals in synchronization with the test cycle, and predetermined timing information given to the test signals. Timing generating circuits TU _1b , TU _2b , TU _3b , ... and driver circuits TU _1c , TU _2c , TU _3c , ... which give predetermined level information to the test signal.
, And the output signal of the device under test DUT is compared with a predetermined reference level signal, or the comparison result is compared with the expected value data at the comparison timing from the timing generation circuits TU _1b , TU _2b , TU _3b ,. Comparison circuit TU that compares and collates with
_1d , TU _2d , TU _3d , ... and this comparison circuit TU _1d , TU _2d , TU _3d , ...
There are provided test data memories TU _1e , TU _2e , TU _3e , ... For sequentially storing the output signals of ... In synchronization with the test cycle. The test unit is not limited to these,
Other test units are provided as needed.

The flow of test execution in the above embodiment is shown in FIG.

Then, first, the main controller MC loads the test program to be executed into the main memory (see a). Main controller MC has a common test program unit
CU instruction group and each pin electronics PE ₁ , PE ₂ , PE ₃ ,…
.. for each instruction group, and each control program is generated based on the instruction group (see b). The contents of the control program include, for example, setting conditions and setting procedures for each test unit in its own pin electronics, contents and method of changing conditions, calculation and processing method of test results, and the like.
If the test program is basically divided into such control program groups, it is not necessary for the main controller MC to have this function.

Then, the main controller MC, after generating the control program, downloads the program to the common unit CU and each of the sub-controllers SC ₁ , SC ₂ , SC ₃ , ... (See c and d). Then, after loading all the control programs, the main controller MC sets the sub-controllers SC ₁ , SC ₂ , SC ₃ ,
...... is commonly activated by using a dedicated control line on the bus BUS (see e), and then the sub-controller SC ₁ ,
Waiting for the operation end notification from SC ₂ , SC ₃ , ... (f
reference).

On the other hand, in the sub-controllers SC ₁ , SC ₂ , SC ₃ , ..., the bus BU
When the start signal is received from the dedicated line on S,
The loaded control program is operated to set the test condition value for each test unit in its own pin electronics (see g). Then, after all the condition settings have been completed, an end notification is sent to the main controller MC (see h). Regarding the end notification, if the dedicated line on the bus BUS is used, the main controller MC can simultaneously receive the end notification from all the pin electronics PE ₁ , PE ₂ , PE ₃ , ....

The main controller MC, which receives the end notification from all the pin electronics PE ₁ , PE ₂ , PE ₃ , ... cancels the wait and activates the common unit CU to start the test (see i). After this, the common unit CU sends the signal under test to the main controller MC and the sub-controllers SC ₁ , SC ₂ ,
Send to SC ₃ , ... (See j). The operation of the entire IC test equipment is controlled by the main controller MC under the control of the common unit CU (test mode) from the time the test signal is generated until the test end signal is generated (during test execution). There is. During the test execution, the main controller MC and the sub-controllers SC ₁ , SC ₂ , SC ₃ , ... monitor the operating status of each test unit (see l), and if any abnormality is detected, the test is interrupted to the common unit CU. Operates to issue a command (see m).

When the common unit CU finishes the prescribed test operation, the main controller MC and the sub-controllers SC ₁ , SC ₂ , SC ₃ , ...
Is notified of the end of the test (see k). When the main controller MC confirms the test end notification (see n),
If necessary, read the test progress (DC measurement result, etc.) from the common unit CU, and sub-controllers SC ₁ , SC ₂ , SC ₃ , ...
The process waits for the processing result in (see o).

When the sub-controllers SC ₁ , SC ₂ , SC ₃ , ... receive the test end notification, each sub-controller individually reads the test result from the test unit in its own pin electronics (see p) and according to the control program contents. Then, the presence or absence of a fault, the number of fault bits, the fault address, etc. are checked from the test results (see q). After that, if the test unit in my pin electronics needs to be modified,
New data is set in the test unit (see r), and when it is finished, the main controller MC is notified of the end (see s). As described above, this end notification can be simultaneously notified to the main controller MC from all the pin electronics PE ₁ , PE ₂ , PE ₃ , ... Using a dedicated line on the bus BUS.

Main controller MC has all sub-controllers SC ₁ and SC
_2, SC _3, releases the waiting state receives the end signal from ..., based on the contents of the test program, read the test results from the sub-controller required (calculation-processing result) (see t). After that, if the condition needs to be changed (if the number of executions is less than the number of condition changes), the common unit CU is restarted (see i) to execute the test again, and the next test is executed. Then, when a series of tests is completed, all test results (calculation / processing results)
Is output (see u), and the test is completed.

As described above, according to the present invention, it is possible to change the conditions during the execution of the test for each sub-controller SC ₁ , SC ₂ , SC ₃ ,.
Since the conditions can be simultaneously executed in parallel, there is an advantage that the time for changing the condition can be executed in a short time regardless of the number of test units (the number of pin electronics) to be changed.

Further, after completion of the test in the present invention each pin electronics PE ₁ (after test end signal receiving), PE _2, PE _3, the sub-controller SC ₁ in ......, SC _2, SC _3, to the control under the ...... Presence / absence of failure for the contents of certain test data memory TU _1e , TU _2e , TU _3e , ... Controls calculation / processing such as counting of failure bit pattern address failure bit and expected value Program content , And then the main controller MC reads the calculation / processing results of each pin electronics PE ₁ , PE ₂ , PE ₃ , ... sequentially and recalculates / processes. Although there is a drawback that the amount of hardware increases, the calculation processing can be executed in parallel in each pin electronics PE ₁ , PE ₂ , PE ₃ , ..., so that fault diagnosis can be made more efficient. in addition,
Since the present invention is basically a software process, it takes a little time to execute the calculation / process, but it has the advantage of being rich in flexibility and expandability of functions.

Furthermore, by inserting the change contents and its control sequence in the control program of the sub-controllers SC ₁ , SC ₂ , SC ₃ , ... in advance, the main controller MC can commonly change the change time by the sub-controllers SC ₁ , SC 3. ₂ , SC ₃ , ...
The sub-controllers SC ₁ , SC ₂ , SC ₃ , ... can change the conditions in parallel to all pin electronics PE ₁ , PE ₂ , PE ₃ , ..., basically pin electronics PE ₁ , PE ₂ , PE. Even if the number of ₃ ... increases, there is no problem that the time required to rewrite data increases, and it has the advantage of being compatible with future LSIs with many pins.

Also, by introducing sub-controllers SC ₁ , SC ₂ , SC ₃ , ..., the functions equivalent to the hardware such as the counter circuit can be freely realized by software, so that the tester hardware functions can be delegated to software. It is possible, and there is also an advantage that the hardware amount can be reduced as a whole. Note that the essential difference from the distributed processing of computers is that software transfer of this hardware is possible.

Next, Fig. 3 shows the device under test DUS in the test.
Shows an example of condition setting of input / output signal of
IC test equipment, PE _J , PE _K , PE _L , PE _M are pin electronics. Input / output pin 1 of the device under test DUT
Pins to 4 pins are used as 1 pin: input pin 2 pin: input pin 3 pin: input / output pin 4 pin: output pin.

Then, the pin 1 of the device under test DUT is supplied with the test signal from the pin electronics PE _J. The figure shows the test signals at the nth cycle and the n + 1th cycle of the test pattern, and in this example, t _J1 during each cycle.
The RZ (return-to-zero) signal, which becomes the high level of V _J1 at the timing of and the low level of V _J2 at the timing of t _J2 , is supplied to the device under test DUT.

The pin electronics PE _K supplies the test signal to the pin 2 of the device under test DUT. In the figure, at the timing of t _{K1 in} each cycle, the high level of V _K1 or
An NRZ (non-return to zero) signal, which is a low level of V _K2 , is supplied to the device under test DUT.

Also, the 3 pin test signal from the pin electronics PE _L of the device under test DUT is applied, the device under test DUT with respect to the same pin electronics PE _L
The response result of is input. In the figure, each cycle (n, n + 1
Early supplies a signal from the pin electronics PE _L to the device under test DUT mode cycle) (I-mode)
It operates as a mode in which the second half the response result to the pin electronics PE _L from the device under test DUT is inputted (O
Mode), which is an example of so-called I / O mode operation. Then, in the case of the I mode, 2 in this example.
In both cycles, the low level of V _L2 is the device under test D
Supplied to UT. In the case of O mode, in this example, an output higher than the threshold level V _THL of the comparison circuit of the pin electronics PE _L from the device under test DUT is input to the pin electronics PE _L in the nth cycle, and the device under test is tested in the n + 1th cycle. An output below V _THL from the DUT is input to the pin electronics PE _L.

Further, 4-pin device under test DUT is to pin electronics PE _M, the response result of the test device DUT is input. In FIG higher response than the threshold level V _THL is input to the pin electronics PE _M in n-th cycle, n +
Less responsive than V _THM is input to the pin electronics PE _M in the first cycle.

FIG. 4 shows a block configuration diagram of pin electronics for performing the above setting. Although the figure shows the pin electronics PE _J , the other pin electronics have exactly the same configuration. It should be noted that a level generation circuit is used as a test unit rather than the configuration shown in FIG.
TU _Jf has been added.

Pin Electronics PE for performing the test of Fig. 3
The contents of the _J setting conditions (part of the control program in the sub-controller) are as follows. In other words, the timing generation circuit TU _Jb has five timings (t _{J1 to} t _J4 , STB _J 5).
Set a predetermined value for t _J1 and t _J2 of the phase). Driver circuit
Set the RZ waveform mode to TU _Jc . Pattern memory TU
_Ja is set so that high level data is output at the nth cycle and the n + _1th cycle. Level generator TU _Jf
Of the output levels (3 phases of V _J1 , V _J2 , and V _THJ ) of V _J1 , V _J2 is set to a predetermined value. A desired operation can be realized by the above settings.

Next, the setting conditions of Pin Electronics PE _K are as follows. The suffix J in FIG. 4 will be described as K. Then, the timing generator TU _Kb
Is set to a predetermined value for t _K1 . N for driver circuit TU _Kc
Sets the RZ waveform mode. N for pattern memory TU _Ka
The high level data is output in the cycle and the low level data is output in the (n + 1) th cycle. Predetermined values are set for V _K1 and V _K2 of each output level of the level generation circuit TU _Kf . With the above settings, the pin electronics PE _K can achieve the desired operation.

The setting conditions for Pin Electronics PE _L are as follows. That is, the timing generation circuit TU _Lb has t _L1
And STB _L to the specified values. Further, setting the start timing and value of the stop time for the output of each driver circuit TU _Lc in t _L3 and t _L4 and floating level (or fixed level). In the example of FIG. ₃ , the intermediate timing value of the cycle is set to t _L3, and the timing value of the end of the cycle is set to t _L4 . Driver circuit
Set the NRZ waveform mode to TU _Lc . Pattern memory T
U _La becomes low level data at the nth cycle and the n + 1th cycle, and is set to be floating by t _L3 and released by t _L4 so as to operate in the I / O operation mode. Level generator TU
Set predetermined values for V _L2 and V _THL for each output level of _Lf . Further, the storage start address of the test result is set in the test data memory TU _Le . Pin electronics PE _L by further configuration desired operation can be realized.

Setting condition contents of the pin electronics PE _M is as follows. That is, the timing generation circuit TU _Mb STB _M
Set a predetermined value to. The driver circuit TU _Mc is set to fix the output at the floating level in order to operate in the O mode. Set a predetermined value for V _THM, which is the output level of the level generator TU _Mf . Also, the storage start address of the test result is set in the test data memory TU _Me . The pin electronics PE _M can be realized desired operation by the above configuration.

Incidentally, the pin electronics PE _J -PE Each input or pin electronics P to the device under test DUT from _L
E _M, so that each output from the device under test DUT to the pin electronics PE _L of O mode is executed at a predetermined timing, level, it is necessary to set the time. Also,
Pin electronics PE _L , PE _M pattern memory TU _La , TU
An expected value for the response result of the device under test DUT is stored in _Ma , the expected value is generated at the same time as the test pattern, and the expected value is sent to the comparison circuits _TULd and _TUMd .

Next, FIG. 5 is a block diagram showing another embodiment of the present invention. In this embodiment, the sub-controllers SC ₁ , SC ₂ , ...
.. are arranged in units of a plurality of test unit groups, that is, in units of pin electronics groups PE ₁₁ , PE ₁₂ , ..., Different from the embodiment shown in FIG. The operation is basically the same as that of the above-described embodiment, except that the sub-controllers SC ₁ , SC ₂ , ... Control objects of a plurality of test unit groups are applied to the above-described embodiment. Therefore, this embodiment is suitable when the number of test units or the number of pin electronics is smaller than that of the above-described embodiments.

In each of the above embodiments, the common unit CU is an IC
It is a general term for units whose functions within the test unit in the test equipment cannot be divided into pin electronics units.
Specifically, it consists of a rate generator, DC measurement unit, DUT power supply, and so on. Of these, the unit most relevant to the description so far is the rate generator, and the following describes its function only in that respect.

That is, the rate generator waits for activation from the main controller MC after being loaded with test conditions such as a test rate value from the main controller MC. After starting from the main controller MC, the rate generator first sends a signal under test to the main controller MC and sub controller S.
_{C 1, SC 2, SC 3} , sent to ... to set the entire system to the test mode, all pin electronics _{PE 1, PE 2, PE 3} , and sends a rate signal to the test unit of .... Then, after generating the rate signal for a predetermined number of clocks, the rate generator stops the generation of the rate signal, and then outputs the test end signal to the main controller MC and the sub-controllers SC ₁ , SC ₂ , SC ₃ ,.
Send to ... and release the whole system from the test mode.

(Effects of the Invention) As described above, in the IC test apparatus of the present invention, condition setting and calculation of test results for various test units that were conventionally performed in series with one controller were performed.
Various execution controls such as processing are divided into sub-controllers provided in each pin electronics unit or multiple pin electronics units, in addition to the main main controller, so that control can be performed in parallel. It is possible to greatly improve the problem of increasing the test time, which has been a major problem when increasing the functionality and increasing the pin count of IC test equipment. It should be noted that since the control contents of the sub-controller can be sufficiently supported by the functions of a general-purpose microprocessor, an increase in the amount of hardware and the price of the device are not a big problem.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an IC test apparatus according to the present invention, FIG. 2 is a flow chart showing its operation, and FIG. 3 is an explanatory diagram of condition setting of input / output signals of a device under test in a test. FIG. 4 is a block diagram of the pin electronics for performing the setting of FIG. 3, FIG. 5 is a block diagram of another embodiment of the present invention, and FIG. 6 is a conventional IC.
FIG. 7 is a block diagram showing the test apparatus, and FIG. 7 is an explanatory diagram of the operation margin test. CP ... Common section, MC ... Main controller, CU ... Common unit, BUS ... Bus, PE ₁ , PE ₂ , PE ₃ ...... Pin electronics, SC ₁ , SC ₂ , SC ₃ ...... Sub controller, TU ₁ , T
U ₂ , TU ₃ …… Test unit group, TU _1a , TU _2a , TU _3a …… Pattern memory, TU _1b , TU _2b , TU _3b …… Timing generation circuit,
TU _1c , TU _2c , TU _3c …… Driver circuit, TU _1d , TU _2d , TU _3d ……
Comparison circuit, TU _1e , TU _2e , TU _3e …… Test data memory, DU
T: device under test, P ₁ , P ₂ , P ₃ ... I / O pin, PE
₁₁ , PE ₁₂ …… Pin electronics group

Claims (3)

(57) [Claims] 1. A main controller for controlling the entire system of the apparatus, a pattern memory for generating a test pattern sequence as a test signal in synchronization with a test cycle, and a timing generator for generating predetermined timing information given to the test signal. Circuit, a driver circuit that gives predetermined level information to a test signal, a comparison circuit that compares the output signal of the device under test with a predetermined reference level signal, or compares with expected value data at the comparison timing from the timing generation circuit, this comparison The test unit is composed of a test unit group such as a test data memory for sequentially storing the output signal of the circuit in synchronization with a test cycle and arranged in a plurality of input / output pin units of the device under test. It has a sub-controller to control the The roller is an IC test device characterized in that condition setting for each test unit, reading of test results, and execution control of calculation / processing of test results are performed in parallel according to the contents of the test program written from the main controller. . 2. The sub-controller according to claim 1, wherein the sub-controller is arranged in a plurality of pin electronics units.
IC test equipment. 3. Sub-controllers are provided with different condition settings for each test unit, reading of different test results, execution control of calculation / processing of different test results in parallel, and respective condition setting and test. The IC test apparatus according to claim 1, wherein a test program is written from the main controller to each sub-controller so that the reading of the result and the calculation / processing of the test result are performed in cooperation with each other.