JPS602699B2 - information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus, and more particularly to timing control during fault diagnosis in an information processing apparatus.

When a malfunction is detected in an information processing device, the system repeats re-execution and retry, and if it still does not succeed, it is assumed that there is a failure, and the device is disconnected and a diagnostic operation is started. In order to quickly finish the diagnostic operation for detecting a fault location, a diagnostic function is provided in advance in the device. Fault diagnosis methods include a manual diagnosis method using a maintenance panel by storing and displaying flip-flops, writing and reading memory devices, and sequential circuit cycle advances; A method of logging out the information to the main memory, etc., or setting the information to an internal flip-flop by a program, performing a clock advance, and then using a flip-flop where the calculation results are stored.
There is a method of reading out the state of the flop and comparing it with a pattern of expected values.

In particular, in the last diagnosis method, the logic unit constituting the information processing device is divided into combinational circuits surrounded by flip-flops, and diagnosis is performed for each of these divided circuits. FIG. 1 is a diagram showing an example of a circuit divided into diagnostic units.

The combinational circuit 2 that is the target of the divided diagnosis is connected to the input flip-flop 1 and the output flip-flop 3. First, data is set in the input flip-flop 1, and then the specified circuit is set.

The data acquisition timing is provided to the output flip-flop 3 by the check advance. An input signal group 4 is sent from the input flip-flop 1 to the combinational circuit 2, and after processing such as arithmetic operations is performed in the combinational circuit 2, an output signal group 5 is sent to the output flip-flop 3. . Diagnosis is then performed by comparing and comparing the status output signal 6 taken in from the output flip-flop 3 with a predetermined value. In order to diagnose such problems,
With conventional timing control methods, it is possible to suppress the timing supply system when diagnosing a fault, or to provide only the timing of a specific phase. It is commonly done for

That is, it has been impossible to supply timings of different phases to the slave and each combinational circuit 2, or to suppress the timing supply for each combinational circuit 2.
FIG. 2 is a flow chart showing the diagnostic procedure of FIG.

In the circuit shown in FIG. 1, tests are repeated according to the procedure shown in FIG. 2 to detect and point out faults in the circuit.

That is, by the diagnosis start STA, {11 divided circuit 2
Test data is set in the input flip-flop 1 of (8 in FIG. 2). Next, the data acquisition timing T of the flip-flop 3 which becomes the output of the '21 division circuit 2 is supplied (9 in FIG. 2). Next, the contents of the flip-flop 3, which is the output of the dividing circuit 2, are discussed and the results are checked. In other words, it verifies whether the contents of input flip-flop 1 are being transmitted correctly. If the contents of output flip-flop 3 are correct, there is no fault in the dividing circuit 2, and if not, there is a fault in the dividing circuit 2. It is determined that this has occurred (see 10 in Figure 2), and the process ends (ST
P). In this way, the fault diagnosis method for the circuit shown in Fig. 1 is executed in the order shown in Fig. 2, but in this case, there is no problem because the output flip-flop 3 and the input flip-flop 3 have an in-phase transfer relationship. occurs.

Figure 3a shows the data acquisition timing, Figure 3b shows the state of input flip-flop 1, and Figure 3c shows the output flip-flop.
The states of flop 3 are shown respectively.

As shown in FIG. 3a, the data acquisition timing T has a certain pulse width, and when this timing T is supplied to the output flip-flop 3, it is also supplied to the input flip-flop 1 at the same time. .

The state of input flip-flop 1 is fixed to "1" when data is set, but the state of the result processed by the previous stage circuit is set by the input of data capture timing T, and the previous state is destroyed. Therefore, this state is taken into the output flip-flop 3 again. In this way, when the capture timing T is sent to the output flip-flop 3, data is also captured at the input flip-flop 3 at the same time, and the preset input pattern changes. Between input flip-flop 1 and output flip-flop 3,
There is no problem if there is a circuit delay larger than the timing pulse width, but if it is smaller than the delay pulse width, the output flip-flop 3 receives the calculation result of the combinational circuit 2 after the input flip-flop 1 changes. This will make the diagnosis impossible. Therefore, conventionally, when there is a division circuit 2 for in-phase transfer as shown in FIG. Changes in the test data of flop 1 are suppressed.

However, it is extremely complicated to trace back and control the flip-flops in the previous stage for each divided circuit 2.
This method has the disadvantage of making it difficult to create a diagnostic program to implement the diagnostic method. An object of the present invention is to eliminate such conventional drawbacks, and when diagnosing a fault in an information processing device, it is an object of the present invention to provide different phase timings to each logical unit constituting the information processing device, and to The purpose is to control timing supply and inhibition for each logical unit to eliminate the influence of in-phase transfer on fault diagnosis.

In the present invention, when the divided logic units are divided into a plurality of logic units and each divided logic unit performs logical operations in synchronization with timings of different phases, a plurality of timing distribution lines are provided for each logic unit, and each distribution line The above objective is achieved by independently controlling timing supply and inhibition in response to the timing.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 4 shows the timing supply v of the information processing device according to the present invention.
FIG. 2 is a block diagram of a feeding system.

The information processing device is divided into a plurality of logical units 13 to 13'.

The timing supplied during fault diagnosis of each logic unit 13 to 13' is, of course, the phase timing supplied during normal processing. Timing distribution circuits 12 to 12' are provided corresponding to each logic unit 13 to 13', and a timing generation circuit 11 that is mutually distal to these circuits is provided. From the timing generation circuit 11 to each timing distribution circuit 12~
Timings 14~ with different phases relative to 12'
14', and each evening timing distribution circuit 12-
A plurality of timing distribution lines 19-19' are provided from 12' to corresponding logic units 13-13'. Multiple timings 14-14' with different phases
is generated by the timing generation circuit 11 and supplied to the timing distribution circuits 12 to 12' corresponding to each logic unit.The timing distribution circuits 12 to 12' amplify the timing of each phase and then output the timing to the logic units 13 to 13'. supply to.

In the conventional timing control method, when suppressing timing supply, the control is commonly applied to each logic unit 13 to 13', but in the present invention, the timing distribution circuit 12 to 12' controls multiple lines 19 to 19. can be individually controlled via '. That is, the timing distribution circuits 12 to 12' are provided with a plurality of timing supply and inhibition control means, and these means distribute a plurality of timings to the logic units 13 to 13', for example, input flip and control means. The timing provided to the flop and output flip-flop can be controlled independently. FIG. 5 is a block diagram of the main parts of the timing distribution circuit in FIG. 4.

In FIG. 5, the timing T for one phase supplied from the timing generation circuit 11 is amplified by an AND gate 17 and becomes input to a plurality of AND gates 18 to 18'.

The timing distribution circuit 12 includes a plurality of timing supply and inhibit control means, that is, control flip-flops 15 to 15.
15' are provided, and or gates 16 to 16' are provided respectively.
The signal becomes an input to AND gates 18 to 18', is synchronized with the timing 20 supplied from the timing generation circuit 11, and is distributed to the logic unit LU. A control signal NOM, which is switched between normal processing and fault diagnosis, is input to the OR gates 16 to 16'.
The logical sum with the set output signals of flops 15 to 15' is broken. Note that the control flip-flops 15 to 15' are
It can be set to any value; when set to "1", timing is supplied; when set to "0", timing supply is suppressed. First, during normal processing, NO
Since the M signal is in the "1" state, the OR signal is
The output signals 21-21' of the gates 16-16' are all "
1". Therefore, AND gates 18-18'
becomes a conductive state, and the timing 20 supplied from the timing generation circuit 11 is constantly sent to the logic unit LU via the AND gates 18 to 18'. Next, when diagnosing a fault, the NOM signal is in the "0" state, so
The states of the output signals 21-21' of the OR gates 16-16' are determined by the respective output signals of the control flip-flops 15-15'.

Therefore, the control flip-flops 15-15' are
By controlling the timing tags to be in the "1" or "0" state, it becomes possible to send only an arbitrary timing tag out of the timings output from the AND gates 18 to 18' to the logic unit LU. If the logic unit LU includes an in-phase transfer circuit as shown in FIG.
Output timings of different AND gates among the in-phase timings outputted from 18' to 18' are respectively used.

If the AND gates 18 to 18' block the timing at which the data is supplied to the flip-flops other than the output flip-flops for diagnostic testing, the data supplied to the input flip-flops can be blocked. Since the acquisition timing is suppressed, the state of the input flip-flop does not change within the timing period, and the adverse effects of in-phase transfer can be prevented. Therefore, when diagnosing a fault, it is necessary to select a group of output flip-flops for a '1' diagnosis unit from within the same logic unit, and to set only the timing control flip-flops associated with the output flip-flops to a logic '1' state. If execution is performed according to the following two rules: 1), even if an in-phase transfer circuit exists, only the timing related to the output flip-flop will be supplied, so that the in-phase transfer will not affect diagnostic execution. In addition, in the example shown in FIG.
Flip-flops 15 to 15' for timing inhibition control are provided corresponding to all the timings supplied to the logic unit LU, but in order to reduce the number of components, one flip-flop has multiple flip-flops. It is also possible to allocate timing to control V supply and inhibition at the same time.

In this case, it is necessary to avoid assigning the timings supplied to the input flip-flop and output flip-flop, which form the in-phase transfer circuit, to the same control flip-flop. As explained above, according to the present invention,
Since timing supply and inhibition are controlled independently for each of the multiple logical units in which the information processing device is divided, data acquisition timing is no longer supplied to the input flip-flop and output flip-flop at the same time. , Therefore, the influence of in-phase transfer during diagnosis execution can be completely eliminated, and the creation of a diagnosis program can be simplified.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a circuit that divides the information processing device into diagnostic units, Fig. 2 is a flow chart showing the fault diagnosis procedure in Fig. 1, and Fig. 3 is an explanation showing the influence of in-phase transfer when performing diagnosis. 4 is a block diagram of the timing matching method of the information processing apparatus according to the present invention, and FIG.
FIG. 2 is a configuration diagram of main parts of the timing distribution circuit shown in the figure. 1: input flip-flop, 2: combinational circuit, 3: output flip-flop, 4: input signal group of combinational circuit,
5: Same output signal group, 6: Status output signal, 11: Timing generation circuit, 12 to 12': Timing distribution circuit,
13-13': Logic unit, 14-14': Timing lines of different phases, 15-15': Control flip-flop, 16-16': OR gate, 17, 18
~18': AND gate, 19~19': Timing distribution line, 20: Timing, 21~21': OR
Gate output, LU: logic unit, NOM: normal processing,
Fault diagnosis switching control signal, T: Timing. Figure 2 Figure 3 Figure 1 Figure 4 Figure 5

Claims (1)

[Claims] 1. In an information processing device that is divided into a plurality of logic units and each of the divided logic units performs logical operations in synchronization with timing of different phases, a plurality of timing distribution lines are provided for each logic unit, and each distribution An information processing device characterized in that means for independently controlling supply and suppression of timing is connected to each line.