JP2552180B2 - Switch control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application of the Present Invention> The present invention relates to a control device for a switching device that controls opening and closing of a plurality of switching devices provided between circuits based on a control signal.

<Prior art> (Figs. 11 to 14) For example, in a tester for an integrated circuit or the like, various signals are switched and input to an input terminal of a device under test, and the response is measured to determine whether or not the device under test Although the determination is performed, in such an apparatus, the switching control of the input signal to the device under test is often automatically performed by a preset control program.

For example, as shown in FIG. 11, in the control device that controls the opening and closing of the relays 3 and 4 provided between the two circuits 1 and 2, as shown in FIG. Data bus of CPU6 (DB1, DB
The signal output from 2} is directly sent to the relay drivers 7 and 8 as an open / close signal to control the open / close of the relays 3 and 4, and as shown in FIG. Data bus (DB1, DB
Temporarily store the signals of 2) in registers 9 and 10, respectively,
Conventionally, the stored output is sent as an open / close signal to the relay drivers 7 and 8 to control the open / close of the relays 3 and 4.

However, in the case of a mechanical switching device such as a relay, there is chattering and mechanical delay, and therefore a delay time is generated for the actual stable open / close state with respect to changes in the open / close signal.

For example, as shown in FIG. 13, when the open / close signal A ₁ for the relay 3 is switched from the closed level to the open level and the open / close signal A ₂ for the relay 4 is switched from the open level to the closed level, The contacts S ₁ and S ₂ of 3 and 4 are
From the rising edge of the opening / closing signals A ₁ and A _2, the state is closed with a delay of T1 including the chattering operation, and the closing state is opened with a delay of T2 from the falling edge of the opening / closing signal.

Therefore, when T2 is larger than the delay time T1, the two relays 3 and 4 are simultaneously turned on for the time corresponding to the difference, and when T2 is smaller than the delay time T1 for the time corresponding to the difference. The two relays are turned off at the same time.

However, the circuit 1 connected via the relays 3 and 4,
Depending on 2, the simultaneous ON state or the simultaneous OFF state may be inconvenient.

For example, when two signal sources from the circuit 2 are switched and input to the circuit 1, when the two relays 3 and 4 are simultaneously turned on, the two outputs of the circuit 2 are connected to each other.

At this time, when the output sources having a small output resistance such as a power supply device and a signal generator are used as the signal source, the two outputs of the circuit 2 become close to a chute and the circuit 2 itself is damaged or the relay 3 4, contact damage, etc. will occur.

In addition, when switching the attenuator to perform signal level sweep control, or when switching the frequency setting for the PLL circuit etc. to perform frequency sweep control, if the switch is turned off at the same time, there is no signal or a lock. Problems such as detachment occur.

Therefore, in the conventional control device, a standby state is provided in the control program to adjust the rising timing and on-time of the opening / closing signal so that the opening / closing control of the switching device is performed at the optimal timing for the circuit or the switching device, or As shown in FIG. 14, a series resistor R is inserted in each of the relays 3 and 4 so as to prevent damage to the circuit and relay contacts in the simultaneous ON state.

<Problems to be Solved by the Present Invention> However, in the method of adjusting the timing between the opening and closing signals by the control program as described above, the control takes the processing time into consideration, and a large number of switching devices are sequentially combined in different combinations. There was a problem that it took a very long time to turn it on.

Further, in such a control device, in addition to the control of the switching device, the control of the circuit connected via this switching device is also performed by this control program, and even if the control is in the same sequence, the type of switching device The control program has to be changed according to the above, and there is a problem that the program is not flexible.

In addition, in the method of inserting a series resistor in the switch, a large loss occurs when the resistance value is larger than the input / output resistance of the circuit due to the voltage drop of the resistance, and conversely when the resistance value is small, the signal source side The isolation may be insufficient and malfunction or damage may occur.

It is an object of the present invention to provide a control device for a switching device that solves the above problems.

<Means for Solving the Problems> In order to solve the problems, the control device for the first switching device of the present invention is the first device after a predetermined time from the time when the state of the control signal changes.
And a first pulse generation circuit for outputting the timing pulse of, and a second timing pulse before the generation of the first timing pulse at the time when the state of the control signal changes or after a predetermined time from this time. A second pulse generating circuit that outputs a third timing pulse during generation of the first timing pulse after a predetermined time has elapsed after outputting the second timing pulse; 2. Each time a third timing pulse is received, the logical state of the input signal is stored and held, and the held output is output as an open / close signal to the corresponding switching device. The control signal for the switch is provided in the closed state and the holding output of the memory circuit corresponding to the switch is in the closed state, or the control signal is in the closed state and has the first timing. Pulse is a plurality of logical operation circuit for outputting the operation output of the closed state of the (C ₁ ~C _n) as an input signal for the corresponding memory circuits while occurred.

Further, the control device for the second switching device of the present invention corresponds to this switching device while the control signal for the switching device is in the closed state, instead of the logical operation circuit of the control device for the first switching device. A plurality of logics for outputting the operation outputs (C _{1 to} C _n ) in the closed state as input signals to the plurality of storage circuits while the holding output of the storage circuit is in the closed state and the first timing pulse is not generated. Equipped with an arithmetic circuit.

Further, the control device for the third switching device of the present invention is provided corresponding to the plurality of switching devices, stores and holds the state of the control signal until the next state change, and holds the held logical state in the first state. A first memory circuit that outputs each as a holding output (D _{1 to} D _n ), a pulse generation circuit that outputs a timing pulse (P4) after a predetermined time from the time when the state of the control signal changes, and a plurality of switching devices. The logic state of the hold output of the first memory circuit, which is provided correspondingly, is stored and held each time the timing pulse is received, and the held logic state is stored in the second hold output (E ₁
To En _n ) respectively, and a second storage circuit provided corresponding to a plurality of switching devices, the first holding output corresponding to the switching devices is in a closed state, and the second holding output is closed. And a plurality of logical operation circuits that output a closed-state open / close signal to the switch during the state.

Furthermore, in the control device for the fourth switching device according to the present invention,
In place of the logical operation circuit of the controller of the switching device, the open / close signal of the closed state while the first holding output corresponding to the switching device is in the closing state or the second holding output corresponding to the switching device is in the closing state. , A plurality of logical operation circuits for respectively outputting to the switch.

<Operation> Therefore, in the control device for the first or second switching device, the change of the control signal from the open state to the closed state or the change from the closed state to the open state is delayed until the third timing pulse is generated. Transmitted to the switch.

Further, in the control device for the third or fourth switching device, the change from the open state to the closed state or the change from the closed state to the open state of the control signal is delayed until the timing pulse is generated and transmitted to the switch. Will be.

<First Embodiment of the Present Invention> (FIGS. 1 to 3) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a control device for a switching device according to a first embodiment. Control signals A _{1 to} A _n from a CPU or the like for a plurality of relays RL _{1 to} RL _n as switching devices and switching thereof. In response to the write signal W indicating the timing, the change of each control signal to the closed state (“H” level) is delayed and output to each relay.

In FIG. 1, reference numeral 11a denotes a first pulse generator which is composed of a monostable multi-circuit or the like, and outputs a first timing pulse of a predetermined width Tw1 _{one by one} after a predetermined time T ₁ each time the write signal W is received. Circuit.

Similarly, 11b is composed of a monostable multi-circuit, etc., and outputs one second timing pulse having a predetermined width Tw2 synchronized with the write signal W, and then generates the first timing pulse, that is, the write signal W. ₁ hour after receiving
It is a second pulse generation circuit that outputs one third timing pulse having the same width Tw2 as the second timing pulse after T ₂ time until T ₁ + Tw ₁ .

Each of these timing pulses is an "H" level pulse having the same logic as the closed state of the control signal.

Each of 12 _{1 to} 12 _n stores and holds the logical level of an input signal from a logical operation circuit 14 _{1 to} 14 _n described later each time it receives a second timing pulse and a third timing pulse, and the held output is held by an opening / closing signal B ₁ to
As B _n, each corresponding relay driver to the relay RL ₁ ~RL _n
It is a register that outputs via 13 _{1 to} 13 _n .

Reference numerals 14 _{1 to} 14 _n denote control signals corresponding to the relays RL _{1 to} RL _n , holding outputs of the registers, and the first pulse generation circuit 10 respectively.
With the output P1 of, the following logical operation for making i a value of 1 to n, Ci = Ai.Bi + Ai.P1 is performed by the two AND circuits 15 and 16 and the OR circuit 17, and the operation result is sent to the corresponding register. It is a logical operation circuit that outputs as an input signal of.

Next, the operation of the control device having the above configuration will be described with reference to the time charts of FIGS. 2 and 3.

FIG. 2 is a diagram showing the operation timing for one relay RLi. When the write signal W is input at t ₁ immediately after the control signal Ai changes to the closed state (“H” level) at t ₀ , In synchronization with this, a second timing pulse of "H" level is input from the second generation circuit 11 to the register 12i.

Since the output Bi of the register 12i before the time t ₁ is at the “L” level, the output Bi remains at the “L” level even when the second timing pulse is input at t ₁ .

If t ₂ at a first timing pulse T ₁ times after time t ₁ rises, since the logical product of the control signal Ai becomes "H" level of the closed state, the output Ci of the logical operation circuit 14i It becomes "H" level.

The first timing pulse is at "H" level T ₂ hours after t ₀ , and the third timing pulse is registered at T ₃
When input to 12i, the logic level (“H” level) of the output Ci of the logical operation circuit 14i is stored and held in the register 12i, and the hold output Bi is closed (“H” level) and relayed via the relay driver 13i. Is output to the relay RLi.

At t ₄ when the control signal Ai changes to the open state (“L” level), the output Ci of the logical operation circuit 14i becomes the “L” level, and immediately after that at t _{5 the} next second timing pulse to the register 12i. Is output, the holding output Bi becomes "L" level in the open state.

Therefore, the timing (t ₀
Hour, t ₄ o'clock and write signal input timing (t _1, o'clock t
Assuming that the time difference from the time of ₅ o'clock is very small, as shown in FIG. 3, the two control signals Ai and Aj change from the closed state to the open state and from the open state to the closed state at t ₁₀ respectively. In this case, the open / close signal Bi corresponding to the control signal Ai changes to the open state at t ₁₀ almost in synchronism with the control signal Aj.
The open / close signal Bj corresponding to is closed by a delay of approximately T ₂ hours.

The contacts of the relays RLi and RLj open and close later than the switching signals Bi and Bj due to chattering and mechanical delay, as shown by Si and Sj in FIG. 3, but there is a delay of T ₂ hours in the switching signal. Therefore, the simultaneous ON state does not occur.

When the control signal continuously reaches the closing level at t _{7 in} FIG. 2, the holding output Bi of the register 12i changes its control signal Ai to the open state (at t ₈ ) and The closed state will be maintained until the second timing pulse is input (at ₉ o'clock).

<Second Embodiment of the Present Invention> (FIGS. 4 to 6) In the above-described embodiment, the relays are prevented from being turned on at the same time in response to the control signals that change to mutually opposite levels in synchronization. but if you do not become a state of simultaneous off Conversely, using a logical operation circuit 20i shown in FIG. 4 in place of the logical operation circuit 14 ₁ to 14 _n of the embodiment.

This logical operation circuit 20i includes an OR circuit 21, an AND circuit 22.
And the inverter 23 performs the following logical operation Ci = Ai + Bi and outputs the operation result to the register 12i.

FIG. 5 is a timing chart showing the operation when the logical operation circuit 20i is used.

In FIG. 5, when the control signal Ai changes to the closed state at the time t _0, the operation output Ci also becomes the closed state synchronously, and the second time at the time t ₁ .
When the timing pulse of is input to the register 12i, the holding output Bi changes to the closed state.

This state is maintained while the control signal Ai is closed, and t ₂
Even if the control signal Ai is in the open state, the hold output Bi remains closed because the inverted output of the first timing pulse and the hold output Bi remain closed.

Here, t ₃ at the first timing pulse becomes closed state operation output Ci becomes an open state, at t ₄ the third timing pulse is output to the register 12i, a the holding output Bi is open state .

Therefore, it is assumed that the time difference between the timing when the state of the control signal changes and the input timing of the write signal W is very small as described above, and two control signals A as shown in FIG.
When i and Aj change from the closed state to the open state and from the open state to the closed state at t ₁₀ respectively, the two holding outputs Bi and Bj are relayed so that they overlap for T2 hours after t _10. It will be output to RLi and RLj, and its contact is S
As shown by i and Sj, switching is performed in the synchronous ON state.

<Third Embodiment of the Present Invention> (FIGS. 7 to 8) In the first and second embodiments, when the state change of the control signal is maintained until immediately before the next write signal is input. However, when the pulse width of the control signal is small and the state does not change to the opposite level in synchronization,
It is also possible to configure a control device as shown in FIG.

In FIG. 7, 31 _{1 to} 31 _n are first registers for storing and holding the states of the control signals A _{1 to} A _n for each input of the write signal W, and 32 _{1 to} 32 _n are the _first registers. Registers 31 _{1 to} 31 _n
Is a second register that stores and holds the logic states of the holding outputs D _{1 to} D _n of each of the timing pulses P4 from the pulse generating circuit 33.

The pulse generating circuit 33 is composed of a monostable multivibrator circuit such as to output a timing pulse having a predetermined width Tw4 after receiving write signal W after the predetermined time T ₄ at "H" level.

34 _{1 to} 34 _n are logical operation circuits composed of an AND circuit 35 and an OR circuit 36, and hold outputs D _{1 of} the first registers 31 _{1 to} 31 _n.
˜D _n and the logical outputs and logical sums of the holding outputs E _{1 to} E _{n of} the second registers 32 _{1 to} 32 _n are output.

37 _{1 to} 37 _n are logical product outputs of logical operation circuits 34 _{1 to} 34 _n F _{1 to} F _n
Is a mode selector switch that selectively outputs the output on either side of the logical sum output G _{1 to} G _n as an open / close signal, delays the change of the control signal to the closed state, or changes to the open state. The output on the side of the logical product or the side of the logical sum is selected by the mode signal M for setting whether to delay.

As shown in FIG. 8, when the write signal W is input at t _{1 with a} slight delay from the time t ₀ when the control signal Ai having a small pulse width changes to the closed state, the operation of this controller is as follows. holding the output Di of the first register 31i becomes a closed state, the timing pulse P4 o'clock t ₂ has elapsed T ₄ hours from time t ₁ is input to the second register 32i.

Therefore, the logical product output Fi of the logic circuit 34i is a closed state from the time the t ₂ until t ₃ when the next write signal W is input.

On the other hand, the logical sum output Gi is the holding output D of the first register 31i.
It is in the closed state from t ₁ when i is in the closed state to t ₄ when the holding output Ei of the second register 32i is in the open state.

If the logical product output Fi is selected in advance by the mode signal M, the change of the control signal from the open state to the closed state is delayed by about T ₄ and transmitted to the relay RLi. Similarly to the first embodiment, it is possible to prevent the relay contacts from being turned on at the same time.

In addition, if the OR output Gi is selected, the change from the closed state to the open state of the control signal is delayed by about T ₄ hours and relayed.
It will be transmitted to RLi, and it is possible to prevent the simultaneous OFF state of each relay contact.

<Other Embodiments of the Present Invention> (FIGS. 9 to 10) In the first to third embodiments, the logical operation circuit 1 is used.
Although AND circuits and OR circuits were used as 4, 20, and 36, for example, as shown in FIG. 9, control signal Ai, hold output
Bi, the first timing pulse P1 and the ROM circuit 40i whose address is the mode signal M corresponding to the two switching modes (simultaneous off mode, simultaneous on mode), and the logical level of the operation output Ci corresponding to these level states. If it is stored in advance as shown in FIG. 10, the switching control equivalent to the operation of the first and second embodiments can be easily performed only by inverting the logic level of the mode signal M.

Further, in the first to third embodiments, the output timing of each timing pulse is set based on the input timing of the write signal W input together with the control signal, but the state change of the control signal is directly changed. It is also possible to detect and set the output timing of each timing pulse based on this detection timing.

Although the first to third embodiments have described the case where the relay is used as the switching device, the present invention can be similarly applied to other switching devices such as an analog switch.

<Effects of the Present Invention> As described above, the controller of the switching device of the present invention, based on the configuration of the logical operation circuit and each timing pulse, changes the control signal from the open state to the closed state, or
Since it is configured to delay control the change of the open state from the closed state and give it to the switch, it is possible to prevent damage and malfunction of the circuit and the switch itself due to the simultaneous on state or the simultaneous off state of the switch, The switching control can be performed at the optimum timing.

In addition, the delay control by the program is not required, and even when controlling the switching of a large number of switches, it is possible to control in a very short time, and by adjusting the output timing of each timing pulse, the delay time for all the switches can be adjusted. Therefore, even if the type of the switch is changed, the control program of the same sequence can be used.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a timing chart diagram of each signal for one switching device of the first embodiment, and FIG. 3 is a first embodiment. It is a timing chart figure of each signal to two example changers. FIG. 4 is a circuit diagram showing only an essential part of the second embodiment of the present invention, FIG. 5 is a timing chart diagram of each signal for one switch of the second embodiment, and FIG. It is a timing chart figure of each signal with respect to two switching devices of a 2nd example. FIG. 7 is a circuit diagram showing a third embodiment of the present invention, and FIG. 8 is a timing chart diagram of each signal for one switching device of the third embodiment. FIG. 9 is a circuit diagram showing only an essential part of another embodiment of the present invention, and FIG. 10 is a correspondence diagram of data to addresses for explaining the operation of FIG. FIG. 11 is a circuit diagram showing a switching device connected between circuits,
12 (a) and 12 (b) are circuit diagrams showing a conventional device for the switch of FIG. FIG. 13 is a diagram showing an operation timing of a relay contact with respect to a control signal of the conventional device, and FIG. 14 is a circuit diagram showing an improved example of the simultaneous ON state of the conventional device. 11a ... 1st pulse generating circuit, 11b ... 2nd pulse generating circuit, 12 _{1 to} 12 _n ... register, 14 _{1 to} 14 _n , 20i ... logical operation circuit, 31 _{1 to} 31 _n ... 1 register, 32 _{1 to} 32 _n ...
… Second register, 33 …… Pulse generation circuit, 34 _{1 to} 34 _n ….
… Logical operation circuit, RL _{1 to} RL _n …… Relay.

Claims (4)

(57) [Claims] 1. A plurality of switching devices (RL _{1 to} R) provided between circuits.
In the control device of the switching device, which controls opening and closing of L _n ) based on the control signals (A _{1 to} A _n ) corresponding to each switching device, the first timing after a predetermined time from the time when the state of the control signal changes in the previous period. A first pulse generating circuit (11a) which outputs a pulse (P1), and a second timing before the generation of the first timing pulse at a time when the state of the control signal changes or a predetermined time after the time. A second pulse generation circuit (P2) is output, and a third timing pulse (P3) is output during the generation of the first timing pulse after a predetermined time has elapsed from the output of the second timing pulse ( 11b) and corresponding to the plurality of switches, each time the second and third timing pulses from the second pulse generating circuit are received, the logical state of the input signal is stored and held, and the held output corresponding to (B ₁ ~B _n) That a plurality of storage circuits for outputting as an opening and closing signal to the switch and (12 ₁ ~12 _n), provided corresponding to said plurality of switching devices, and said switch said control signal is a closed state with respect to the switching device While the holding output of the storage circuit corresponding to the closed state is in the closed state, or the control signal is in the closed state and the first timing pulse (P1) is generated, the calculation output of the closed state (C ₁ and a plurality of logical operation circuits respectively outputting a -C _n) as said input signal to said plurality of memory circuits, a change to the closed state from the open state of said control signal until said third timing pulse generator A switching device control device, which outputs delayed switching signals to each switching device. 2. A plurality of switching devices (RL _{1 to} R provided between the circuits.
L _n ) is a switching device control device that controls opening and closing based on control signals (A _{1 to} A _n ) corresponding to each switching device, and a first timing after a predetermined time from the time when the state of the control signal changes. A first pulse generating circuit (11a) which outputs a pulse (P1), and a second timing before the generation of the first timing pulse at a time when the state of the control signal changes or a predetermined time after the time. A second pulse generation circuit (P2) is output, and a third timing pulse (P3) is output during the generation of the first timing pulse after a predetermined time has elapsed from the output of the second timing pulse ( 11b) and corresponding to the plurality of switches, each time the second and third timing pulses from the second pulse generating circuit are received, the logical state of the input signal is stored and held, and the held output corresponding to (B ₁ ~B _n) That a plurality of storage circuits for outputting as an opening and closing signal to the switch and (12 ₁ ~12 _n), provided corresponding to said plurality of switch, the control signal for the switch is exchange between or該切the closed state A plurality of storage circuits corresponding to the operation outputs (C _{1 to} C _n ) in the closed state while the holding output of the storage circuit corresponding to the container is in the closed state and the first timing pulse (P1) is not generated. A plurality of logical operation circuits that respectively output as the input signals for the switch signals, and open / close signals obtained by delaying the change of the control signal from the closed state to the open state until the third timing pulse is generated. A controller for a switching device, which is characterized by outputting to 3. A plurality of switching devices (RL ₁ -R) provided between the circuits.
L _n ) is a switching device control device that controls opening and closing based on control signals (A _{1 to} A _n ) corresponding to each switching device, and is provided corresponding to the plurality of switching devices, and the state of the control signal The first control circuit (31 _{1 to} 31 _n ), which stores and holds the current state until the next state change, and outputs the held logical state as the first held output (D _{1 to} D _n ), respectively, and the control signal. Pulse generation circuit (33) that outputs the timing pulse (P4) after a predetermined time from the time when the state of
And a logical state of the holding output of the first storage circuit, which is provided corresponding to the plurality of switches, is stored and held each time the timing pulse is received, and the held logical state is held by the second holding output ( E ₁ and to E _n) is output as the second memory circuit (32 ₁ to 32 _n), provided corresponding to said plurality of switch, said first holding output closes corresponding to the switch And a plurality of logical operation circuits that output an open / close signal of the closed state to the switch while the second holding output corresponding to the switch is in the closed state, the open state of the control signal. A switching device control device, which outputs to each switching device an opening / closing signal obtained by delaying a change from a closed state to a closed state until the timing pulse is generated. 4. A plurality of switches (RL _{1 to} R) provided between the circuits.
L _n ) is a switching device control device that controls opening and closing based on control signals (A _{1 to} A _n ) corresponding to each switching device, and is provided corresponding to the plurality of switching devices, and the state of the control signal The first control circuit (31 _{1 to} 31 _n ), which stores and holds the current state until the next state change, and outputs the held logical state as the first held output (D _{1 to} D _n ), respectively, and the control signal. Pulse generation circuit (33) that outputs the timing pulse (P4) after a predetermined time from the time when the state of
And a logical state of the holding outputs (D _{1 to} D _n ) of the first memory circuit, which are provided corresponding to the plurality of switches, are stored and held each time the timing pulse is received, and the held logical state is stored. and the second holding output (E ₁ to E _n) respectively output second memory circuit as (32 ₁ to 32 _n), provided corresponding to said plurality of switch, the first corresponding to the switch A plurality of logical operation circuits that output an open / close signal in the closed state to the switch while the hold output is in the closed state or while the second hold output corresponding to the switch is in the closed state, A switching device control device, which outputs an opening / closing signal obtained by delaying a change of the control signal from a closed state to an open state until the timing pulse is generated, to each switching device.