JPS6210389B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device that is capable of shortening test time when performing functional tests of various parts.

Functional testing of semiconductor integrated circuit devices such as a single-chip CPU has become increasingly complex due to the diversification and higher integration of circuit devices.

FIG. 1 is a block diagram showing the configuration of a CPU as an example of a conventional semiconductor integrated circuit device. In the figure, a bus buffer 1 activates an external circuit connected to the outside of the CPU, and also switches data input/output to and from an internal bus line 2 and an external buffer line 3, respectively. Further, a memory 4 consisting of ROM and RAM is connected to the internal bus line 2. The program counter (PC) 5 specifies the address of the memory 4 mentioned above.
Determine the CPU execution address. An arithmetic unit (ALU) 6 performs arithmetic and logical operations on the contents of an A register (AR) 7 and a B register (BR) 8 connected to the internal bus line 2, respectively. The timing signal generation circuit 9 generates timing signals for controlling the bus buffer 1, memory 4, PC5, ALU6, AR7, and BR8, respectively, based on the clock pulse CP supplied from the outside, and also connects to the outside of the CPU. It sequentially generates timing signals to control the memory, etc.

Here, the operation of the conventional CPU configured as described above when testing whether the data stored in the ROM area of the memory 4 is correct will be described. However, in this case, as a prerequisite for the test, the RAM area of memory 4 contains
It is assumed that a group of instructions necessary to read data stored in the ROM area are stored in advance. First, as shown in Figure 2, the clock pulse CP
is input to the timing signal generation circuit 9, the PC
A timing signal is sent to PC 5, after which the PC 5 stores the ROM data read command in memory 4.
Specify the address P of the RAM area. Then, the next clock pulse CP is generated by the timing signal generation circuit 9.
, a timing signal is sent to the memory 4, and then the memory 4 reads out the data I in the RAM area designated by the address P. The read data I is then sent to the internal bus line 2. Yet another clock pulse
When CP is input to the timing signal generation circuit 9,
The timing signal is sent to PC5 again, and then the PC
5 sets the above data I and specifies the address I of the ROM area. When the next clock pulse CP is input to the timing signal generation circuit 9, the timing signal is again sent to the memory 4, and after this, the memory 4 is designated by the above address I.
Read data R in the ROM area. This read data R is then sent to the internal bus line 2. Further, this data R is then sent to the outside via bus buffer 1 and external bus line 3, and tested to see if it is correct data. Thereafter, data in the ROM area is sequentially read out and sent to the outside in the same manner, thereby testing the memory 4.

By the way, in the conventional CPU mentioned above, it takes a clock pulse CP to read one piece of data from the memory 4.
must be entered four times. That is, a four-step sequence is required to test one piece of data in the memory 4, and the test time becomes longer as the amount of data in the ROM area increases. Also, not only memory 4 but also ALU6
When testing, the necessary data is first stored in the memory 4, and then the arithmetic instructions of the ALU 6 are executed, which increases the number of test steps and increases the test time. Become.

This invention has been made in consideration of the above circumstances, and its purpose is to provide a semiconductor integrated circuit device that can shorten test time by reducing the number of test steps during a functional test. .

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block configuration diagram when the semiconductor integrated circuit device of the present invention is implemented in a one-chip CPU, and portions corresponding to those of the conventional device are given the same reference numerals. The basic difference between this embodiment circuit and the conventional circuit is that the timing signal generation circuit 9
From bus buffer 1, memory 4, PC5, AR7,
Each data multiplexer 10-14 is inserted in each path of the timing signal sent to each BR8, and the timing signal from the timing signal generation circuit 9 is supplied to one input terminal of each of these data multiplexers 10-14, and the timing signal is supplied to the other input terminal. By supplying other timing signals, the bus buffer 1 or
Each BR8 is operated by two systems of timing signals. In the diagram, the terminal
Mode selection signals MS ₀ and MS ₁ for selecting the test mode of this CPU are supplied to T ₁ and T ₂ , respectively, and both signals are sent to the decoder 1.
Sent to 5. The decoder 15 selects a non-test mode, a ROM test mode for the memory ₄ , and a ROM test mode for the memory 4, depending on the level states of the mode selection signals MS 0 and MS ₁ .
It selects four modes: RAM test mode and ALU test mode. When non-test mode is selected, mode signal M _NORM is selected, when ROM test mode is selected, mode signal M _ROM is selected, and when RAM test mode is selected, mode signal M NORM is selected. When the M _RAM selects the ALU test mode, the mode signal M _ALU is set to a high level. The mode signal M _NORM is sent to the control end of each of the data multiplexers 10, 12-14. The mode signal M _ROM is sent to the OR gate 16, and the mode signal M _RAM is sent to the OR gate 16, the control end of the data multiplexer 11, the AND gate 17, and the inverter 18, respectively. The output signal of the OR gate 16 is sent to the AND gate 19. Further, the mode signal M _ALU is sent to AND gates 20 and 21. The timing signal T _A generated by the timing signal generation circuit 9 is applied to one input terminal of the data multiplexer 10, and the timing signal T _B is applied to one input terminal of the data multiplexer 11.
The timing signal T _C is connected to one input terminal of the data multiplexer 12, the timing signal T _D is connected to one input terminal of the data multiplexer 13, and the timing signal T _E is connected to one input terminal of the data multiplexer 13.
are respectively sent to one input terminal of the . Further, the timing signal T _F for bus input/output switching generated by the timing signal generation circuit 9 is the mode signal M _{N
The ORM} is output to the outside from the terminal _T3 via the tri-state buffer 22 inputted to its control terminal, and a timing signal for switching input/output of the internal bus line ₂ from the outside is output to the terminal T3.
Tf is supplied, and this timing signal Tf is sent to the other input terminal of the data multiplexer 10 via the buffer 23. Furthermore, the timing signal T _G for external memory control generated by the timing signal generation circuit 9 is transmitted to a terminal via a tri-state buffer 24 to which an inverted signal of the mode signal M _RAM by the inverter 18 is input.
This terminal T ₄ is output externally from T ₄ .
is supplied with a timing signal Tg for controlling the memory 4 inside the CPU from the outside, and this timing signal Tg is sent to the AND gate 17 via the buffer 25, and further to the AND gate 1.
The output signal of 7 is sent to the other input terminal of the data multiplexer 11. Similarly, the timing signal T _H for external memory set generated by the timing signal generation circuit 9 is transmitted to the tri-state buffer 26 to which the mode signal M _NORM is input to the control terminal.
It is output to the outside from _{terminal T5} via
Timing signal to control AR7 and BR8
Th is supplied, and this timing signal Th is passed through a buffer 27 to the three AND gates 19 to 2.
1 and the clock edge of the D-type flip-flop 28. The output signal of the flip-flop 28 is supplied to the data input terminal, and its Q output signal is inverted every time the timing signal Th is sent. The Q output signal of the flip-flop 28 is sent to the AND gate 21. A clock pulse CP is also supplied to the terminal _T6 from the outside, and this clock pulse is sent to the timing signal generating circuit 9. And the above AND gate 17, 19, 20,
Each output signal of 21 is sent to the data multiplexer 11~
14, and each output signal of the data multiplexers 10-14 is sent to the bus buffer 1, memory 4, PC5, AR7, and BR8, respectively.

Next, the operation of the apparatus configured as described above will be explained. First, a clock pulse CP is supplied to the terminal _T6 in advance, and when this is input to the timing signal generating circuit 9, the timing signal generating circuit 9 generates timing signals T _A to T _H according to predetermined timing. In order to operate the CPU normally in this state,
Two mode selection signals supplied to terminals T ₁ and T ₂
Set both MS ₀ and MS ₁ levels to low level. When the signals MS ₀ and MS ₁ are both set to low level, the decoder 15 selects the non-test mode and sets only the mode signal M _NORM to high level.
When the mode signal M _NORM is set to a high level, the four data multiplexers 10, 12, 13, and 14 to which this signal M _NORM is input to their control terminals each receive a timing signal T _A generated by the timing signal generation circuit 9. , T _C , T _D , and T _E are selectively output.
Also, the mode signal M which is at a low level at this time
The data multiplexer 11 to which _{the RAM} is input at its control end also selectively outputs the timing signal T _B generated by the timing signal generation circuit 9. Furthermore, at this time, the two tri-state buffers 22 and 26 to which the high-level mode signal M _NORM is input to their control terminals and the tri-state buffer 24 to which the output signal of the inverter 18 is input are activated. The timing signals T _F , T _G , T _H generated by the timing signal generation circuit 9 are as follows.
The signals are output to the outside via terminals T ₃ , T ₄ and T ₅ , respectively. As a result, each data multiplexer 10~
14 output signals, that is, timing signals T _A to _{T E}
input bus buffer 1, memory 4, PC 5,
AR7 and BR8 will perform normal operation.

Next, when performing a ROM test to determine whether the data stored in the ROM area of the memory 4 is correct, the mode selection signal MS ₀ is set to a low level and the mode selection signal MS ₁ is set to a high level. In this setting state, the decoder 15 selects the ROM test mode and sets only the mode signal _{M_ROM} to a high level. When this mode signal M _ROM is set to a high level, one input signal of an AND gate 19 becomes a high level through an OR gate 16, and this AND gate 19 is opened. Also at this time, the mode signal M _NO
Since _RM is at a low level, the data multiplexer 10 selectively outputs the timing signal Tf supplied to the terminal _T3 . In this state, first, supply the timing signal Tf to the terminal _T3 to switch the bus buffer 1 to the data input side, and
As shown in FIG. 4, an arbitrary address I in the ROM area is supplied to the external bus line 3, and then the terminal _T5
A timing signal Th is supplied to. At this time, as mentioned above, the AND gate 19 is open, so
The signal Th is input to the data multiplexer 12 via this AND gate 19. Furthermore, at this time, since the mode signal M _NORM input to the control terminal of the data multiplexer 12 is at a low level, the data multiplexer 12 selects the timing signal Tf and outputs it to the PC 5. When the above signal Tf is input, PC5 outputs internal bus line 2.
, that is, the above address I is set.
Then, at the timing of the next clock pulse CP, memory 4 is specified by the above address I.
Read data R in the ROM area. This read data R is then output to the internal bus line 2. Then, by supplying the timing signal Tf to the terminal _T3 , the bus buffer 1 is switched to the data output side, and the data R is outputted to the outside. Thereafter, it is determined whether this data R is correct data or not outside the CPU.

In this way, read data from the ROM area of memory 4 and determine whether the data is correct or not.
In the case of ROM testing, the ROM area is operated independently without reading the data in the RAM area as in the past, so to read one piece of data, you only need to input the clock pulse CP twice. The number of test steps can be reduced from the conventional 4 steps to 2 steps. Therefore, the time required for the ROM test can be significantly reduced compared to the conventional method.

When testing the ALU 6, both mode selection signals MS ₀ and MS ₁ are set to high level. In such a setting state, the decoder 15
Select the ALU test mode and set only the mode signal M _ALU to high level. When this mode signal M _ALU is set to high level, two AND gates 2
0 and 21 both open. Also, at this time, since the mode signal M _NORM is at a low level as described above, the data multiplexer 10 selectively outputs the timing signal Tf supplied to the terminal _T3 . In this state, first connect the timing signal Tf to the terminal.
T ₃ is supplied to switch the bus buffer 1 to the data input side, and data D ₁ is supplied to the external bus line 3 as shown in FIG _.
A timing signal Th is supplied to. At this time, as mentioned above, since the AND gate 20 is open,
The signal Th is input to the data multiplexer 13 via this AND gate 20. Furthermore, at this time, since the mode signal M _NORM input to the control terminal of the data multiplexer 13 is at a low level, the data multiplexer 13 selects the timing signal Th and outputs it to the AR7. When the signal Th is input, AR7 sets data _D1 on internal bus line 2. On the other hand, when the above Th is input, the Q output signal of the flip-flop 28 rises to a high level. After the AR7 sets the data _D1 , it supplies another data _D2 to the external bus line 3, and also supplies the timing signal Th to the terminal _T5 once again. At this time, the Q output signal of the flip-flop 28 is at a high level, the mode signal M _ALU is also at a high level, and the AND gate 21 is open, so the signal Th
is input to the data multiplexer 14 via this AND gate 21. At this time, the mode signal M _NORM input to the data multiplexer 14 is at a low level, so the data multiplexer 14 selects the timing signal Th and BR
Output to 8. When the above signal Th is input, BR8
sets data _D2 on internal bus line 2.
As a result, data D ₁ and D ₂ are set in AR7 and BR8. Then, at the timing of the next clock pulse CP, if the ALU 6 is under addition operation control, the ALU 6 adds the above two data D ₁ and D ₂ . This added data _D3 is then output to the internal bus line 2. And after this, the terminal
By supplying the timing signal Tf to _T3 , the bus buffer 1 is switched to the data output side, and the data _D3 is outputted to the outside. Then, it is determined externally whether this data _D3 is correct data.

ALU that tests the calculation operation of ALU6 in this way
Even in the case of testing, without operating the memory,
Since the AR7, BR8, and ALU6 are operated independently, the number of test steps is only three, and the time required for the test can be significantly shortened compared to conventional methods.

Also test the RAM area of memory 4, i.e.
When performing a RAM test, the mode selection signal
The process starts by setting MS ₀ to a high level and MS ₁ to a low level, but their explanation will be omitted.

In this way, in the above embodiment, only the parts of the CPU to be tested are operated independently by timing signals from the outside, so the number of test steps can be reduced and the test time can be shortened. becomes possible.

FIG. 6 is a block diagram showing the structure of another embodiment of the invention. In the above example, non-test, ROM
We have explained the case where the CPU is provided with special terminals T ₁ and T ₂ for selecting each test mode of test, _RAM test, and ALU test. ₁ may be sent to the decoder 30 via the bus lines 3 and 2. However, in this case, the decoder 30 receives the above two signals MS ₀ ,
It is necessary to provide a storage section for temporarily storing MS ₁ , and it is also necessary to provide a control terminal _Tx for controlling this storage section. If the bus lines 3 and 2 are used in this manner, the effect of reducing the number of terminals when the number of test modes increases is extremely large.

The present invention is not limited to the embodiments described above; for example, in the embodiments described above, a CPU is used as a semiconductor integrated circuit device, but it goes without saying that this invention can be applied to any other device. do not have.

As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit device that can reduce the number of test steps during a functional test and shorten the test time.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional CPU, Figure 2 is a block diagram of a conventional CPU.
3 is a block diagram showing an embodiment of the semiconductor integrated circuit device according to the present invention, and FIGS. 4 and 5 are timing charts showing the operation of the device of the above embodiment, respectively. , FIG. 6 is a block diagram showing another embodiment of the present invention. 1...Bus buffer, 2...Internal bus line, 3...
External bus line, 4... Memory, 5... Program counter (PC), 6... Arithmetic circuit (ALU), 7... A register (AR), 8... B register (BR), 9... Timing signal generation circuit, 10 to 14... Data multiplexer, 15...decoder, 16...or gate,
17, 19, 20, 21...and gate, 18...
Inverter, 22, 24, 26... tri-state buffer, 23, 25, 27... buffer, 28...
D-type flip-flop, 30...decoder, T ₁ ~
T ₆ , T _X ...terminals.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device having a plurality of functional units that sequentially operate in response to each timing signal generated by a timing signal generation unit, a signal selection circuit is provided in each of the timing signal supply paths to each of the plurality of functional units, A semiconductor integrated circuit device characterized in that a timing signal is supplied from the outside to each of the signal selection circuits, and each of the functional sections is operated independently by the timing signal.