JP2552827B2 - Output correction device for stepwise data - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] In the present invention, for example, in a frequency meter or a liquid level meter, the measurement result to be recorded becomes stepwise as in the case of recording the measurement result at predetermined time intervals. The present invention relates to an output correction device that corrects the output of a continuous envelope.

[Outline of Invention]

In the present invention, each sample value of the stepwise data and the data one sample before are subtracted, and the tendency when continuously changing from the data one sample before to the sample data is estimated based on the subtraction result. In this way, output data that continuously changes from the data one sample before to the data is obtained.

[Conventional technology]

For example, there is a frequency meter as shown in FIG. 5 as a frequency meter for measuring a signal frequency which changes every moment.

That is, in the figure, (2) is a counter, and a pulse whose frequency changes from moment to moment is supplied to the counter (2) through the input terminal (1) and counted. The output count value of the counter (2) is supplied to the latch circuit (3).

On the other hand, the pulse generator (7) obtains a pulse having a period T to be measured, for example, a one-second period, which triggers the monostable multivibrator (8), which produces a latch pulse L ₁ (Fig. 6A). To be Then, the count value of the counter (2) is latched in the latch circuit (3) by the latch pulse L ₁ .

The latch pulse L ₁ is also fed to and triggered by the monostable multivibrator (9), from which the latch pulse
A delayed pulse L ₂ (FIG. 6B) is obtained from L ₁ , which resets the counter (2). Therefore,
After the counter (2) is reset, the latch circuit (3) latches the count value immediately before being reset. The count value is the number of input pulses included in the latch cycle T. Yes, this represents the frequency of the input pulse within its period T without re-acquisition.

The output CO of the latch circuit (3) is updated in the cycle T by the pulse L _{1 and} therefore becomes stepwise data as shown in FIG. 6C. Therefore, the output CO is D / A converted by the D / A converter (4), and the analog output also has a stepwise shape, which is passed through the low-pass filter (5) to smooth the stepwise deformation so that the change is not stepwise. It is made to have a continuous waveform and is led to the output terminal (6).

Then, the analog output voltage obtained at the output terminal (6) is recorded on, for example, a recording paper.

[Problems to be solved by the invention]

As described above, if the stepwise data is recorded as it is on the recording paper, step changes will be noticed and it will be difficult for the user to handle the recording.Therefore, the waveform will be corrected and output as a continuous waveform without step changes and output. It is common to record.

In the example of FIG. 5, the waveform is corrected by the low pass filter.

However, the one using this low-pass filter has a drawback that the response is slow because of the time constant.

[Means for solving problems]

The present invention proposes an output correction device having a fast response. In the present invention, first latch means (13) for fetching input data at predetermined intervals and fetched by the first latch means (13). Subtraction circuit (1) for calculating the difference between the data of the second latch means (14) for fetching the immediately preceding data and the data of the first and second latch means (13) (14).
5) and the value is continuously changed from the data value of the second latch means (14) toward the data value of the first latch means (13) according to the subtraction result from the subtraction circuit (15). Means (16) (17) (18) are provided.

[Action]

An output for continuously changing the value from the data value one sample before from the second latch means (14) toward the data value at that time of the first latch means (13) is obtained, and the correction with fast response is obtained. Output is obtained.

〔Example〕

FIG. 1 shows an embodiment of the device of the present invention, which is an example when applied to a frequency meter as in the case of FIG.

That is, the input pulse whose frequency changes every moment through the input terminal (11) is supplied to the counter (12) and counted. The count value output is supplied to the storage register (13). Further, the output of this storage register (13) is supplied to the storage register (14).

On the other hand, a pulse of the measurement cycle T is obtained from the pulse generator (22), and this pulse is a monostable multivibrator (23).
To obtain a pulse P ₀ (FIG. 2A), and this pulse P ₀ is delayed by the monostable multivibrator (24) to obtain a pulse P ₁ (FIG. 2B). This pulse P ₁ is delayed by the monostable multivibrator (25) to obtain the pulse P ₂ (FIG. 2C). Then, the pulse P ₀ is transferred to the storage register (14) and the pulse P ₁
Is supplied to the storage register (13) as a latch pulse, and the pulse P ₂ resets the counter (12).

Therefore, the storage register (13) stores the count value immediately before the counter (12), which is the number of input pulses in the measurement cycle T, is reset, and the storage register (14) stores the count value of the register (13). The count value one sample before is taken in.

Output data value M ₁ of storage register (13) (see FIG. 2D) and output data value M ₂ of storage register (14)
(Refer to E in the figure) is supplied to the subtractor (15),
In this, a subtraction of M ₁ −M ₂ is performed, and its absolute value S =
| M ₁ −M ₂ | and the signal POL indicating the positive and negative polarities of the subtraction result are obtained from this.

Then, the absolute value S of the difference is supplied to the frequency changing means (16), and the frequency of the clock from the oscillator (17) is the absolute value S.
It is changed according to the size of. That is, the larger the value S, the higher the frequency. This frequency changing means (16) may use a multiplication circuit, or
A frequency dividing circuit may be used and the frequency dividing ratio may be changed according to the absolute value S. A microcomputer can also be used, in which case an oscillator (17) and frequency changing means (1
6) may be integrally configured, the period T may be divided into a number corresponding to the absolute value S, and the number may be converted into a frequency.

The clock CP from the frequency changing means (16) is supplied to the clock terminal of the up / down counter (18). On the other hand, when the signal POL indicating the polarity from the subtractor (15) is supplied to the up / down control terminal of the up / down counter (18) and the signal POL indicates "positive", the counter (18) is up. When the count and signal POL indicate "negative", the counter (18) is in the down count state.

The output data value of the register (14) is preset in the counter (18) at the time of the pulse P ₀ . That is, at the same time that the data is taken into the register (14),
The fetched data value M ₂ is preset in the counter (18).

Accordingly, the counter (18) counts up or down counts the clock CP toward the data value M ₁ at that time from the data value M ₂ (equal to the next data value M _2).
In this case, the frequency of the clock CP is sufficiently higher than the output pulse of the pulse generator (22), and after the lapse of the period T, the count value of the counter (18) started from the value M ₂ is just the value. Of course, the frequency is selected to be M ₁ .

However, even if the frequency of the clock CP is not exactly such a frequency, the data value M ₂ of the register (14) is preset in the counter (18), so that the frequency error is not accumulated. .

That is, in principle, it is not necessary to preset the counter (18), and it is sufficient to sequentially count up and down from the initial value. But the clock CP as described above
Since it is difficult to accurately select the frequency of, the error will accumulate if it remains as it is, and the data value will not change correctly from M ₂ to M ₁ . However, in this example, the counter (12) is always added to the initial data value M ₂ in the cycle every cycle T.
Since we preset, there is no such error accumulation.

In the example of FIG. 1, since the clock CP has a constant frequency during the initial T, the rising or falling is linear,
The frequency may be changed within the period T to increase or decrease in a curve.

As described above, the count value of the counter (18) changes as shown by the broken line in FIG. 2E. This count value output is converted into an analog voltage AO (Fig. 2F) in the D / A converter (19), and this voltage AO is converted into an amplifier (2
It is led to the output terminal (21) through 0) and the waveform of this voltage AO is recorded on the recording paper.

By the way, the example of FIG. 1 can be realized by a microcomputer, and in that case, a D / A converter (1
All the circuit parts except 9) and the amplifier (20) can be realized by microcomputer software. Then, in that case, a digital value that changes with a slope according to the absolute value of the difference can be obtained as an output by the calculation means, and the same operation as described above can be performed only by D / A converting this. is there.

FIG. 3 shows another example of the device of the present invention, which is an example in which the present invention is applied to the output correction of the cycle detecting device.

That is, in FIG. 3, (30) is an integrator, and its output VO ₁ is the input voltage VI of the terminal (31) to the resistor (32).
A voltage obtained by integrating the constant current I divided by is obtained. The switch circuit (34) connected in parallel to the integrating capacitor (33) is for resetting. When the switch circuit (34) is turned on, the integrated output VO ₁ is reset and the current I is integrated again from zero. It Therefore, this switch circuit (3
If the cycle in which 4) is reset is long, the integrated output VO ₁ will be high, and if the cycle is short, the integrated output VO ₁ will be low.

In this example, this is used to detect the cycle, and the input pulse SI ₀ (FIG. 4A) whose cycle changes momentarily through the input terminal (35) is applied to the monostable multivibrator (3
6) is delayed to obtain pulse SI ₁ , this pulse SI ₁ is delayed by monostable multivibrator (37) to obtain pulse SI ₂ , and this pulse SI ₂ is further added to monostable multivibrator (38 ), A pulse SI ₃ is obtained. Then, the delay pulse SI ₃ is supplied to the switch circuit (34) and the switch circuit (34) is turned on during the pulse width period. Therefore, the switch circuit (34) is turned on in the cycle of the input pulse SI ₀ , the integrator (30) is reset, and the integrated output voltage VO ₁ has a sawtooth-shaped peak value corresponding to the cycle of the input pulse SI _0. Waves are obtained (Fig. 4B).

The output voltage VO ₁ immediately before the integrator (30) is reset, that is, the peak value of the output voltage VO ₁ is the pulse SI.
_{When the} switch circuit (39) is turned on by ₂ , the sample is held in the capacitor (40). Therefore, as shown in FIG. 4C, the pulse S for inputting the peak value of the sawtooth wave voltage VO ₁ as the output M ₁ ′ of the operational amplifier (41).
The voltage sampled and held in the cycle of I ₀ is obtained.

Further, the output M ₁ ′ is sampled and held by the pulse SI ₁ in the sampling and holding circuit composed of the switch circuit (42) and the capacitor (43). Therefore, as the output M ₂ ′ of the operational amplifier (44), as shown in FIG. 4D, the value of the output M ₁ ′ immediately before it is sampled and held (that is, the value one sample before) is changed by the pulse SI _1. The sampled and held voltage is obtained.

The output M ₁ ′ of the operational amplifier (41) is supplied to the inverting input terminal of the operational amplifier (45) via the resistor (46), and the output M ₂ ′ of the operational amplifier (44) is non-inverted of this operational amplifier (45). It is supplied to the input terminal. A resistor (47) is placed between the output terminal and the inverting input terminal of this operational amplifier (45).
Is connected. In this case, if the resistors (46) and (47) are selected to have the same value, the operational amplifier (45) performs an operation of 2M ₂ ′ −M ₁ ′, and the operation result is the diode (48) and the switch circuit. It is supplied via a resistor (52) to an inverting input terminal of an operational amplifier (51) which constitutes an integrator (50) via a parallel circuit of (49). On the other hand, the output M ₂ ′ of the operational amplifier (44) is the operational amplifier (5
It is supplied to the non-inverting input terminal of 1).

Further, a preset switch circuit (54) is connected in parallel with the integrating capacitor (53), and the switch circuit (5
4) is turned on by pulse S ₁ . When the switch circuit (54) is turned on, the output of the integrator (50) is preset to the output M ₂ ′ of the operational amplifier (44).

Then, in the integrator (50), the operational amplifier (51)
Potential difference between the two input terminals, that is, (2M ₂ ′ −M ₁ ′) −M
_{2 '= M 2' -M 1} ' to from would be integrating the divided by current resistor (52), the preset value M _2' will be integrated from towards M ₁ 'is made.

By the way, the output M ₂ ′ is a value one sample before the output M ₁ ′, but since the period of the input pulse SI ₀ is different, the hold times of the corresponding values of both outputs are clear from FIGS. 4C and 4D. So different. Therefore, the integrated output VO of the integrator (50)
_{When 2} rises toward the output M ₁ ′, this value M ₁ ′
May exceed. Therefore, in this example, the integrated output VO ₂ and the output M ₁ ′ of the operational amplifier (41) are compared (5
When the integrated output VO ₂ exceeds the output M ₁ ′, the switch circuit (49) is turned off by the output of the comparison circuit (55). Then, at this time, the diode (4
8) is off, the integration operation is interrupted and the integrated output VO ₂
Is held at a value equal to the output M ₁ ′.

Even if the integrated output VO ₂ is larger than the output M ₁ ′, if the integrated output VO ₂ drops, the diode (48)
Is on, the integration operation is performed.

When the pulse SI ₁ arrives before the integrated output VO ₂ reaches the output M ₁ ′, the integrated output VO ₂ is preset to the output value M ₂ ′ at that pulse.

Thus, the output VO ₂ of the integrating circuit (50) is shown in FIG.
As shown in, an output whose value continuously changes in response to the stepwise output M ₁ ′ is obtained.

When recording on recording paper, this integrated output VO ₂ is supplied to the division circuit (56), the reciprocal thereof is calculated, the periodic output is converted into a frequency output, and this frequency output is converted into a frequency voltage conversion circuit (5
7) to obtain a voltage output, which is output terminal (58)
To be recorded on a recording paper.

〔The invention's effect〕

As described above, according to the present invention, the staircase data can be corrected to an output that continuously changes in response to this.

Moreover, since this corrected output changes from the data value of one sample before, toward that data value, the response is very fast.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of the invention device, FIG. 2 is a time chart for explaining the same, FIG. 3 is a block diagram of another example of the invention device, and FIG. 4 is a time chart for explaining the same. A chart, FIG. 5 is a block diagram of an example of a conventional device, and FIG. 6 is a time chart for the explanation. (13) is a storage register as a first latch means, (14) is a storage register as a second latch means, and (15) is a subtraction circuit.

Claims (4)

(57) [Claims] 1. A first latch means for fetching input data at predetermined intervals, a second latch means for fetching data immediately before the data fetched by the first latch means, and the first and the second means. A subtraction circuit for calculating a difference between the data of the second latch means, and a data value of the second latch means continuously from the data value of the second latch means in accordance with the subtraction result from the subtraction circuit. An output correction device for stair-step data, which comprises a means for changing the value. 2. The means for continuously changing the value is preset with the data value of the second latch means, the output value of the subtracting means is integrated, and the preset value is used for the first latch means. The output correction device for stepwise data according to claim 1, comprising an integrating circuit for obtaining an output toward a data value. 3. The means for continuously changing the value comprises a variable frequency generating means, a counter, and a D / A converter, and in the variable frequency generating means, the output frequency of the clock signal is the output of the subtraction circuit. According to
The output correction device for staircase data according to claim 1, wherein the clock signal is supplied to the counter, and the count value output of the counter is converted into analog data by a D / A converter. 4. The means for continuously changing the value comprises an operation means and a D / A converter, and the operation means outputs a digital value which changes with a slope according to the output of the subtraction circuit, The output correction device for stepwise data according to claim 1, wherein the output value is converted into analog data by the D / A converter.