JPH0412430B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Technical Field] The present invention relates to a digital voltage change rate measuring device that measures the change value of a detected voltage per unit time, and in particular, a measurement unit time scale that overlaps the previous voltage change rate by a predetermined time. This invention relates to a digital voltage change rate measuring device that measures the voltage change rate in real time. [Prior Art] Conventionally, as a voltage change rate measuring device for measuring the rate of change in a detection voltage that fluctuates over time obtained from a detector such as a water level meter, a device as shown in Fig. 2 has generally been used. ing. This is a differential amplifier circuit using an operational amplifier, in which a capacitor C is connected in series to the negative input terminal of the operational amplifier AM, and a resistor R is connected in parallel to the output of the operational amplifier AM. The rate of change of the detected voltage continuously appears in the output voltage as its differential value. [Problems to be Solved by the Invention] However, the differential amplifier circuit using such an operational amplifier has the following problems. In principle, due to the frequency characteristics of the differential amplifier circuit, the differential amplifier circuit exhibits differential characteristics only in the range below the frequency f=1/2πCR, and is unable to capture steep changes in the detected voltage. If the differential time constant CR is set long, problems will arise in the input characteristics and drift characteristics of the operational amplifier AM, and leakage of the capacitor C will occur, making it extremely difficult to realize a high-quality differential amplifier circuit due to its configuration. Calibration of analog circuits is generally difficult, inaccurate, and unreliable. On the other hand, a digital technique is known in which the detected voltage is sampled and measured at predetermined time intervals, temporarily stored, and the difference value between the previous measurement value and the current measurement value is obtained in time series. However, if the sampling interval is set long in such a technique, no knowledge can be given of the rate of voltage change between sampling points. That is, it is not possible to obtain a real-time voltage change rate. Therefore, in this case,
Normally, it is limited to measuring changes in detected voltage that occur slowly over time. Conversely, if the sampling interval is set short, the measured values will have a large standard deviation when the detected voltage is relatively low, resulting in poor accuracy and lack of reliability. Since there is uncertainty in either case, it is necessary to consider the characteristics of the detected voltage in advance and then set the optimum unit time. However, this setting is extremely difficult, and even if the setting is done well, the characteristics of the detection voltage will inevitably fluctuate unexpectedly. There was a problem in that it was essentially impossible to measure. Therefore, the present invention solves the various problems mentioned above, and its objectives are, firstly, to accurately measure the rate of voltage change of a detected voltage having any fluctuation characteristics; and secondly, to It is an object of the present invention to provide a digital voltage change rate measuring instrument capable of measuring the voltage change rate in real time without a blind period. [Means for Solving the Problems] In order to solve the above problems, the means taken by the present invention is an analog-to-digital conversion system that receives a detected voltage and sequentially outputs a measured value as a digital quantity corresponding to the detected voltage every predetermined time t. and a difference means for sequentially outputting the difference value between the previous measured value and the current measured value at predetermined time intervals t based on the sequentially outputted measured values;
Temporary storage means that stores the difference value for a unit time nt (where n is a positive integer) and then outputs it sequentially; and the output of this temporary storage means is used as a subtraction input, and the output of the difference means is received as an addition input. It consists of an addition/subtraction means that sequentially outputs the cumulative values of both, and sequentially changes the voltage change rate in a width of unit time nt, which is shifted by a predetermined time t while overlapping the previous voltage change rate by time (n-1)t. It's something you get. [Description of Embodiment] Next, an embodiment of the present invention will be described based on the drawings. <Configuration of Embodiment> FIG. 1 is a block diagram showing an embodiment of a digital voltage change rate measuring instrument according to the present invention. In the figure, 1 is an analog-to-digital converter that receives a detected voltage and outputs a measured value as a digital amount corresponding to the detected voltage.
The measured values are sequentially outputted to the difference circuit 3 at intervals of minute time t in synchronization with every clock pulse of pulse interval t generated. The differential circuit 3 is an analog-to-digital converter 1
The measured values sequentially outputted from the clock are temporarily stored for a time t, and based on this, the difference value between the previous measured value and the current measured value is sequentially output at every minute time t in synchronization with the clock pulse from the clock generation circuit 2. It is. This difference circuit 3 can be configured by, for example, a counter and a digital comparator or a register and a full adder. Reference numeral 4 denotes an n-stage shift register as a temporary storage means, which stores the difference values sequentially outputted from the difference circuit 3 for a predetermined time nt, and then outputs them in synchronization with a clock pulse. For example, when the shift register 4 has n stages, the difference value from the difference circuit 3 is sequentially shifted from the first stage in synchronization with the clock pulse from the clock generation circuit 2, and outputted from the last stage in a delayed manner. , the temporary storage time of the difference value is given by (number of stages n of shift register 4 x period t of clock pulse). This temporary storage time nt corresponds to a unit time of the voltage change rate, as described later. Reference numeral 5 denotes an adder/subtractor circuit, which has a subtraction input terminal 5a for receiving the output of the shift register 4 and an addition input terminal 5b for receiving the output of the difference circuit 3. It subtracts and accumulates values, adds and accumulates actual difference values, and sequentially outputs all accumulated values. This addition/subtraction circuit 5 can be configured by, for example, a register and a counter or a full adder and an ALU. <Operations and Effects of the Embodiment> Next, the operation of the above embodiment will be explained. now,
The number of stages of the shift register 4 is 3, and the elapsed time t ₀
Assume that the contents of the analog-to-digital converter 1, the difference circuit 3, the shift register 4, and the addition/subtraction circuit 5 are cleared, and then a detection voltage is applied to the analog-to-digital converter 1. Here, the analog-to-digital converter 1 detects elapsed times t ₁ , t ₂ , t ₃ , t ₄ , t ₅ , as shown in Table 1 below.
...t _i , t _i+1 , t _i+2 , t _i+3 , ... sequentially V ₁ , V ₂ , V ₃ ,
Digital measurement values of V ₄ , V ₅ , . . . V _i , V _i+1 , V _i+2 , V _i+3 , . . . are output.

[Table] The output of the differential circuit 3 at elapsed time t ₁ is V ₁ −0
(=V ₁ ), the contents of shift register 4 are as follows:
Since V ₁ is 0 in the second and third stages, the output of the addition/subtraction circuit 5 is 0+V ₁ -0=V ₁ . The output of the differential circuit 3 at elapsed time t ₂ is V ₂ −V ₁ ,
The contents of the shift register 4 are as follows: the first stage is V ₂ −V ₁ , 2
Since the first stage is _V1 and the third stage is 0, the output of the addition/subtraction circuit 5 is _V1 +( _V2 - _V1 )-(0)= _V2 . Further, the output of the differential circuit 3 at the elapsed time t ₃ is V ₃ −V ₂ , and the contents of the shift register 4 are V ₃ −V ₂ in the first stage, V ₂ −V ₁ in the second stage, 3 Since the stage is V ₁ and the overflow output of the shift register 4 is 0, the output of the addition/subtraction circuit 5 is V ₂
+( _V3 - _V2 )-0= _V3 . In other words, from the reset time _t0 to the time _t3 , the output of the adder/subtractor 5 is the same as the output of the analog-to-digital converter 1,
No digital voltage change rate is given during this initial time 3t. Next, the output of the differential circuit 3 at time t ₄ is
At V ₄ −V ₃ , the contents of shift register 4 are as follows:
V ₄ -V ₃ , the second stage is V ₃ -V ₂ , the third stage is V ₂ -V ₁ , and the overflow output is V ₁ , so
The output of the addition/subtraction circuit 5 is V ₃ + (V ₄ −V ₃ )−V ₁ =V ₄ −
It becomes V ₁ . Similarly, the output of the differential circuit 3 at elapsed time _t5 is _V5 - _V4 , the output of the shift register 4 is _V5 - _V4 for the first stage, _V4 - _V3 for the second stage,
Since its overflow output is V ₂ −V ₁ , the output of the adder/subtractor 5 is V ₄ −V ₁ +(V ₅ −V ₄ )−(V ₂ −
V ₁ )=V ₅ −V ₂ . In this way, the output of the adder/subtractor circuit 5 at time t _i is generally V _i −V _i-3 , which is the difference between the actual digital voltage value V _i at time t _i and the time t _i- 3 three clocks (3t) earlier. Digital voltage value V _i-2 at
It changes at the difference value. Here, the digital change rate is given by the ratio of the change value to the unit time, but in this example, the unit time is 3t, so the addition/subtraction circuit 5
sequentially outputs a digital rate of change with a unit time of 3t. Generally, when the number of stages of the shift register 4 is n and the clock pulse period is t, the unit time is nt, and the output of the addition/subtraction circuit gives a digital rate of change of (V _i -V _io /nt). Therefore, by changing the number of stages n of the shift register 4 and the clock pulse period t, it is possible to change the length of the unit time as appropriate. The digital rate of change obtained from the addition/subtraction circuit 5 gives the rate of change at the time of measurement. It is also interesting to note that there is a period in which the digital change rates at adjacent points of time overlap by (n-1)t. This overlap period eliminates the blind period and achieves almost real-time measurement. Furthermore, especially by making the measurement unit time relatively long, it is possible to accurately obtain the rate of voltage change at low speed or extremely low speed. Here, in order to better understand the operation of this embodiment, assume that the number of stages in the shift register 4 is 10, and time-series data in which the numerical value monotonically increases by 10 for each clock from T=0 to T=19. . The contents of the adder/subtractor 5 in this case are given as shown in Table 2, and this situation is shown in FIG. 3A. After T=11, the contents of the adder/subtractor 5 are in equilibrium and the rate of change during the unit time=10×clock period is 100. Also, suppose a data string in which a numerical value of ±5 is added alternately to a numerical value that monotonically increases by 10 for each clock. The contents of the adder/subtractor 5 in this case are given as shown in Table 3, and this situation is shown in FIG. 3B. In this case as well, the contents of the adder/subtractor 5 are balanced after T=11, and the value is 100. Furthermore, suppose a data string in which a numerical value of ±20 is added alternately to a numerical value that monotonically increases by 10 for each clock. The contents of the adder/subtractor 5 in this case are given as shown in Table 4, and this situation is shown in FIG. 3C. In this case as well, the contents of the adder/subtractor 5 are balanced after T=11, and the value is 100.

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〔Effect of the invention〕

As explained above, the digital voltage change rate measuring device according to the present invention is characterized in that the voltage change rate for a measurement unit time that is a positive multiple of the interval is obtained in a time series at a predetermined time interval. This produces the following effects. Since adjacent voltage change rates overlap by a predetermined period of time, the voltage change rate can be measured every clock time without waiting for the unit time to elapse. Small fluctuations within a unit time (the product of the number of stages of the shift register and the clock time) are ignored, only large fluctuations within a unit time are captured, and the rate of change of this large fluctuation can be detected. By digitally changing the length of the clock time and the number of stages of the shift register, it is easy to change the unit time, and therefore it is possible to obtain a rate of change in the detected voltage corresponding to various fluctuation characteristics. By determining the difference value of the digital quantity in advance by the difference means, and by having the temporary storage means and the addition/subtraction means handle only the difference value, regardless of the absolute value of the digital quantity corresponding to the detected voltage,
It becomes possible to allocate the bit lengths of the temporary storage means and the addition/subtraction means to only difference values, that is, digital quantities corresponding to the amount of voltage change every predetermined time t. Therefore, it is possible to provide a measuring device with a wide dynamic range that can sufficiently follow even steep voltage changes.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital voltage change rate measuring device according to the present invention. Second
The figure is a circuit diagram showing an example of a conventional digital voltage change rate measuring device. FIG. 3A is a graph diagram showing the input data and the contents of the adder/subtractor corresponding to Table 2;
FIG. 3B is a graph diagram showing the input data corresponding to Table 3 and the contents of the adder/subtractor, and FIG. 3C is a graph diagram showing the input data corresponding to Table 4 and the contents of the adder/subtractor. [Explanation of symbols], 1...Analog-digital converter, 2...Clock generation circuit, 3...Differential circuit, 4
...shift register, 5...addition/subtraction circuit, 5a...subtraction input terminal, 5b...addition input terminal, AM...operational amplifier, C...capacitor, R...resistance.

Claims (1)

[Scope of Claims] 1. Analog-to-digital conversion means that receives a detected voltage and sequentially outputs measured values as digital quantities corresponding to the detected voltage at predetermined time intervals t; A difference means for sequentially outputting the difference value at predetermined time intervals t; a temporary storage means for sequentially outputting the difference value after storing it for a unit time nt (where n is a positive integer); A digital voltage change rate measuring instrument, comprising: an addition/subtraction means which receives the output of the difference means as a subtraction input, receives the output of the difference means as an addition input, and sequentially outputs the cumulative value of both. 2. The digital voltage change rate measuring instrument according to claim 1, wherein the temporary storage means is an n-stage shift register that performs a shift operation every predetermined time t.