JP2553836B2 - Self-correcting semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In the self-correction memory, a plurality of surplus cells for defect relief selected by each word line, a surplus bit line for exchanging information with the surplus cell, and a defective column address are provided. Column decoder that can program the memory and a defect isolation circuit that disconnects the bit line corresponding to the defective column address from the means for performing parity check and inputs a "High" (or "Low") fixed level to the means for performing parity check. And surplus data connected in series to a plurality of 1-input parity circuits in which the 1-input parity circuits to which the surplus bit line information is input are cascaded only when the horizontal group or the vertical group to which the defective column address belongs is activated. By adding a connection circuit, error correction is performed even after the defect found by the test at the time of manufacturing is switched to the surplus bit line in correspondence with the bit line. Has a function,
A self-correcting semiconductor memory that can satisfy both the improvement in manufacturing yield and the reliability in use.

[Industrial applications]

The present invention relates to a semiconductor memory having a self-correction function for automatically correcting a bit error in the memory, and in particular, has a redundant structure capable of replacing a hard error at the time of manufacture with an extra line and correcting a bit error generated at the time of use. The present invention relates to a self-correcting semiconductor memory.

[Conventional technology]

As a semiconductor memory having a self-correction function for automatically correcting a bit error in the memory (referred to as a self-correction memory), a horizontal / vertical parity code is applied to a plurality of memory cells connected to one word line. A basic structure of a semiconductor memory device (Japanese Patent Application No. 56-37223 and Japanese Patent Application Laid-Open No. 57-152597) and an improved structure that reduces the size of an additional circuit for self-correction and enables high-speed error correction operation Wish sho 59-
No. 86930, Japanese Patent Laid-Open No. Sho-SHO is proposed. An example of this improved configuration is shown in FIG. 7, and the correction principle is shown in FIG. Here, 1 is a memory cell, 2 is a parity cell for storing inspection information of memory cell information, 3 is a word line, 4 is a bit line, 5 is a parity bit line for a parity cell, 6 is a cell array, and 7 is a row decoder including a word driver. , 8
Is a multiplexer, 9 and 10 are selection switches, 11 is a one-input parity circuit in which the paths for transmitting two reference voltages “H” and “L” are switched according to input information, and 12 is a horizontal group parity check circuit including the selection switch 9. A circuit, 13 is a vertical group parity check circuit element including the selection switch 10, 14-1 is an upper column decoder, 14-2 is a lower column decoder, 15-1 is an upper column address, 15-2 is a lower column address, 16
Is a corrected data output terminal, 17 is a horizontal group, 18 is a vertical group, INV1 is an inverter, AND1 is an AND gate, and EOR1 is an exclusive OR gate.

First, the correction principle will be described with reference to FIG. 9
7 parity cells 2 are prepared for each memory cell 1 ((2N + 1) parity cells for N ² memory cells), and parity cell information is set so that even parity is established in each horizontal group and each vertical group. Is stored in each parity cell. In this state, for example, 17 horizontal groups and 18 horizontal groups shown in FIG.
I examined the vertical group's parity and found that the parity result was "1",
That is, if a parity error occurs, this means an error in the memory cell information located at the intersection of the 17 horizontal groups and the 18 vertical groups. It is necessary to correct the bit error by inverting this information. You can These 16 cells in total are connected to one word line 3 shown on the right in FIG. 8, and one horizontal group and one vertical group to which the memory cell information to be corrected belongs are selected by using a column decode signal. By performing each parity check and correcting the memory cell information to be corrected using the result, a self-correction memory as shown in FIG. 7 can be realized.

In this improved configuration, a one-input parity circuit indicated by 11, that is, a circuit for exchanging the connection relationship between the nodes N1, N2 and the nodes N3, N4 with the input signal and its complementary signal using the transistors Q1, Q2, Q3, Q4. By connecting them in cascade and arranging these circuits on the bit lines, it is possible to integrate the selector for selecting one horizontal group and vertical group and the parity check circuit for performing the parity check of each group. It is possible to achieve miniaturization and high-speed circuit operation. Note that the column decoder is divided into two in this configuration because the selection of the horizontal group by the column decoder 14-1 to which the upper column address (2 bits) 15-1 is input is determined by the lower column address (2 bits). This is because the lower column decoder 14-2 to which 15-2 is input selects each vertical group.

[Problems to be solved by the invention]

In the case of introducing a redundant configuration with a redundant line for defect relief aiming at an improvement in manufacturing yield, which is often used in the past, to the self-correction memory of this kind described above, in the case of an extra word line, cells of the same word line are used. Since it is possible to introduce the error-correcting code to the information without any trouble, in the case of the extra bit line, the defect bit line and the extra bit line when selecting the horizontal group and the vertical group Since there is no existing replacement method and the error correction function cannot be realized, it is impossible to introduce a surplus bit line, and it is impossible to construct a self-correction memory including a surplus bit line for relieving defects during manufacturing. There were flaws.

[Means for solving problems]

In order to solve the conventional problems, the present invention provides a conventional semiconductor memory device having a self-correction function with a plurality of surplus cells for defect relief selected by each word line and a surplus cell for exchanging information with the surplus cells. The bit line, the surplus column decoder that can program the defective column address, and the bit line corresponding to the defective column address are separated from the means for performing parity check, and the "High" (or "Low") fixed level is performed for parity check. The defect isolation circuit input to the means and the 1-input parity circuit in which the surplus bit line information is input only when the horizontal group or the vertical group to which the defective column address belongs is activated are connected in a plurality of 1-input parity circuits. It is characterized by adding a surplus data connection circuit connected in series.

[Action]

The present invention introduces a conventional defect relief surplus bit line into a self-correction memory by realizing a configuration in which a horizontal group and a vertical group can be newly selected with all bit lines including a surplus bit line replaced with a defective bit line. Moreover, since it is possible to correct the bit error occurring in the memory even after the defect relief, just as before the defect relief, the manufacturing yield and the reliability can be improved at the same time, and the redundant configuration technique is essential. It can be applied to an ultra-large capacity semiconductor memory that must achieve a low soft error rate. The details will be described below with reference to the drawings.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and the numbers 1 to 16 and AND1 and EOR1 are the same as the constituent elements of FIG. 7 described above. Reference numeral 19 is a surplus cell, 20 is a surplus bit line for exchanging information with the surplus cell, 21 is a surplus cell array, and 22 is a defect isolation circuit to be described later, the input and output of which are isolated by fusing of fuses or the like, and "High" or " A circuit for supplying a "Low" fixed level, 23-1 is a surplus upper column decoder capable of programming the upper address of the defective column address, 23-2 is a surplus lower column decoder capable of programming the lower address of the defective column address, 30, 30 'surplus Only when the upper column decoder 23-1 or the surplus lower column decoder 23-2 is activated, the one-input parity circuit 11 to which the information of the surplus bit line indicated by 20 is input is connected to a plurality of one-stage connected main stages. The surplus data connection circuit connected in series to the input parity circuit is shown, INV2, INV3, INV4 are inverters, and AND2 is an OR gate.

Next, the operation of this embodiment will be described. First, when there is a defect in one or more cells or a bit line in a column address, 22 defect isolation circuits belonging to the column address are activated, that is, laser or electrical fuse is blown. By doing so, for example, a "High" fixed level is supplied to the output of the circuit. An example of the defect isolation circuit 22 is shown in FIG. Reference numeral 24 denotes a fuse element, which normally turns off the transistor Q5 by holding the node N20 at "Low" level,
By transmitting the input signal of IN1 as it is as the output signal of OUT1 and melting two fuses when activated
By supplying a fixed "High" level to OUT1 by disconnecting IN1 and OUT1 and turning on Q5. Here, Vcc and V′cc mean “High” level power supply and Vss means “Low” level power supply. Even when OUT1 is supplied with “Low” fixed level by Vss, complementary input of 1-input parity circuit The same can be done by simply exchanging connections.

FIG. 3 shows an example of a surplus upper (lower) column decoder for programming a defective column address in the surplus upper column decoder and the surplus lower column decoder 23-1 and 23-2 with activation of the defect isolation circuit 22. . By disconnecting one of the fuse elements 24, to which a complementary signal is input corresponding to each column address, according to the defective column address, the defective upper (lower) column address is surplus upper (lower) column decoder 23-1 (23-2). ) To register. As a result, the output terminal RDOUT pre-charged by the reference signal ▲ ▼ holds the "High" level only when the input upper (lower) column address and the defective upper (lower) column address match.

The memory operation and the correction operation after activation of the defect isolation circuit and registration of the defective address in the surplus upper (lower) column decoder as described above will be described below.

In the first case, a defective column address is input. In this case, the bit lines corresponding to the defective column address are connected to the horizontal and vertical group parity check circuits of 12,13 by the selection switches of 9,10. In the 1-input parity circuit shown by 11, two reference voltages are transmitted through and removed from the target of parity check. On the other hand, since the surplus upper column decoders 23-1, 23-1 and the surplus lower column decoders are both selected, the nodes N16, N17 are set to the "High" level, and as a result, the surplus data connection circuits of 30, 30 'are Upon activation, the surplus bit line information is taken into the horizontal group and the vertical group, and parity check is performed in each. Therefore, the correction signal for the excess bit line information is obtained at the node N10. On the other hand, the AND2 causes the node N18 to go to the "High" level, and the information on the surplus bit line 20 is transmitted to the node N19 instead of the defective bit line information obtained by the multiplexer 8.
Therefore, the information of the surplus cell connected to the surplus bit line replaced with the defective bit line including the defective cell is inspected, and if there is an error, it will be corrected and output from the data output terminal 16 via EOR1. .

In the second case, a column address in which only the column address matches the defective upper column address is input. In this case, since the bit line corresponding to the defective column address is not included in the vertical group selected by the selection switch 10 and the surplus lower column decoder 23-2 is not selected, the surplus data connection circuit 30 'is activated. Not
The same parity check as before is performed. On the other hand, the bit line corresponding to the defective column address is included in the horizontal group selected by the selection switch 9 and this bit line information is changed from the target of parity check by the activation of the defect isolation circuit 22. Be removed. On the other hand, since the 23-1 surplus upper column decoder is selected, the activation of the 30 surplus data connection circuits causes the parity check of the selected horizontal group including the surplus bit line information. Further, in this case, since the node N16 is at "Low" level, the node N18 is also at "Low" level, and as a result, the bit line information selected by the multiplexer 8 appears at the node N19. Therefore,
The bit line information of the input column address is inspected by replacing the surplus bit line information with the defective bit line information at the time of parity check of the horizontal group, and if there is an error, it will be corrected and output. .

In the third case, a column address in which only the lower column address matches the defective lower column address is input. In this case, contrary to the second case, the selected horizontal group does not include a defective bit line, and the parity check is performed in the same manner as in the conventional case because the surplus upper column decoder 23-1 is not selected. . On the other hand, although the selected vertical group includes a defective bit line, the bit line information is removed from the target of parity check by the activation of the defect isolation circuit 22. On the other hand, since 23-2 surplus lower column data is selected, the parity check of the vertical group selected by activation of the surplus data connection circuit 30 'is performed including the surplus bit line information. The rest is performed in the same manner as in the second case. In conclusion, the bit line information of the input column address is used by replacing the surplus bit line information with the defective bit line information at the time of parity check of the vertical group. It is inspected, and if there is an error, it is corrected and output.

In the fourth case, a column address that does not match the defective upper column address and the defective lower column address is input to both the column address and the lower column address. In this case, neither the selected horizontal group nor the vertical group includes a defective bit line, and both the surplus upper column decoder and the surplus lower column decoder are unselected, so that the surplus data connection circuits of 30, 30 'are activated. Therefore, the parity check and error correction similar to the conventional one are performed accordingly.

According to the description of the first to fourth cases described above,
It has been clarified that the self-correction memory including the excess bit line for defect relief shown in the embodiment has the same self-correction function as before even after the defect relief. It is also possible to prepare a plurality of surplus bit lines in exactly the same manner.The 22 defect isolation circuits provided in the surplus bit lines are turned off when a defect is found in the surplus bit line after programming. It is for separation and can be replaced with another surplus bit line.

FIG. 4 is an example to which the present invention is applied, in which one horizontal group unit including a defective bit line is replaced with an extra bit line. Reference numeral 25 is a circuit having a function opposite to that of the defect isolation circuit 22 as shown in FIG. 5, that is, OUT2 is normally supplied with a "High" level, and the two fuses are blown to disconnect the node N21. 22 'is a connection circuit for bringing IN2 and OUT2 into conduction, and 22' has a configuration in which 22 defect isolation circuits are paired. After programming, one output is at "High" level and the other output is at "High" level. A circuit for fixing to the "Low" level, 30 "is a surplus data connection circuit having a function equivalent to 30, 30 'in the embodiment of FIG. 1, and 26 is a multiplexer selected by the lower column address 15-2. This circuit operates only when the surplus upper column decoder 23-1 is selected.

This principle is shown in FIG. 6, in which 28 horizontal groups including defective cells shown by 27 are replaced with a redundant horizontal group shown by 29 formed by 19 extra cells in group units. In this application example, 22 defect isolation circuits and 22 'pair configuration defect isolation circuits are provided between the 9 and 10 selection switches and 11 1-input parity circuits, one for each horizontal group unit. Has been done. Further, only the surplus upper column decoder indicated by 23-1 is arranged, and there is no surplus lower column decoder. Therefore, the number of programmed portions is smaller than that of the embodiment, and the defect isolation circuits 22 and 22 'and the pair configuration defect isolation circuits can be easily arranged on the high density array. Since the circuit operation in this application example is included in the first to fourth cases described in the embodiment, it is omitted here. Further, it is obvious that, for this application example, a configuration in which one vertical group unit including a defective bit line is replaced with an extra bit line can be easily realized. Further, it is possible to realize a similar configuration by using a part of the horizontal group or the vertical group as a replacement unit.

〔The invention's effect〕

As described above, according to the present invention, the conventional surplus bit line for defect relief can be introduced into the self-correction memory, and after the defect relief, the bit error occurring in the memory can be corrected just as before the defect relief. Therefore, there is an advantage that the manufacturing yield can be improved and the reliability can be improved at the same time, and it can be applied to an ultra-large capacity semiconductor memory in which a redundant configuration technology is essential and a low soft error rate must be achieved.

[Brief description of drawings]

1 is an embodiment of the present invention, FIG. 2 is a defect isolation circuit which is an essential part of the present invention, FIG. 3 is a surplus upper (lower) column decoder, FIG. 4 is an application example of the present invention, and FIG. Is a connection circuit which is a main part of the application example, FIG. 6 is a replacement principle diagram of the application example, FIG. 7 is a configuration example of a conventional self-correction memory, and FIG. 8 is a principle diagram of self-correction by a horizontal and vertical parity system. is there. 1 ... Memory cell, 2 ... Parity cell, 3 ... Word line, 4 ... Bit line, 5 ... Parity bit line, 6 ... Cell array, 7 ... Row decoder including word driver, 8 ... Multiplexer, 9 , 10 …… Selection switch, 11 …… 1 input parity circuit, 12 …… Horizontal group parity check circuit, 13 …… Vertical group parity check circuit element, 14-1 …… Column decoder, 14-2 …… Lower column decoder, 15-1 ... above column address, 15-2 ... lower column address, 16 ... data output terminal, 17 ... horizontal group, 18 ... vertical group, 19 ... surplus cell, 20 ... Surplus bit line, 21 ... Surplus cell array, 22 ... Defect isolation circuit, 22 '... Paired defect isolation circuit, 23-1 ... Surplus upper column address, 23-2 ... Surplus lower column address, 24 ... Fuse element, 25 ... Connection circuit, 26 ... excessive cell multiplexer, 27 ... defective cell, 28 ... defect horizontal group, 29 ... extra horizontal groups 30, 30 ', 30 "... surplus data connection circuit.

Claims (1)

(57) [Claims] 1. A plurality of memory cells for storing information, a plurality of check cells for storing information for detecting a bit error occurring in a memory, and a word for simultaneously selecting the plurality of memory cells and the check cells. Line, a bit line for exchanging information with the memory cell, a check bit line for exchanging information with the check cell, and desired bit line information and check in the code group to which the memory cell to be checked belongs. A selection switch for selecting bit line information by a column decode signal and a means for switching a path for transmitting two reference voltages “H” and “L” are connected in multiple stages, and a plurality of signals from the selection switch are input. Means for performing a parity check, and an error correction circuit for automatically correcting a bit error using the output of the means for performing a parity check. In the conductor recording device, a surplus bit line provided separately from the check bit line, a plurality of surplus cells connected to the surplus bit line and selected by the word line, and a surplus column decoder capable of programming a defective column address, A defect isolation circuit for disconnecting the bit line corresponding to the defective column address from the parity check means, and inputting the reference voltage “H” (or “L”) fixed level to the parity check means; The surplus bit line information is input only when the selection switch associated with the defective column address is activated, and a switch means for switching a path for transmitting the two reference voltages performs a multi-stage parity check. A redundant data connection circuit connected in series to the means. Correction semiconductor memory.