JP2554633B2 - Digital data conversion method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to a digital data conversion method effective for demodulating a television signal by digital processing.

(Prior Art) In recent years, a technique for digitally processing a video signal inside a television receiver has been developed. The reason for this is that in the case of analog signal processing, the signal processing circuit can be integrated into a single-chip LSI (large-scale integrated circuit), but many peripheral parts of the LSI are required, adjustment points remain, etc. There is a limit to the reduction. In order to further improve the image quality, a memory for delaying the signal and various filter operations are necessary, but such processing is much more accurate and stable in digital processing than in analog processing.

Here, the signal processing unit where digitization is effective is a unit that separates and demodulates the composite color video signal into a luminance signal and a chromaticity signal. In Japan, the NTSC system is used for broadcasting, so this will be described below as an example.

FIG. 9 shows a system for demodulating an NTSC composite color video signal in which a chromaticity signal is multiplexed with a luminance signal. In the NTSC system, the chromaticity signal is quadrature-modulated with a color subcarrier of frequency fsc. The color subcarrier of fsc is 1 line (1 scan line)
There is a phase inversion relationship for each, and the modulation signal can be separated from the composite color video signal by taking the difference between the front and rear scanning lines, and the color signal is demodulated by synchronously detecting this with the color subcarrier of fsc. .

When a composite color video signal is supplied to the digital comb filter 11 shown in FIG. 9, a modulated color signal is obtained at its output. The comb filter 11 has one horizontal period (1H below)
It is composed of delay circuits 12 and 13 and an adder 14, and utilizes the fact that the frequency positions of the spectra of the luminance signal component and the chromaticity signal component shown in FIG. be able to. This modulated color signal is supplied to the bandpass filter 15 and extracted as a modulated color signal in a predetermined band. The bandpass filter 15 is composed of 1-clock delay circuits 16 and 17 and an adder 18, and removes the components in the low band taken out by the comb filter 11. As shown in FIG. 11, if the NTSC signal is sampled at a clock of 4 fsc and is sampled in phase with the I axis, the sampled data is I The axis component and the Q-axis component are alternately arranged. If this signal is supplied to the synchronous detector 19 and the I and Q components are alternately taken out, it means that the synchronous detection is performed and a color signal can be obtained.

Generally, to demodulate a quadrature-modulated signal, the carrier
The demodulation output can be obtained by multiplying the SIN component and the COS component, but if sampling is performed with a 4 fs clock by the digital method, the demodulation output can be obtained by simple filter processing. Therefore, in the above-mentioned system for obtaining the demodulated output of the I and Q axis components, the sampling process with the clock of 4 fsc is very important.

Furthermore, what is convenient when the color video signal is digitally processed is that scanning line interpolation processing can be performed. NTSC
The system employs a 2: 1 interlace system. Interlacing is for thinning out the scanning lines of one image and transmitting it, and is useful for compressing the transmission band, but on the other hand, it is a factor of image quality deterioration called interlace failure. Line flicker is a typical deterioration phenomenon. This is a phenomenon in which the image appears to shake up and down in the case of a still image, but this can be eliminated by performing scanning line interpolation. That is, rattling can be eliminated by interpolating the thinned scanning lines and reproducing and displaying. Two-dimensional or three-dimensional as means for scanning line interpolation
A dimensional filter is required, which is difficult with analog technology but relatively easy with digital implementation.

12 and 13 are diagrams shown for explaining the scanning line interpolation processing. First transmitted in interlaced format
The scanning lines of the field are shown by solid lines, and the scanning lines of the second field are shown by dotted lines. When the interpolation is performed, the scanning line I3 is formed between the scanning lines L1 and L2 before and after, and the number of scanning lines is doubled. The scanning line signal thus obtained can be improved in image quality by being screen-scanned and displayed at twice the normal frequency. A line memory is required to interpolate the scanning lines as described above, but the interpolation process can be relatively easily achieved by performing digital processing.

Now, let us consider the clock when scanning line interpolation is performed by digital processing. FIG. 14 shows the first scanning line L1 and the second scanning line L2. To perform interpolation using such scan lines, both scan lines L1, L2
It can be understood that it is better that the sampling points are at the same horizontal position when viewed in the vertical direction.

However, for example, a home video tape recorder (hereinafter VT
Looking at the signal reproduced from R), jitter often occurs in the horizontal sync. In other words, the synchronization signal in Fig. 14
As in HD, there may be a shift in the time axis direction.
This is because mechanical factors in the rotating system of the VTR, expansion and contraction of the tape itself, etc. cause fluctuations in the playback signal on the time axis. The reproduced image by such a signal looks normal in the conventional television receiver because the horizontal deflection circuit automatically performs horizontal scanning of the cathode ray tube in synchronization with the horizontal synchronizing signal. That is, horizontal deflection scanning is performed following the horizontal synchronization signal.

However, if the signal with time-axis fluctuation as shown in the example in Fig. 14 is sampled with a very stable signal such as an fsc clock made by a crystal oscillator, the sample position will shift from line to line and the vertical correlation I can't expect correct interpolation of. This phenomenon will be described with reference to FIG.

Now, let us say that the scanning line signal L11 in the figure is a signal without jitter, the scanning line signal L12 is a signal in which jitter has occurred, and the points marked with circles are sampling points using the 4fsc clock. When sampling with 4 fsc clock, in case of NTSC video signal, the number of clocks required to sample the signal in one horizontal period is 910.
It becomes an individual. However, the jittered scan line signal L12 (this example is shown as a signal with a shortened signal period) is sampled with a number less than 910, so the number of data of 910 or less And will be stored in memory. When scanning line interpolation is performed using the data sampled in this way and the data obtained by sampling a signal with no jitter such as the scanning line signal L11, interpolation as shown by the interpolating scanning line signal L13 is performed. It becomes data, and the signal waveform is not normal.

In order to eliminate the above-mentioned interpolation defects, 910 clocks must be present in one horizontal period. Therefore, it is necessary to improve the oscillation frequency of this circuit by using a clock generation circuit having a frequency of 910fh (fh is a horizontal frequency) so as to follow the horizontal synchronizing signal and change. FIG. 16 shows the sampling position and the interpolation scanning line signal L14 when the sampling clock frequencies of the scanning line signal L11 and the scanning line signal L12 change following the horizontal synchronizing signal.
Is shown.

(Problems to be Solved by the Invention) As described with reference to FIGS.
A clock with a frequency of 4 fsc is required, and Figs. 13 to 16
A clock having a frequency of 910fh is required for the scanning line interpolation processing described in the figure. Therefore, in order to create a system that performs both color demodulation and scanning line interpolation by digital processing, it is necessary to configure an independent digital processing unit according to the difference in clock frequency. For example, it is a system as shown in FIG. In FIG. 17, first, an NTSC composite color video signal is input to an analog / digital converter 22 via an input terminal 21 and converted into a digital signal. This digital video signal is input to the luminance / chromaticity demodulation circuit 23.
This luminance / chromaticity demodulation circuit 23, as described in FIG. 9,
The I-axis component and the Q-axis component are demodulated, and the luminance signal component Y
Demodulate. Next, the I-axis component, the Q-axis component, and the luminance signal component Y are supplied to the digital / analog converter 24. The digital / analog converter 24, the previous analog / digital converter 22, and the luminance / chromaticity demodulation circuit 23 are a clock system with a frequency of 4 fsc. Next, the demodulated signals are again input to the analog / digital converter 25 and converted into digital signals. Then, it is inputted to the scanning line interpolation circuit 26, and the scanning line interpolation circuit 26 interpolates it. Each signal interpolated by the scanning line is input to the digital / analog converter 27, converted into an analog signal, and supplied to the color picture tube side. The analog / digital converter 25, the scanning line interpolation circuit 26, and the analog / digital converter 27 are a clock system having a frequency of 910fh.

If a system that performs both color demodulation and scanning line interpolation by a series of processes is created in this way, a digital / analog converter 24 and an analog / digital converter 25 having different clock frequencies are required on the way, and the cost increases. Further, if digital / analog conversion or analog / digital conversion is continuously performed, the signal may be deteriorated. Further brightness, I
This requires a circuit of three systems for the axis and Q axis components, which causes a price increase.

Therefore, according to the present invention, when the processing circuits that require clocks of two different frequencies are combined in series as described above, they can be digitally combined without passing through the digital / analog and analog / digital conversion processing paths. An object of the present invention is to provide a digital data conversion method which can reduce the price and can reduce the factors of signal deterioration.

[Structure of the Invention] (Means for Solving Problems) In the present invention, in order to achieve the above object, the luminance
On the chromaticity demodulation side, data that is sampled using a clock with a frequency of 4 fsc, which is convenient for separation and demodulation, is interpolated by the interpolation filter unit and is equivalent to data that is sampled with a clock that is an integer multiple of that. On the other hand, on the other hand, on the interpolation side, the interpolation processing is performed using the clock of 910fh.When selecting the data to be used for interpolation from the data equivalent to that sampled with the clock of the integral multiple, The above object is achieved by selecting the data whose phase is closest to the 910fh clock for each sample.

(Operation) As described above, data loss is eliminated by preparing by data interpolation interpolation that is equivalent to sampling with a clock that is an integral multiple of the clock of 4fsc frequency. By selecting data close to the sampling position of the clock, even if the time axis on the input side fluctuates, when interpolating data between scanning lines, it is possible to prevent temporal displacement of the interpolated data. ing.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. An analog composite color video signal is supplied to an input section 31, and this signal is converted into a digital signal by an analog / digital converter 32.
This digital signal is input to the luminance / chromaticity demodulation circuit 33, and separated and demodulated into a luminance signal component Y1, an I-axis signal component I1, and a Q-axis signal component Q1. These signal components are supplied to the digital-to-digital conversion unit 34, which is a feature of the present invention.

The digital / digital conversion unit 34 is provided corresponding to the interpolation filters 41a, 41b, 41c for interpolating each digital signal and the interpolation filters 41a, 41b, 41c, and 910fh of the output of the interpolation filter. Selection circuits 42a, 42b, 42c that select the data closest to the sampling position of the clock of
2a, 42b, 42c corresponding to each selection circuit 42a, 42b, 42
It has memories 43a, 43b and 43c for storing the output of c at the clock of 910fh and reading it at the clock of 4fsc.

The digital signal output from the digital-to-digital conversion unit is input to the scanning line interpolation circuit 35, the scanning line is interpolated, and then input to the digital-analog converter 36.
The analog luminance signal, the I-axis signal component and the Q-axis signal component from the digital / analog converter 36 are supplied to the picture tube drive circuit in the next stage.

The present invention is characterized by the digital / digital conversion section 34, and the operation of this section will be described in principle below.

FIG. 2 shows one system of the digital-to-digital converter of FIG. 1 as a representative. The interpolation filter 41a includes
Sample data having a frequency of 41 fsc indicated by a circle in FIG. 3 is supplied. The interpolation filter 41a creates interpolation data indicated by triangle marks by using the sampling data before and after in the time direction. The amount of data obtained by this is equivalent to being sampled at twice the sampling frequency. Furthermore, this data is interpolated and interpolated to create data at the position indicated by x in the figure. The amount of data in this case is equivalent to that the signal is sampled equivalently at a sampling frequency of 4 times. To perform the interpolation as described above, for example, a delay circuit 50 as shown in FIG. 5, coefficient units 521 to 52n for multiplying each delay element 501 to 50n of the delay circuit 50 by a coefficient, and each coefficient unit 521 to 52n. And a synthesizing circuit 53 for synthesizing the outputs of the.

The data prepared as described above is supplied to the selection circuit 42a. In this selection circuit 42a, the horizontal frequency fh
The sample data closest to the sample position of the clock having the frequency of 910fh phase-locked with is selected, and the selected sample data is stored in the memory 43a at the next stage.
When selected in this way, the video signal VD
Even if 4 is subject to jitter, the number of samples of the video data for one horizontal period stored in the memory 43a will always be 910, and even if 910 is used in this way, samples of unnecessary parts are sampled. It contains no data. That is, the data distribution is obtained by sampling the data for one horizontal period of the video signal in which the jitter has occurred at equal intervals.

The video data stored as described above is read from the memory 43a with a clock having a frequency of 4fsc and supplied to the scanning line interpolation circuit 35. The signal processed by the present invention is
Since the digital-to-digital conversion unit 34 has been subjected to the jitter correction, when the data array in the vertical direction is viewed, the vertical correlation is kept good.

FIG. 6 shows one example of the selection circuit 42a more specifically, and FIG. 7 shows a time chart of the circuit of FIG.

In FIG. 6, DFF1 to DFF10 are D type flip-flop circuits (hereinafter referred to as "flip-flop circuits"), and the data input parts of the flip-flop circuits DFF1, DFF2, DFF3 respectively have the circled positions described above. data,
The data at the x mark position and the data at the triangle mark position are supplied in parallel. Here, the flip-flop circuit DFF1 is driven by the inverted clock of the clock of 4fsc frequency, the flip-flop circuit DFF2 is driven by the inverted clock of the clock of 8fsc frequency, and the flip-flop circuit DFF3 is driven by the clock of 4fsc frequency. In this case, the data of the circle mark position, the data of the x mark position, and the data of the triangle mark position are supplied while being shifted so that the switching portions of the data do not coincide with each other as shown in the time chart.

The output data of the flip-flop circuits DFF1, DFF2, DFF3 are supplied to the flip-flop circuits DFF4, DFF5, DFF6, respectively. This flip-flop circuit DFF4, DFF5, DFF6
Are driven by a clock of 910fh which is phase-synchronized with the horizontal synchronizing signal. And this flip-flop circuit DF
The output data of F4, DFF5, DFF6 are AND circuits 61, 6 respectively.
It is supplied to one of the input terminals of 2,63. This AND circuit
61, 62, 63 select any one of the data according to the control signal from the code converter 66 and supply it to the flip-flop DFF10 via the OR circuit 64. AND circuit 61,62,63
The selection in is to select the data closest to the sampling position of the clock of 910fh, and the selection control signal is generated as follows.

The flip-flop circuits DFF7, DFF8, DFF9 respectively
An inverted clock of the 4fsc clock, an inverted clock of the 8fsc clock, and a 4fsc clock are supplied as data inputs. And these flip-flop circuits DFF7, DFF8, DFF9
Are driven by a clock of 910fh which is phase-synchronized with the horizontal synchronizing signal. This means that the data closest to the sampling position of the clock with a frequency of 910fh is 4fsc, 8fs.
It is to detect using each clock of c and 4fsc. In other words, the flip-flop circuits DFF1, DFF2, DFF3 are also 4fsc, 8fsc, 4f
Since it is driven by the clock of sc, if this clock is sampled by the clock of 910fh, the data output can be obtained to the flip-flop circuit whose timing is matched. The output data of the flip-flop circuits DFF7, DFF8, DFF9 are supplied to the code converter 66. The code converter 66 includes an exclusive OR circuit 67 and AND circuits 68, 6
9. Negative input OR circuit 70. And AND circuit 68,
The output of 69 is supplied to the other input of the AND circuits 61 and 62, and the output of the negative input OR circuit 70 is supplied to the other input of the AND circuit 62.

The conversion table of the above code converter 66 is represented as shown in FIG. An example of data selection will be described with reference to FIGS. 6 and 7. At time t1, the output c of the flip-flop circuit DFF9 becomes "1", and the outputs a and b of the other flip-flop circuits DFF7 and DFF8 are "0". In this case, the output of the negative input OR circuit 70 becomes "1", and the data at the sample position indicated by x is selected. At time t2, the outputs a, b, c of the flip-flop circuits DFF7, DFF8, DFF9 become "0, 1, 1". In this case, the data at the sample position indicated by the triangle mark is selected. In this way, data in a stable state near the sampling position of the frequency of 910fh is selected and supplied to the scanning line interpolation circuit of the next stage.

[Effects of the Invention] As described above, according to the present invention, data processing circuits having different clock frequencies are smoothly integrated without passing a digital / analog converter or an analog / digital converter in the middle thereof. Therefore, it is possible to provide a digital data conversion method that is effective in reducing the circuit scale and preventing signal deterioration.

[Brief description of drawings]

FIG. 1 is a structural explanatory view showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a part of the circuit shown in FIG. 1, and FIG.
FIG. 4 is an explanatory diagram of interpolation processing according to the present invention, and FIG.
FIG. 6 is a diagram showing an example of the interpolating film shown in FIG. 2, and FIG.
FIG. 7 is a diagram showing an example of the selection circuit of FIG. 2, FIG. 7 is a time chart shown in the explanation of the operation of the circuit of FIG. 6, and FIG.
FIG. 9 is a diagram showing a conversion table of the code conversion circuit in FIG. 9, FIG. 9 is an explanatory diagram showing a configuration of a luminance / chromaticity demodulation circuit, FIG. 10 is a diagram showing a frequency spectrum of a television signal, and FIG. 11 is a diagram showing a chromaticity signal. FIG. 12 is a diagram showing demodulated output, FIG. 12 is a diagram for explaining scanning lines of a television signal, FIG. 13 is an explanatory diagram of scanning line interpolation processing, and FIG. 14 is an explanation for explaining jitter of a television signal. FIG. 15 is a diagram for explaining scanning line interpolation of a television signal in which jitter has occurred, and FIG. 16 is a diagram for explaining time axis correction when performing scanning line interpolation,
FIG. 17 is a configuration explanatory view showing a conventional digital television signal processing circuit. 32 …… Analog / digital converter, 33 …… Luminance / chromaticity demodulation circuit, 34 …… Digital / digital converter, 35 …… Investigation line interpolation circuit, 36 …… Digital / analog converter, 41a-4
1c ... Interpolation filter, 42a-42c ... Selection circuit, 43a-43c
……memory.

Claims (1)

(57) [Claims] 1. A sample data string having a sample frequency f1 (Hz) is converted into a sample data string having a sample frequency of n × f1 (Hz) (n is a natural number or rational number) using a linear interpolation filter, For each sample point of a sampling frequency f2 (Hz) different from × f1 (Hz), the sample point of the sample data string of n × f1 (Hz) that is temporally closest to this sample point is determined by the determining means, A digital data conversion method, characterized in that the data of the sample point judged by the judging means is selected from the sample data string of n × f1 (Hz) by the selecting means and the sample data string of the sampling frequency f2 (Hz) is output. .