JP2558932B2 - Compound semiconductor integrated circuit - Google Patents
Compound semiconductor integrated circuitInfo
- Publication number
- JP2558932B2 JP2558932B2 JP2196624A JP19662490A JP2558932B2 JP 2558932 B2 JP2558932 B2 JP 2558932B2 JP 2196624 A JP2196624 A JP 2196624A JP 19662490 A JP19662490 A JP 19662490A JP 2558932 B2 JP2558932 B2 JP 2558932B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor integrated
- compound semiconductor
- integrated circuit
- film
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は耐湿性を向上した化合物半導体集積回路に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor integrated circuit having improved moisture resistance.
従来の技術 従来の一般的な化合物半導体集積回路の製作方法を、
基板としてガリウム砒素を用い、主要素子として電界効
果トランジスタ（FET）を使用する場合を例にとり説明
する。第３図に示すように、例えば半絶縁性ガリウム砒
素基板51上に選択的にイオン注入法によってSiイオンを
加速エネルギー25KeV、ドーズ量7.0×1012(cm-2)で活性
層52を形成し、次に通常の方法にて例えばタングステン
シリコンナイトライド（WSiN）によりゲート電極53を形
成する。このゲート電極を利用し、自己整合的にSiイオ
ンを加速エネルギー50KeV、ドーズ量6.0×1012(cm-2)イ
オン注入してｎ′層54を形成し、次に基板上全面に例え
ば二酸化珪素膜を2000A堆積し、この膜厚を利用しゲー
ト電極から約1500A離れてSiイオンを加速エネルギー150
KeV、ドーズ量5.0×1013(cm-2)イオン注入してn+層55を
形成する。その後、二酸化珪素膜を除去してから通常の
方法にて820℃で15分アニールし、各イオン注入層を活
性化する。さらに通常の方法にて窒化珪素膜（SiN）を2
000A堆積した後、オーミック電極57を形成しFETを完成
する。次にSiN膜58を3000A堆積し、スルーホール59を形
成後、チタン（Ti）60、金（Au）61をそれぞれ500A、50
00A蒸着し、イオンミリング法にて所定のパターンの一
層配線及びパッド部を形成する。次に、SiN膜62を7000A
堆積し、スルーホール63を形成後、Ti64及びAu65をそれ
ぞれ500A,8000A蒸着し、イオンミリング法にて所定のパ
ターンの二層配線を形成する。更にパッシベーション膜
としてSiN膜66を10000A堆積し、パッド部を所定の寸法
に例えば反応性イオンエッチング法にて開口し、化合物
半導体集積回路を完成する。2. Description of the Related Art Conventional manufacturing methods for general compound semiconductor integrated circuits
An example will be described in which gallium arsenide is used as the substrate and a field effect transistor (FET) is used as the main element. As shown in FIG. 3, for example, an active layer 52 is formed on a semi-insulating gallium arsenide substrate 51 by selectively implanting Si ions with an acceleration energy of 25 KeV and a dose of 7.0 × 10 12 (cm −2 ). Then, the gate electrode 53 is formed by a usual method, for example, using tungsten silicon nitride (WSiN). Using this gate electrode, Si ions are ion-implanted in a self-aligned manner with an acceleration energy of 50 KeV and a dose of 6.0 × 10 12 (cm -2 ) to form an n'layer 54. Next, for example, silicon dioxide is formed on the entire surface of the substrate. A film of 2000 A is deposited, and using this film thickness, Si ions are accelerated about 150 A away from the gate electrode by an acceleration energy of 150.
An n + layer 55 is formed by ion implantation of KeV and a dose amount of 5.0 × 10 13 (cm −2 ). Then, after removing the silicon dioxide film, annealing is performed at 820 ° C. for 15 minutes by a usual method to activate each ion implantation layer. Further, a silicon nitride film (SiN) is formed by a conventional method.
After depositing 000 A, an ohmic electrode 57 is formed to complete the FET. Next, a SiN film 58 is deposited to 3000 A and a through hole 59 is formed, and then titanium (Ti) 60 and gold (Au) 61 are deposited to 500 A and 50, respectively.
00A is vapor-deposited, and a single-layer wiring and a pad portion having a predetermined pattern are formed by an ion milling method. Next, apply SiN film 62 to 7000A
After depositing and forming the through hole 63, Ti64 and Au65 are vapor-deposited at 500A and 8000A, respectively, and a two-layer wiring having a predetermined pattern is formed by an ion milling method. Further, a SiN film 66 as a passivation film is deposited at 10000 A, and a pad portion is opened to a predetermined size by, for example, a reactive ion etching method to complete a compound semiconductor integrated circuit.
発明が解決しようとする課題 上記従来法による化合物半導体集積回路においては、
パッド部のAuとSiN膜の密着性が必ずしも十分ではない
ため、水分がAuとSiN膜の界面を経由して侵入し、最終
的には回路内部まで浸透し、素子を破壊する。In the compound semiconductor integrated circuit according to the above conventional method,
Since the adhesion between the pad and Au and the SiN film is not always sufficient, moisture penetrates through the interface between the Au and SiN film and eventually penetrates into the circuit to destroy the device.
本発明の目的は配線／絶縁膜界面を介しての水分の回
路各素子への侵入を抑えた化合物半導体集積回路を提供
することにある。An object of the present invention is to provide a compound semiconductor integrated circuit in which moisture is prevented from entering the respective circuit elements through the wiring / insulating film interface.
課題を解決するための手段 本発明は上記課題を解決するため、本発明は、化合物
半導体集積回路において、パッド部と回路各素子とを結
ぶ配線が吸湿層と交差することを特徴とする。Means for Solving the Problems In order to solve the above problems, the present invention is characterized in that, in a compound semiconductor integrated circuit, a wiring connecting a pad portion and each circuit element intersects a hygroscopic layer.
作用 上記手段を採用したことにより、パッド部と回路各素
子とを結ぶ配線が吸湿層と交差するため、パッド部から
の水分の侵入をこの吸湿層で受け持たせることができ
る。また、パッド部の主たる金属であるAuとSiN膜間にS
iN膜と密着性の良い第２の金属層を有するため、パッド
部からの水分の侵入を抑えることができる。By adopting the above means, the wiring connecting the pad portion and each circuit element intersects with the moisture absorption layer, so that the moisture absorption layer can handle the intrusion of water from the pad portion. In addition, S between the Au and SiN films, which are the
Since the second metal layer having good adhesion to the iN film is provided, it is possible to prevent moisture from entering through the pad portion.
実施例 以下、本発明の実施例を図面に基づき説明する。Embodiment An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例による化合物半導体集積回
路を示す断面図である。ここでは化合物半導体としてガ
リウム砒素（GaAs）を用い、主要素子としてFETを使用
する場合を例にとり説明する。同図において、まず半絶
縁性GaAs基板１上の所定部位に例えばSiイオンを加速エ
ネルギー25KeV、ドーズ量7.0×1012(cm-2)で活性層２を
形成し、次にゲート金属として例えばWSiNをスパッタ法
にて2000A堆積した後、所定の長さに加工しゲート電極
３を形成する。このゲート電極を利用し、自己整合的に
前記活性層２よりやや深くSiイオンを加速エネルギー50
KeV、ドーズ量6.0×1012(cm-2)イオン注入してｎ′層４
を形成し、次に基板上全面に例えば二酸化珪素膜を2000
A堆積し、この膜厚を利用しゲート電極から約1500A離れ
てSiイオンを加速エネルギー150KeV、ドーズ量5.0×10
13(cm-2)イオン注入してn+層５を形成する。その後、二
酸化珪素膜を除去してから通常の方法にて820℃で15分
アニールし、各イオン注入層を活性化する。さらに通常
の方法にて窒化珪素膜（SiN）６を2000A堆積した後、オ
ーミック電極７を形成しFETを完成する。次にSiN膜８を
3000A堆積した後、吸湿層として例えばSiO2膜を1000A堆
積し、第１図９のように例えばウェットエッチング法に
よって幅50μｍ残して取り去り、吸湿性を持つSiO2層９
を形成する。更にスルーホール10を形成した後、Ti11、
Au12をそれぞれ500A、5000A蒸着し、イオンミリング法
にて所定のパターンの一層配線及びパッド部を形成す
る。次に、SiN膜13を7000A堆積し、スルーホール14を形
成後、Ti15及びAu16をそれぞれ500A,8000A蒸着し、イオ
ンミリング法にて所定のパターンの二層配線を形成す
る。更にパッシベーション膜としてSiN膜17を10000A堆
積し、パッド部を所定の寸法に例えば反応性イオンエッ
チング法にて開口し、化合物半導体集積回路を完成す
る。FIG. 1 is a sectional view showing a compound semiconductor integrated circuit according to an embodiment of the present invention. Here, the case where gallium arsenide (GaAs) is used as the compound semiconductor and the FET is used as the main element will be described as an example. In the figure, first, an active layer 2 is formed at a predetermined portion on the semi-insulating GaAs substrate 1 with, for example, Si ions at an acceleration energy of 25 KeV and a dose amount of 7.0 × 10 12 (cm −2 ), and then as a gate metal, for example, WSiN. Is deposited by a sputtering method to 2000 A and then processed into a predetermined length to form a gate electrode 3. Using this gate electrode, the Si ions are accelerated in a self-aligned manner and slightly deeper than the active layer 2 with an acceleration energy of 50.
KeV, Dose 6.0 × 10 12 (cm -2 ) Ion-implanted n'layer 4
Then, a silicon dioxide film, for example, is formed on the entire surface of the substrate.
A is deposited, and using this film thickness, about 1500 A away from the gate electrode, Si ions are accelerated energy 150 KeV, dose 5.0 × 10
13 (cm -2 ) ions are implanted to form the n + layer 5. Then, after removing the silicon dioxide film, annealing is performed at 820 ° C. for 15 minutes by a usual method to activate each ion implantation layer. Further, after depositing a silicon nitride film (SiN) 6 of 2000 A by a usual method, an ohmic electrode 7 is formed to complete the FET. Next, the SiN film 8
After 3000A deposited, as wicking layer such as SiO 2 film 1000A deposition, removal leaving width 50μm for example by wet etching as shown in Fig. 1 9, SiO 2 layer having a hygroscopic 9
To form. After forming the through hole 10, Ti11,
Au12 is vapor-deposited at 500 A and 5000 A, respectively, and a single layer wiring and a pad portion having a predetermined pattern are formed by an ion milling method. Next, after depositing the SiN film 13 at 7000A and forming the through hole 14, Ti15 and Au16 are vapor-deposited at 500A and 8000A, respectively, and a two-layer wiring having a predetermined pattern is formed by an ion milling method. Further, a 10000 A SiN film 17 is deposited as a passivation film, and the pad portion is opened to have a predetermined size by, for example, a reactive ion etching method to complete the compound semiconductor integrated circuit.
次に本発明の第２の実施例の化合物半導体集積回路を
第２図に示す。前記実施例に示した通りの方法にてFET
のオーミック電極までを形成した後（第２図１〜７）、
SiN膜を3000A堆積し、スルーホール20を形成する。次に
Ti21、Au22、Ti23の順にそれぞれ500A、5000A,250A蒸着
し、イオンミリング法にて所定のパターンの一層配線及
びパッド部を形成する。更にSiN膜13を7000A堆積し、ス
ルーホール14を形成後、Ti15、Au16、Ti24をそれぞれ25
0A,8000A、500A蒸着し、イオンミリング法にて所定のパ
ターンの二層配線を形成する。次にパッシベーション膜
としてSiN膜18を10000A堆積し、例えば反応性イオンエ
ッチング法にて第２図17のようにSiN膜とTi膜界面まで
開口し、更にSiN膜開口部より小さいレジストパターン
によりパッド部最上部のTi膜24を例えば反応性イオンエ
ッチング法により開口し、化合物半導体集積回路を完成
する。開口部においてTiを最上層に残さないのはTi表面
が酸化され易いためである。Next, FIG. 2 shows a compound semiconductor integrated circuit according to a second embodiment of the present invention. FET as described in the above embodiment
After forming up to the ohmic electrode of FIG.
A through hole 20 is formed by depositing a SiN film at 3000 A. next
Ti21, Au22, and Ti23 are vapor-deposited in the order of 500 A, 5000 A, and 250 A, respectively, and a single-layer wiring and a pad portion having a predetermined pattern are formed by an ion milling method. Further, after depositing 7,000 A of SiN film 13 and forming a through hole 14, Ti15, Au16, and Ti24 are each added to 25
0A, 8000A, and 500A are vapor-deposited, and a two-layer wiring having a predetermined pattern is formed by an ion milling method. Next, a SiN film 18 is deposited as a passivation film at 10000A, and is opened by the reactive ion etching method to the interface between the SiN film and the Ti film as shown in FIG. The top Ti film 24 is opened by, for example, the reactive ion etching method to complete the compound semiconductor integrated circuit. The reason why Ti is not left in the uppermost layer in the opening is that the Ti surface is easily oxidized.
発明の効果 以上のように、本発明によれば、パッド部と回路各素
子とを結ぶ配線が吸湿層と交差するため、パッド部から
侵入した水分をこの吸湿層で止めることができ、例えば
第４図（１）に示すように高信頼性の化合物半導体集積
回路を実現できる。As described above, according to the present invention, since the wiring connecting the pad portion and each circuit element intersects with the moisture absorption layer, moisture that has entered from the pad portion can be stopped by this moisture absorption layer. As shown in FIG. 4A, a highly reliable compound semiconductor integrated circuit can be realized.
また本発明によれば、パッド開口部はSiN膜と密着性
の良いTiと相接しているので、パッド部からの水分の侵
入を防ぐことができ、例えば第４図（２）に示すように
高信頼性の化合物半導体集積回路を実現できる。Further, according to the present invention, since the pad opening is in contact with Ti, which has good adhesion to the SiN film, it is possible to prevent water from entering through the pad, as shown in FIG. 4 (2), for example. Thus, a highly reliable compound semiconductor integrated circuit can be realized.
第１図は本発明の一実施例を説明する化合物半導体集積
回路の断面図、第２図は本発明の他の実施例を説明する
化合物半導体集積回路の断面図、第３図は従来の化合物
半導体集積回路の断面図、第４図は本発明によるFETと
従来法によるFETの耐湿性の差を比較した図である。 ９……SiO2膜（吸湿層）、16……Au、17.18……パッシ
ベーション膜、24……Ti膜。FIG. 1 is a sectional view of a compound semiconductor integrated circuit for explaining an embodiment of the present invention, FIG. 2 is a sectional view of a compound semiconductor integrated circuit for explaining another embodiment of the present invention, and FIG. 3 is a conventional compound. FIG. 4 is a cross-sectional view of a semiconductor integrated circuit, and FIG. 4 is a diagram comparing the difference in humidity resistance between the FET according to the present invention and the FET according to the conventional method. 9 …… SiO 2 film (moisture absorption layer), 16 …… Au, 17.18 …… passivation film, 24 …… Ti film.
Claims (1)
層と交差することを特徴とした化合物半導体集積回路。1. A compound semiconductor integrated circuit in which a wiring connecting between various circuit elements and pads intersects with a moisture absorption layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2196624A JP2558932B2 (en) | 1990-07-24 | 1990-07-24 | Compound semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2196624A JP2558932B2 (en) | 1990-07-24 | 1990-07-24 | Compound semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0482225A JPH0482225A (en) | 1992-03-16 |
| JP2558932B2 true JP2558932B2 (en) | 1996-11-27 |
Family
ID=16360858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2196624A Expired - Lifetime JP2558932B2 (en) | 1990-07-24 | 1990-07-24 | Compound semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2558932B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3954998B2 (en) * | 2003-08-11 | 2007-08-08 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
| JP6319028B2 (en) * | 2014-10-03 | 2018-05-09 | 三菱電機株式会社 | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3610709A1 (en) * | 1986-03-29 | 1987-10-08 | Philips Patentverwaltung | METHOD FOR PRODUCING SEMICONDUCTOR COMPONENTS |
-
1990
- 1990-07-24 JP JP2196624A patent/JP2558932B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0482225A (en) | 1992-03-16 |
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