JP2559929B2 - Programmable controller - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller provided with a coprocessor dedicated to instruction execution in addition to a main processor.

[0002]

2. Description of the Related Art Conventionally, for the purpose of improving the processing speed of a programmable controller, as shown in FIG. 6, a general-purpose main processor 11 conventionally used and an instruction execution-only coprocessor operating in parallel. It is proposed to provide 21. Coprocessor 21
In order to speed up the processing, a reduced instruction set processor (RISC processor) is used. In this case, the source code of the sequence program designed by the user or the like and stored in the source program memory 12 is stored in the object program memory 22 after being compiled and converted into a reduced instruction, and the basic instructions and the application instructions are stored in the object program. It is executed by the coprocessor 21 based on the object code made up of the reduction instruction stored in the memory 22. The source code is compiled by the main processor 11 using a compiler stored in the system memory 13. Further, the main processor 11 is not used for executing the instructions of the sequence program, but is used for controlling the peripheral devices and communication performed through the interface 14 in addition to compiling the source code. Communication between the main processor 11 and the coprocessor 21 is performed by the bus controller 15
Done through. Here, the data bus of the main processor 11 is 16 bits, and the data bus of the coprocessor 21 is 32 bits with the object program memory 22 and 16 bits with the data memory 23. The bus controller 15 includes a 16-bit data bus of the main processor 11 and a coprocessor 21.
It has a function of connecting with the 32-bit data bus of. Since the internal processing of the coprocessor 21 is performed in 32 bits, the instruction can be executed faster than the main processor 11 in combination with the RISC processor.

The relationship between the source code and the object code is as shown in FIG. For example, when the source code has three instructions and the number of words of each instruction is 2, 4, and 4, the number of words of the object code using the reduced instruction is, for example, 3 for each instruction of the source code. ,
7, 5 and so on. In the object code, one word corresponds to one instruction. In the above example, one instruction using two words in the source code is three instructions in the object code.

By the way, since the basic instruction in the source code is a bit processing instruction and the application instruction is another instruction, in the coprocessor 21, as shown in FIG.
A bit processing unit 31 that specially executes a bit processing instruction corresponding to a basic instruction, and a multi-bit processing unit 32 that specially executes an instruction corresponding to an application instruction are provided.
While executing instructions on the one hand, fetching on the other hand is performed to speed up execution by pipeline control. In order to perform such pipeline control, the bit accumulator bacc output from the bit processing unit 31 is set as the execution condition of the multi-bit processing unit 32.
Is at the H level (hereinafter, the H level is 1), and the internal error flag ierr sent by the occurrence of an error inside the multi-bit processing unit 32 is required to be 0. That is, the bit accumulator
bacc and internal error flag ierr are set to the NOT circuit NOT
Type ₁ and the AND circuit execution control unit 33 composed of the AND _1, is performed to control by the execution condition by inputting the output of the execution control unit 33 to the multi-bit processing unit 32. Bit accumulator
The bacc is set or reset by the execution result of the bit processing instruction in the bit processing unit 31, and is set (becomes 1) when the execution is transferred to the multi-bit processing unit 32. Here, the bit processing instruction processed by the bit processing unit 32 is not executed by the bit accumulator bacc because it is only executed.

[0005]

In the above-mentioned configuration, the number of steps may be very large when the application instructions of the source code are expanded into the object code. In such a case, it is possible to save the capacity of the object program memory 22 by converting a part of the object code into a subroutine.

If the subroutine contains a division instruction, an error will occur in the subroutine when the divisor is zero. By the way, it is usual that the subroutine is transferred by a call instruction in the main routine, and is returned to the main routine by a return instruction at the end of the subroutine.
However, if an error occurs in the subroutine, the subsequent processing is not performed and the return instruction cannot be executed, so that there is a problem in that the process cannot return to the main routine.

As a general processing for an error, it is considered that the execution is stopped when the error occurs, but as described above, the source code is expanded to obtain the object code. Therefore, if the execution is stopped at an arbitrary position in the object code, there is a problem that the meaning of the execution stop point cannot be understood. That is, while execution monitoring is performed in units of source code instructions, if execution is stopped irrespective of the unit of object code corresponding to one instruction in the source code, the next time execution is resumed, There is inconvenience because it does not correspond to the source code. In short, if an error occurs in the middle of a subroutine and it becomes impossible to return to the main routine, there arises a problem that the process of stopping the execution cannot be performed at the head of the block of the object code corresponding to the next instruction of the source code.

As another processing for the error, the value of the end position designation field in the instruction of the final position of the block of the object code corresponding to one instruction of the source code is provided in the instruction of the object code. Is different from the value of the end position designation field of the instruction at another position, so that the value of the end position designation field may be used to control the stop point of execution when an error occurs. By performing such processing, when an error occurs in the main routine, the subsequent instruction can be made non-execution (NOP), and the execution stop processing can be performed in correspondence with one instruction of the source code. Since the end position of the block does not exist in the subroutine, when an error occurs in the subroutine, the process is stopped when the position corresponding to the end position of the block is found in the area after the subroutine. That is, there is a problem that the execution is stopped at a time point corresponding to another instruction instead of the next instruction of the source code.

By the way, the error judgment processing is performed by the object code inside the multi-bit processing unit 32.
Error occurs in one instruction like division or BCD conversion
Error flag in the hardware if it can occur
There is a function to set. On the other hand, for example, if the address specified by index modification (accessing the memory with the value obtained by adding a predetermined addition value to the value in the index register as the address) is within the data area of the memory, the object code There is also a case in which it is desired to perform the determination process by combining the instructions of However, conventionally, there is no means for setting the determination result obtained by the object code program as an error flag, and such a determination result cannot be used for execution control of the multi-bit processing unit 32. .

The present invention is intended to solve the above problems, and by providing means for forcibly executing only a return instruction even if an error occurs in a subroutine of an object code, a main routine is provided. To enable execution control corresponding to the source code, and even when performing error judgment processing using object code, execution control of the multi-bit processing unit can be performed using the judgment result. It is intended to provide a programmable controller as described above.

[0011]

According to the present invention, in order to achieve the above object, a coprocessor dedicated to instruction execution for executing a sequence program is provided separately from the main processor, and the source code of the sequence program is compiled and obtained. In the programmable controller that executes the object code by the coprocessor, the coprocessor is a bit processing unit that executes the object code corresponding to the basic instruction of the source code, and a multi-bit that executes the object code corresponding to the application instruction of the source code. External by the processing unit, the forced execution flag register in which the forced execution flag set field in the instruction of the object code sets the forced execution flag, and the error flag set field in the instruction of the object code Error flag register in which the error flag is set, and an execution control unit for controlling the execution state of the multi-bit processing unit by the output. If an internal error flag is generated due to an internal error detection from or the external error flag is set in the error flag register, the execution of the multi-bit processing unit is stopped and the forced execution flag is set. When set in the forced execution flag register, the multi-bit processing unit is set to the execution state regardless of other conditions.

[0012]

According to the above configuration, the coprocessor is provided with a compulsory execution flag register in which the compulsory execution flag is set by the compulsory execution flag set field in the object code and an external error flag is set by the error flag set field in the object code. The error flag register and the execution control unit that can control the execution state of the multi-bit processing unit based on the output value are provided. When the internal error flag is generated by the processing unit due to an internal error detection or the external error flag is set in the error flag register, the execution of the multi-bit processing unit is stopped and forced execution is executed. Flag is a forced execution flag Since the multi-bit processing unit is set to the execution state regardless of other conditions when it is set in the register, for example, the contents of the forced execution flag set field of the return instruction of the subroutine of the object code are set in the forced execution flag register. By setting the content to set the forced execution flag, it is possible to return to the main routine by executing only the return instruction even if an error occurs in the subroutine, and as a result, an error occurs. Then, it becomes possible to stop the execution at the break point of the block of the object code corresponding to one instruction of the source code. Further, the source code instruction and the object code block can be associated with each other, which facilitates debugging and editing. Further, it becomes possible to forcibly execute a program other than the sequence instruction, which enhances the expandability.

On the other hand, by providing the error flag register for setting the external error flag, the external error flag is set in the error flag register based on the judgment result when the error judgment process based on the combination of the object codes is performed. Such processing becomes possible, and error processing becomes possible in addition to the internal error flag generated from the multi-bit processing unit.
As a result, a complicated error determination condition can be set by the program of the object code, and the expandability of error processing is increased.

[0014]

[Example] The basic configuration of the programmable controller is
Since the configuration is the same as the conventional configuration shown in FIG. 6, the internal configuration of the coprocessor 21 will be mainly described below.
The coprocessor 21 is different from the conventional configuration shown in FIG.
Forced execution flag register 34, error flag register 3
5 is added and the configuration of the execution control unit 33 is changed.

The forced execution flag register 34 and the error flag register 35 each have a 3-input AND circuit A.
ND ₂ and AND ₃ , and D flip-flops FF ₁ and FF ₂ whose outputs from the AND circuits AND ₂ and AND ₃ are input to the clock terminal CK. Each AND circuit A
ND ₂ and AND ₃ have a flag set signal obtained by decoding a flag set instruction described later in the object code.
sreq and the clock signal clk are input, the third input bit b ₃ of the flag set instruction is input to the remaining input terminals of the AND circuit AND ₂ , and the flag input is set to the remaining input terminals of the AND circuit AND _3. The first bit b ₁ of the instruction is input. The second bit b ₂ of the flag set instruction is input to the data terminal D of the D flip-flop FF ₁ , and the 0th bit b ₀ of the flag set instruction is input to the data terminal D of the D flip-flop FF _2. To be done. The flag set signal sreq becomes H level (hereinafter, H level is 1) when the flag set instruction is generated, and at the same time, the first bit b of the flag set instruction is generated.
_{When 1} is 1, the value of the 0th bit b ₀ of the flag set instruction is synchronized with the clock signal clk and the value of the D flip-flop F
It is set to F ₂ . If the third bit b ₃ of the flag set instruction is 1 when the flag set instruction is generated, the value of the second bit b ₂ of the flag set instruction is transferred to the D flip-flop FF ₁ in synchronization with the clock signal clk. It is set. In the flag set instruction, the 0th bit b ₀ is called an external error flag, the 1st bit b ₁ is called an external error flag update instruction, the 2nd bit b ₂ is called a forced execution flag, and the 3rd bit b ₃ is called a forced execution flag update instruction. The meaning is given as follows.

The execution control unit 33 takes the logical sum of the output of the error flag register 35 which is the output of the D flip-flop FF ₂ and the internal error flag ierr which is output when an error occurs inside the multi-bit processing unit 32. OR circuit OR _1, the NOT circuit NOT ₁ which outputs the NOT of the output of the OR circuit OR ₁ take, the bit processing units 31
AND circuit AN for outputting a logical product of a bit accumulator bacc output as an execution permission signal from the multi-bit processing unit 32 to the NOT circuit NOT _1.
It is constituted by an OR circuit OR ₂ which takes the logical sum of the output of the forced execution flag register 34, which is the output of D ₁ and the D flip-flop FF _{1, and} the output of the AND circuit AND ₁ . The output of this OR circuit OR ₂ is the multi-bit processing unit 3
2 is input to control execution.
Therefore, the external error flag due to the flag set instruction is not set in the error flag register 35, the content of the error flag register 35 is 0, and the internal error flag ierr from the multi-bit processing unit 32 is set.
Is not occurring and the bit accumulator
If bacc is 1, then multi-bit processing unit 32 is in the running state. Even if at least one of the above three assumptions is not satisfied, if the content of the forced execution flag register 34 is 1, the multi-bit processing unit 32 is in the execution state. In short, if the external error flag is set to the error flag register 35, the execution of the multi-bit processing unit 32 can be stopped, and if the forced execution flag is set to the forced execution flag register 34, another condition is satisfied. Regardless of this, the multi-bit processing unit 32 can be forcibly set to the execution state.

The instructions used by the coprocessor 21 have four types as shown in FIG. here,
src1, src2, and dst1 are fields for designating internal registers of the coprocessor 21. FIG. 4A shows an instruction of a type called M type corresponding to the instruction to move data between the object program memory 22 or the data memory 23 and the internal register. The upper 6 bits are the instruction code field (op-code), the next 3 bits are the source register specification field (src1) that specifies the move source, the next 3 bits are the destination register specification field (dst1) that specifies the move destination, The next 4 bits are a status tag field (St) that stores the status tag code indicating the correspondence between the source code and the object code, and the lower 16 bits are an offset field (offset) that stores the offset value of the memory address. . If the source or destination is an internal register, the designated internal register becomes the source or destination, and the source or destination is the object program memory 22 or the data memory 2.
If it is 3, the data stored in the designated internal register becomes the source or destination address.

FIG. 4B shows an instruction of a type called R type in which the result of logical operation or arithmetic operation between values stored in two internal registers is stored in another internal register. A source register specification field that specifies two internal registers that store 6 bits and two operands in the instruction code field (op-code) from the upper bit.
Three bits are used for each of (src1) and (src2), four bits are used for the status tag field (St), and three bits are used for the destination register designating field (dst1) that designates the internal register for storing the operation result. The remaining 13 low-order bits are empty fields used as a function field for the purpose of enhancing functionality.

FIG. 4C shows an instruction of a type called I type for storing the result of a logical operation or arithmetic operation between the value stored in the internal register and the set value in another internal register. Is. In this type of instruction, an immediate field is used instead of the offset field of the M type instruction.
The difference in format is that (immediate) is provided.
In this instruction, a logical operation or arithmetic operation is performed between the value stored in the source register designation field (src1) and the value set in the immediate value field (immediate). Therefore, except that one of the two values to be calculated is stored in the immediate field (immediate) in the setting,
The same processing as the R type instruction is performed.

FIG. 4 (d) jumps to the address set by the program counter or jumps to the address stored in one internal register according to the magnitude relation of the values stored in the two internal registers. It is an instruction in a format called J type. Formally, the destination register specification field of the M type instruction
Source register specification field (src2) instead of (dst1)
It is in the format with. That is, a source register designation field (src1) that designates two internal registers,
The value stored in (src2) is compared in magnitude to jump to the address specified by the program counter, or one of the source register specification fields (src1), (src2)
The value stored in is used as the jump destination address. Instructions of this type include non-operation instructions.

The status tag field (St) described above
Is 4 bits, and as shown in FIG. 5, a 3-bit code number field (code) for storing the number of words forming one unit of the source code, and an object code corresponding to each unit of the source code. 1-bit end position specification field that indicates the position of the last instruction code in the block
(end) and. When one unit of the source code is a plurality of words and the corresponding block of the object code is a plurality of words, the compiler uses the code number field (code) of the instruction code at the beginning of the block of the object code corresponding to one unit of the source code. Set the number of words per unit of source code in). For other instruction codes in the same block, the code number field (c
ode) to 0. Here, the code number field (cod
Since e) is 3 bits, the maximum number is 7. However, one unit of the source code may be 8 words or more. In this case, the number of words is set in the code number field (code) in order from the instruction code at the beginning of the block of the object code corresponding to one unit of source code, and the total number of words in the same block is It is sufficient that the number of words is 1 unit. For example, if one unit of the source code is 15 words, the code number field (cod
e) is 7, 7, in order from the instruction code at the beginning of the block.
It becomes 1.

On the other hand, the end position of the block corresponding to one unit of the source code is designated by the contents of the end position designation field (end). That is, when the end position designation field (end) is "0", it shows the instruction code in the middle of the block, and when it is "1", it shows the instruction code at the final position. The flag set instruction is a J type instruction among these four types of instructions, and as shown in FIG. 2, the source register designation fields (src1) and (src2) are unused and the lower 4 bits b _{0 to} b are set. _The meaning of ₃ is given as described above. That is, the 0th bit b ₀ and the 1st bit b ₁ are error flag set fields, and the 2nd bit b ₂ and the 3rd bit b ₃ are forced execution flag set fields. When the upper bits b ₁ and b ₃ of the set field are 1, the lower bits b ₀ and b ₂ are set in the error flag register 35 and the forced execution flag register 34, respectively. Further, not only the dedicated instruction set for the flag set but also the return instruction of the subroutine, etc. are similarly given meanings to the lower 4 bits b _{0 to} b ₃ . it can. In this case, it is necessary to configure the decoder so that the flag set signal sreq is generated even for the return instruction.

With the above configuration, for example, if a return instruction of a subroutine is forcibly executed by the multi-bit processing unit 32, a return instruction in which both bits of the forced execution flag set field are set to 1 is generated. It should be written in the object code program. In such a return instruction, a flag set instruction sreq is generated from the decoder as shown in FIG. 3A, and a forced execution flag set field of the instruction as shown in FIGS. 3B and 3C. Second
Since bit b ₂ and third bit b ₃ are 1,
A signal as shown in FIG. 3 (e) is input from the AND circuit AND ₂ to the clock terminal CK of the D flip-flop FF ₁ in synchronization with the clock signal clk as shown in (d), and the value of the second bit b ₂ is latched. Is done. This forces the multi-bit processing unit 32 into the running state,
The return instruction can be executed.

On the other hand, if the third bit b ₃ on the upper side of the forced execution flag set field is set to 1 and the second bit b ₂ on the lower side is set to 0, the forced execution flag is released. be able to. The same applies to the external error flag. If both the 0th bit b ₀ and the 1st bit b ₁ are set to 1, the external error flag is set,
When the first bit b _{1 is set} to 1 and the 0th bit b ₀ is set to 0, the external error flag is cleared.

[0025]

As described above, according to the present invention, the coprocessor is externally controlled by the compulsory execution flag register in which the compulsory execution flag is set by the compulsory execution flag set field in the object code and the error flag set field in the object code. Since the error flag register in which the error flag is set and the execution control unit that can control the execution state of the multi-bit processing unit based on the output value are provided, the execution permission signal is not sent from the bit processing unit. Execution of the multi-bit processing unit is stopped when either the internal error flag is generated by the internal error detection from the multi-bit processing unit or the external error flag is set in the error flag register. Then
Since the multi-bit processing unit is set to the execution state regardless of other conditions when the forced execution flag is set in the forced execution flag register, for example, the contents of the forced execution flag set field of the return instruction of the subroutine of the object code By setting the contents to set the forced execution flag in the forced execution flag register, it becomes possible to return to the main routine by executing only the return instruction even if an error occurs in the subroutine. As a result, when an error occurs, it is possible to perform the processing of stopping the execution at the break point of the block of the object code corresponding to one instruction of the source code. Further, the source code instruction and the object code block can be associated with each other, which facilitates debugging and editing. Furthermore, it becomes possible to forcibly execute programs other than sequence instructions, even if
For example, to a language other than sequence language (such as BASIC)
There is an advantage that the expandability increases , such as enabling support .

On the other hand, by providing the error flag register for setting the external error flag, the external error flag is set in the error flag register based on the judgment result when the error judgment processing based on the combination of the object codes is performed. Such processing becomes possible, and error processing becomes possible in addition to the internal error flag generated from the multi-bit processing unit.
As a result, it is possible to set a complicated error judgment condition by the program of the object code, and there is an advantage that the expandability of error processing is increased.

[Brief description of drawings]

FIG. 1 is a block diagram of an essential part showing an embodiment.

FIG. 2 is an explanatory diagram showing a format of a flag set instruction used in the embodiment.

FIG. 3 is an operation explanatory diagram of the embodiment.

FIG. 4 is an explanatory diagram showing a format of an instruction code used in the embodiment.

FIG. 5 is an explanatory diagram showing a configuration example of a status tag field in an instruction code used in the embodiment.

FIG. 6 is a block diagram of a programmable controller according to the present invention.

FIG. 7 is an explanatory diagram showing an example of a relationship between a source code and an object code in the programmable controller according to the present invention.

FIG. 8 is a principal block diagram showing a conventional example.

[Explanation of symbols]

 31-bit processing unit 32 Multi-bit processing unit 33 Execution control unit 34 Forced execution flag register 35 Error flag register

Claims (1)

(57) [Claims] 1. A programmable controller in which a coprocessor dedicated to executing instructions for executing a sequence program is provided separately from a main processor, and an object code obtained by compiling a source code of a sequence program is executed by the coprocessor. , By the bit processing unit that executes the object code corresponding to the basic instruction of the source code, the multi-bit processing unit that executes the object code corresponding to the application instruction of the source code, and the forced execution flag set field in the instruction of the object code Forced execution flag register in which forced execution flag is set, error flag register in which external error flag is set by error flag set field in object code instruction, and output An execution control unit for controlling the execution state of the multi-bit processing unit is provided, and the execution control unit does not output an execution permission signal from the bit processing unit or an internal error flag due to an internal error detection from the multi-bit processing unit. Occurs or the external error flag is set in the error flag register, the execution of the multi-bit processing unit is stopped, and the forced execution flag is set in the forced execution flag register. A programmable controller characterized by setting a multi-bit processing unit to an execution state regardless of other conditions.