JP2561479B2 - Semiconductor circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a semiconductor circuit for reducing the current consumption particularly in a circuit configuration for generating a precharge signal such as ROM, RAM or PLA (Programmable Logic Array). Regarding

(Prior Art) Conventionally, for example, a simple method for creating a precharge signal for charging a bit line in a ROM, a RAM, a PLA, or the like is used.
As shown in FIG. 3 by taking PLA as an example, the sources of P-channel transistors Q ₇ and Q ₈ of C-MOS transistors are connected to a high potential (for example, 5 V) power supply terminal V _D , and a gate is a low potential power supply terminal. With GND connected, bit line Y ₁ ,
A current is always supplied to the high potential power supply terminal V _D to Y ₂ .

(Problems to be solved by the invention) As described above, in the precharge signal for charging the bit line in the conventional ROM, RAM or PLA, the gates of the P-channel transistors Q ₇ and Q ₈ are connected to the low potential power supply terminal. ,
Because it is fixed, N-channel transistor Q ₉ of C-MOS transistor is turned on the signal of the word line X ₁ becomes a high level. Therefore, there is a problem that current continues to flow and unnecessary current is consumed.

It is an object of the present invention to provide a semiconductor circuit that reduces unnecessary current consumption in a circuit configuration that creates such a precharge signal.

(Means for Solving Problems) The present invention solves the above problems by, for example, a gate output in which all signals of a word line are gated by a NOR circuit and the output thereof and a high-potential power supply terminal output are introduced into a NAND circuit. Is applied to the gate of the precharge signal transistor and is fed back to the NOR circuit to which the input from the input selection circuit is applied.

That is, the drain is connected to one of the bit lines (D, E), the gate is connected to one of the word lines (A, B, C), and the source is connected to the ground potential (GND). a memory cell transistor (Q ₃ ~Q _8), a source connected to the high-potential power supply (V _D), bit lines (D, E)
Precharge transistors (Q ₁ , Q ₂ ) with drains connected to one end, output circuits (DOUT) connected to the other ends of bit lines (D, E), and decoder circuits (ADDEC) that output address signals And a NOR circuit (I, II, III) in which the output of the decoder circuit (ADDEC) is used as one input and the output is connected to the word lines (A, B, C) at one end. , B, C) and a signal consisting of the logical sum of the signals obtained from (B, C) are supplied to the gates of the precharge transistors (Q ₁ , Q ₂ ) and the other input of the NOR circuit (I, II, III). Solve it.

(Operation) It is possible to easily reduce the wasteful current flowing through each bit line in the circuit configuration that creates a precharge signal for ROM, RAM, PLA, etc.

(Examples) Hereinafter, the present invention will be described with reference to the drawings using examples.

FIG. 1 is a simplified configuration diagram of an embodiment in which the present invention is described by taking a PLA as an example, and FIG. 2 is an operation waveform diagram for explaining FIG.

In FIG. 1, ADDEC is an input selection circuit (decoder) composed of a decoder in ROM, RAM or PLA, D, E are bit lines, DOUT is an external output circuit for selecting a signal derived from the bit line, A, B and C are word lines, Q ₁ and Q ₂ are precharge transistors, and Q ₃
To Q ₆ are memory cells, I to IV are NOR circuits, V is NAN
D circuit, V _D is high potential power supply terminal, GND is low potential power supply terminal, IN
₁ to IN ₃ are input terminals, I is a connection line (node) that connects the output of the NOR circuit IV and the input of the NAND circuit V, and J is NAND.
It is a feedback signal path for returning the output of the circuit V to the gates of the precharging transistors Q ₁ and Q ₂ and the inputs of the NOR circuits I to III.

In such a configuration, first, the signal selected by the input selection circuit ADDEC is applied to the input terminals IN ₁ to IN ₃ .

Initially, when high level signals (waveforms, a to c in FIG. 2) are applied to all the input terminals IN ₁ to IN ₃ , the word lines A to C are all at a low level (low). Similarly, the connection line (node) I becomes high level (d, e, f) and the low level (same as j) is derived to the feedback signal path J (same as i), and the bit lines D and E are charged. (The same, g, h).

Next, assuming that only the input terminal IN ₁ goes low, only the word line A goes high and the node I goes low.

Therefore, a high level is derived in the feedback signal path J,
The charging of the bit lines D and E is interrupted. However, immediately after that, the signal from the feedback signal path J is transmitted to the NOR circuits I to I.
When applied to II, a low level appears on word lines A to C. As a result, as in the case described above, the feedback signal path J becomes low level, and the charging of the bit lines D and E is restarted, but the driving currents (k, l) of the precharging transistors Q ₁ and Q ₂ are low. Therefore, before the bit lines D and E are charged up, the charge is interrupted by the level change of the feedback signal path J. This makes the bit line
The signal derived from D and E and output from the external output circuit DOUT does not change due to this feedback signal. However, the current consumed in the precharging transistors Q ₁ and Q ₂ is reduced.

That is, as described above, in the conventional configuration, the current always flows in the bit line in which the memory cell is in the ON state.
The current flowing through Q ₁ and Q ₂ decreases.

Although the present invention has been described above with reference to the embodiment using the PLA, it goes without saying that this can be applied to the configuration including the ROM, the RAM and the like.

(Effects of the Invention) As is apparent from the above description, the present invention provides ROM, RAM, and PLA.
In a circuit that creates a precharge signal such as
This is a semiconductor circuit that can reduce wasteful current consumption, and has an excellent effect.

[Brief description of drawings]

FIG. 1 is a simplified circuit diagram illustrating a programmable logic array (PLA) as an example for explaining an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation, and FIG. 2 is a simplified circuit diagram of the PLA of FIG. ADDEC …… input selection circuit (decoder), DOUT …… external output circuit, Y ₁ , Y ₂ …… bit line, IN ₁ , IN ₂ , IN ₃ …… input terminal, I, II, III, IV …… NOR Circuit, A, B, C ... Word line (node), D, E ... Bit line, V ... NAND circuit, I ... NOR circuit, J ... (NAND circuit output appears)
Negative feedback signal path, Q ₁ , Q ₂ ...... Precharge transistors, Q ₃ to Q ₆ ...... Memory cells.

Claims (1)

(57) [Claims] 1. A plurality of bit lines, a plurality of word lines, a drain is connected to any one of the plurality of bit lines, a gate is connected to any one of the plurality of word lines, and a source is connected to a ground potential. A connected memory cell transistor, a precharge transistor whose source is connected to a high-potential power supply, and a drain connected to one end of the bit line; an output circuit connected to the other end of the bit line; A decoder circuit that outputs a signal, and an output of the decoder circuit is input to one input end, the output end is provided with a NOR circuit connected to one end of the word line, the signal obtained from the plurality of word lines A signal consisting of a logical sum is supplied to the gate of the precharge transistor and to the other input terminal of the NOR circuit. A semiconductor circuit characterized by being provided.