JPS6028077B2 - amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit constituted by an insulated gate field effect transistor (mainly a MOS field effect transistor (referred to as MOST)), and particularly relates to a circuit that amplifies minute difference signals and generates a binary output. It is related to the circuit obtained.

It should be noted that although the following explanation will be made using an N-channel MOST, it is essentially the same for a P-channel MOST or other insulated gate field effect transistors.

Dynamic memory using MOST is required to be faster, and MOS memory circuit input signals other than clock signals are required to have a TTL level (0.4 to 2.4V), which is smaller than the MOS level (12V). Therefore, it is necessary to convert it to MOS level.

On the other hand, as memory capacity increases, one-transistor memory cells with the smallest memory cell area are used, but when a one-transistor memory cell is read, the binary signal stored in that cell is read out. , that is, "1",
“0” information causes only a small potential change of about 0.1 to 0.5 V on the desitt line, and therefore an amplifier circuit is required to amplify this minute signal. Conventionally, such a minute signal was amplified. The circuit shown in FIG. 1 is used as the circuit.

Stand... Amplifying circuit 1 is a switching transistor Q
, and 03 and load transistors Q2 and Q. Flip-flop outputs 2 and 3 are connected to digit lines 4 and 4' of the memory circuit, respectively, and their load capacitances are made equal. When cell 5, one of the memory cells connected to digit line 4, is read out, digit line 4'
The memory cell 5' connected to the
'' is generated on the digit line 4'. Conversely, when the cell 5' connected to the digit line 4' is read out, the reference voltage generating circuit 6 is applied to the digit line 4.
A reference potential is generated by. FIG. 2 shows the waveforms of both digit lines 4, 4'.

The operation of the circuit shown in FIG. 1 will be described below using the waveforms shown in the same figure.

Digit lines 4 and 4' are both at equal levels before time t, and the transistors are precharged by clock 03 and Q6, respectively. The transistor Q7, to which the clock 03 is applied to its gate, is used to improve the efficiency of bringing the digit lines 4 and 4' to the same level; It is not necessary if the check signal 03 is high enough. After the precharge is completed and the clock signal 3 becomes low level, the address signal selects, for example, the address line 7 and becomes high level, and the information in the memory cell 5 is read out. When the address line 7 becomes high level, charge is exchanged between the digit line 4 and the memory cell 5, and a change in potential appears on the digit line 4 in accordance with the information "1" or "0" of the cell. On the other hand, digit line 4
' is the cell information "1" and "0" by the reference voltage generation circuit 6'.
As a result, a potential difference of about 0.1 V is generated between the digit lines 4 and 4' before time t2. At time t2, the clock signal ?, is set to a high level, and the amplifier circuit 1 is connected to the transistor When activated by Q8, the charge on digit lines 4, 4' is discharged through transistors Q, Q3, respectively, but between digit lines 4, 4',
Since there is a slight potential difference as described above, there is a difference in the on-resistance of the transistors Q, , Q. Now, if digit line 4 is higher, the resistance of transistor Q3 is smaller, and therefore the potential of digit line 4' becomes lower level more quickly. As a result, the on-resistance of the transistor Q becomes larger and larger, further delaying the fall of the potential of the digit line 4, and amplifying the potential difference between the digit lines. As a result, a large potential difference occurs between the output nodes 2 and 3 of the flip-flop at different times. Therefore, is the clock signal at a time ratio of 3? 2 is set to a high level, and the digit line 4, which has once become low, is set to a high level again by the load transistor Q2, and the digit line 4' can be kept at a low level. By the way, what is the clock number? Although the two signals have been explained separately, it is also possible to operate with the same signal. In the amplifier circuit shown in FIG. 1, a DC current always flows through the transistor Q2 or Q4 while the clock ◇2 is at a high level.

Therefore, providing such an amplifier circuit for each digit line consumes a large amount of power. Furthermore, the transistor Q,,
It is also necessary to take a large ratio between the size of the transistor Q and the size of the transistors Q and Q4. These are major drawbacks of this amplifier circuit.
In addition, in this circuit example, it is also possible to make the common source connection point of transistors Q and Q common to multiple amplifier circuits, and to use only one transistor Q for activating the amplifier circuits for multiple amplifier circuits. It is. An object of the present invention is to provide an amplifier circuit with low power consumption.

Another object of the invention is to provide an amplifier circuit that performs dynamic operation.

Still another object of the present invention is to provide an amplifier circuit suitable for amplifying minute difference signals.

Another object of the present invention is to provide an amplifier circuit suitable as a sense amplifier for a memory circuit whose memory element is a one-transistor memory cell.

An amplifier circuit according to the invention includes first and second nodes, means for precharging said first and second nodes, and said first and second nodes.
a first load circuit controlled by the potential of the node;
a first series circuit of field effect transistors, a second load circuit controlled by the potential of the second node, a second series circuit of second field effect transistors, and a gate of the first transistor. means for connecting the gate of the second transistor to an intermediate connection point of the second series circuit;
means for connecting to an intermediate connection point of a series circuit; first and second muscle points; means for precharging the first and second nodes; and the first node and the first series circuit. a third field effect transistor connected to the intermediate connection point of the second series circuit and controlled by the potential of the intermediate connection point of the second series circuit; and between the second node and the intermediate connection point of the second series circuit. and a fourth field effect transistor connected to the first series circuit and controlled by the potential of the intermediate connection point of the first series circuit, and the first and second series circuits are operated as a flip-flop circuit. It is characterized in that one of the second nodes is caused to discharge.

More preferably, this amplifier circuit is used as a sense amplifier of a memory circuit that uses a one-transistor memory cell as a memory element.

According to the present invention, since there is no direct current path in the amplifier circuit, there is no power consumption and dynamic operation is possible.
It becomes possible to use a radioless circuit, and therefore the area occupied on the integrated circuit of the MOST constituting the circuit can be reduced.

Hereinafter, the present invention will be described in detail using examples in order to better understand the present invention. The above-mentioned insulated gate field effect transistor used in the present invention has a source, a drain, and a control, ie, gate, electrode. Even if it is used as a source electrode, it is equivalent and does not limit the present invention in any way.

FIG. 3 shows a reference example of the present invention, and parts equivalent to those in FIG. 1 are given the same reference numerals. 1 output 2 of the flip-flop constituted by transistors Q, -Q4 is input to the gate of switching transistor Q3. The drain of transistor Q9 is connected to the power source Voo through load transistors Q and o.
and to the gate 9 of transistor Q. In addition to the flip-flop, the outputs 3 are switching transistors Q, . becomes the gate input. transistor Q,
．． The drain of is connected to the power supply V through the load transistor Q,2.
oo and the gate 8 of transistor Q2.
connected to. A precharge clock signal of 3 is applied to the gates of the load transistors Q, o, Q, and 2. Also, transistors Q9, Q, . Is the source connected in common and the clock signal to the gate? 4 is applied to the transistor Q, which is grounded through the transistor Q3. The load transistors Q2 and Q4 of the flip-flop are transistors Q, 4, Q, and 5 to which a clock signal ◇2 is applied to their gates, respectively.
Power supply V via.

. It is connected to the. And the gate of transistor Q,4
Putot strap capacitors C and C2 are connected between the gate of transistor Q5 and node 8, and between the gate of transistor Q5 and node 9, respectively. The circuit operation shown in FIG.
This will be explained using the operation waveforms shown in the figure.

Before time 3, digit lines 4 and 4', nodes 8 and 9, and nodes 2 and 3 are precharged to predetermined potentials by clock signal ◇3.

As mentioned above, the transistor Q7 is used to more accurately equalize the precharge levels of nodes 2 and 3. If the parasitic capacitances of digit lines 4 and 4' can be made equal and the levels of nodes 2 and 3 can be made equal, then Not necessary. After the precharge clock signal ◇3 becomes low level, when a signal is applied to the timer address line, the digit line 4
, 4', cell signals are read out.

Time clock signal? , to a high level, and amplifier circuit 1
' is activated, digit lines 4, 4' are activated by time et al.
That is, the potential difference between nodes 2 and 3 is amplified. This is similar to the circuit example shown in FIG. To make the following explanation easier to understand, it is assumed that digit line 4 has a higher potential than 4'. By setting the clock signal ◇4 to a high level at a certain time, the precharged electric charges at the streak points 8 and 9 can be discharged, but since the digit line 4' is at a low level, the transistors Q, . is in the off state, and the charge at node 8 is not discharged and remains at a high level. On the other hand, digit line 2
Since is at a high level, the transistor Q9 is in an ON state, and the charge at node 9 is discharged and becomes a low level. As a result, transistor Q2 is in an ON state because its gate electrode 8 is at a low level, while transistor Q4 is in an oR state because its electrode 9 is at a low level. Clock at time t4? 2 is set to a high level, digit line 4 is charged through transistors Q2, Q, and 4, while digit line 4' is not charged because transistor Q is off, and is brought to ground potential by transistors Q3 and Q8. By controlling the gates of the transistors Q2 and Q that charge the digit lines 4 and 4' using the digit lines 4 and 4' in this manner, it is possible to eliminate the current flowing through the amplifier circuit 1'. Here, the capacity C. , C2 exist for the purpose of raising the nodes 8 and 9 to a higher potential than the precharged potential by capacitive coupling, reducing the ON resistance of transistors Q2 and Q4, increasing the charging speed, and obtaining a higher charging potential. It is not essential for operation. Also, as in the conventional example, the common source connection point of the transistors Q, , Q may be shared by a plurality of amplifier circuits. FIG. 5 shows an embodiment of the present invention, and the difference between this embodiment and the example of FIG. 3 is that transistors Q, . , Q9 are connected to the outputs 2 and 3 of the flip-flop, respectively, so that the transistors Q and 3 and the clock signal ◇4 in FIG. 3 are unnecessary.

The operation of the circuit shown in FIG. 5 will be explained below using the waveforms shown in FIG.

Digit line 4, 4 by clocking 3 before time
', nodes 2 and 3 and nodes 8 and 9 are precharged to the same position, respectively, and time t is equal to digit line 4,
4' is similar to the circuit example shown in FIG. 3.

For the sake of simplicity, it is assumed that the digit line 4 is at a high potential.

Clock signal at time t? , becomes high level and this amplifier circuit is activated. As shown in the circuit example in Figure 3,
Although the potential of the digit lines 4 and 4' decreases, the potential difference between the two is greatly amplified. Here, when the potential difference between both nodes 2 and 3 exceeds the threshold voltage VTH of MOST, transistors Q, . Or one of Q becomes ON state. That is, transistors Q, . Since the gate fin electrode 3 is lower than the source electrode 2, the transistor Q9 remains in the OFF state. On the other hand, the transistor Q9 has a potential difference between the gate electrode 2 and the source electrode 3 exceeding VTH, and becomes the ON state. As a result, the charge at the gate electrode node 9 of the transistor Q is discharged through the transistor Q, and the transistor Q is turned off.

On the other hand, transistors Q, . Since is in o state, node 8
The charges in the transistor Q2 are not discharged, and the transistor Q2 is in the ON state. When clock signal 2 is set to high level at time, transistors Q and 4 are turned on, and transistors Q and 4 are turned on.
Node 2 is charged through Q4 and Q2, but node 3 is not charged and remains at a low level because transistor Q4 is turned on, so there is no DC current path. FIG. 7 is a circuit diagram showing another embodiment of the present invention, in which parts equivalent to those in FIG. 5 are designated by the same reference numerals.

Among the transistors constituting the flip-flop, the sources of the load transistors Q2 and Q3 are both applied with a flip-flop activation clock signal, and the sources of the switching transistors Q, Q are both grounded. .

The signals on input lines (digit lines) 4 and 4' are input to the gates of transistors Q, 6, Q, and 7, respectively, and the drain outputs of transistors Q, s, Q, and 7 are connected to outputs 3 and 2 of the flip-flop, respectively. ing. Also Q, 6,
Q. 7 sources are both grounded. The input lines 4, 4' are further grounded via transistors Q, 8, Q, 9,
The gates of 8, Q, and 9 have flip-flop outputs 3,
2 are input respectively. The circuit operation in Figure 7 is shown in Figure 8.
This will be explained using the waveforms shown in the figure.

By time t, nodes 8 and 9 are fully charged to the same potential by clock signal J3.

Since the clock signal core is at a low level and nodes 8 and 9 are precharged and at a high level, transistor Q2
, Q4 are in the ON state and nodes 2, 3 are at the same low level as the clock signal G,. If at least one of the inputs 4 and 4' is a signal with a potential exceeding the VTH of the MOST, when the clock signal ◇ changes to a high level from time to time, the nodes 2 and 3 tend to go to a high level. However, input 4,4
If there is a slight potential difference between ′, transistors Q, 6, Q,
Since there is a difference in the ON resistance of node 8, there is a difference in the speed at which nodes 2 and 3 reach the high level.

If input 4 is at a higher level than input 4', node 2 will be higher than node 3, and transistor Q3 will turn O earlier.
It becomes N state. For this reason, the potential difference between nodes 2 and 3 increases further, and when the difference exceeds VTH at a certain time, transistor Q is turned on and the charge at node 9 begins to be discharged. On the other hand, transistors Q, . A is in an off state because the source potential is higher than the gate potential, and as a result, a difference occurs in the ON resistance of transistors Q2 and Q, and node 2 becomes a higher level, but node 9 is discharged and transistor Q is turned off. state and clock signal? , no current flows from contact 3 to contact 3. Therefore, the flip-flop outputs 2 and 3 output a signal obtained by amplifying the slight 4-level difference between the inputs 4 and 4'. Here, as mentioned above, when both inputs 4 and 4' are at a high level, that is, at a level higher than the VTH of MOST, and for example, when the input 4 side is high, the output 2 of the flip-flop has a high level.
A low level is generated at the output 3, but if a level higher than V, H of MOST is still applied to the input 4', the transistors Q and 7 remain in the ON state, and therefore the charge at the node 2 becomes Since the light will be emitted through the transistor Q, 7, the transistor Q, 9 with a high level applied to its gate forces the input 4' to fall to a low level.
This is for cutting off the above-mentioned discharge path.

Therefore, in a circuit system in which inputs 4 and 4' are both at a low level thereafter, transistors Q, 8, Q, and 9 are unnecessary, and even if input 4' is at a level lower than VTH in the above example, Similarly, transistors Q, 8, Q, and 9 become unnecessary.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a sense amplifier section in a conventional memory circuit, FIG. 2 is an operating waveform diagram of the circuit in FIG. 1, FIG. 3 is a circuit diagram showing a reference example of the present invention, and FIG. FIGS. 5 and 7 are circuit diagrams showing embodiments of the present invention, and FIGS. 6 and 8 are operation waveform diagrams of the circuits shown in FIGS. 5 and 7, respectively. In the figure, Q,,Q3,Q9 and Q, . are switching transistors, Q2, Q, Q,. and Q, 2 are load transistors, 2, 3 are flip-flop outputs, 4, 4'
indicate the digit lines, respectively. Tsutomu' figure, figure 2 leopard figure 4 figure h rudder ship figure younger brother 6 figure younger brother 7 figure 8

Claims (1)

[Claims] 1. First and second field effect transistors constituting a flip-flop, means for connecting one end of the first transistor and the gate of the second transistor, and one end of the second transistor. and a third field effect transistor connected between one end of the first transistor and the first precharge node and having a gate connected to the gate of the first transistor. a fourth field effect transistor having one end connected to one end of the first transistor and a gate connected to the first precharge node; means for precharging the first precharge node; and one end of the second transistor. a fifth field effect transistor connected between the second precharge node and the gate of the second transistor; and one end of the field effect transistor connected to the second precharge node. An amplifier circuit characterized in that it has a sixth field effect transistor connected thereto and means for precharging a second precharge node. 2 Claims characterized in that the precharging means at the first and second precharging nodes precharges from the third and fifth transistors by setting one end of each of the first and second transistors to the same potential. 1st
Amplification circuit described in section. 3 first and second field effect transistors constituting a flip-flop, a first input/output node connected to one end of the first transistor and the gate of the second transistor, one end of the second transistor and a second input/output node connected to the gate of the first transistor; a third field effect transistor connected between the first input/output node and the third node; a fourth field effect transistor whose gate is connected to the output node and the third node; a fifth field effect transistor whose gate is connected between the second input/output node and the fourth node; a sixth field effect transistor whose gate is connected to the second input/output node and a fourth node, a first capacitor and a seventh field effect transistor whose one end is connected to the third node, respectively; means for connecting the other end of the seventh transistor to a power supply; means for supplying charge from the power supply to the other end of the fourth transistor; and a second capacitor and a second capacitor each having one end connected to the fourth node. An amplifier circuit comprising a No. 8 field effect transistor, means for connecting the other end of the eighth field effect transistor to a power supply, and means for supplying charge from the power supply to the other end of the sixth transistor. .