JP2574145B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2574145B2 JP2574145B2 JP60099212A JP9921285A JP2574145B2 JP 2574145 B2 JP2574145 B2 JP 2574145B2 JP 60099212 A JP60099212 A JP 60099212A JP 9921285 A JP9921285 A JP 9921285A JP 2574145 B2 JP2574145 B2 JP 2574145B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- metal bump
- metal
- layer
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
- H10W72/01251—Changing the shapes of bumps
- H10W72/01255—Changing the shapes of bumps by using masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔概要〕 集積度を向上するため、半導体チップの表面に金属バ
ンプを設け、これを介して複数の半導体チップを対向し
て接続してなるハイブリッド型の半導体装置がある。こ
の構造が、ガリウムヒ素、インジウムアンチモン等、極
低温に冷却して使用することが必要である半導体装置に
使用されると、熱膨張・収縮にもとづく金属疲労のた
め、金属バンプが破損しやすい。特に、一方のチップが
シリコンで他方がガリウムヒ素である等異種の半導体の
場合、その傾向が大きい。この欠点を防ぐためには金属
バンプの高さを高くすればよいが、この高さは、金属バ
ンプの製造方法の関係上、フォトレジストの厚さによっ
て制限を受ける。この制限を回避するには多層にすれば
よいが、位置合わせ誤差等の関係で多層とすることは容
易ではない。そこで、上層ほど面積を大きくし且つ、上
層の厚さを十分厚くした多層として、高さの高い金属バ
ンプを実現して上記の欠点を解消したものである。DETAILED DESCRIPTION OF THE INVENTION [Overview] There is a hybrid type semiconductor device in which a metal bump is provided on a surface of a semiconductor chip and a plurality of semiconductor chips are connected to face each other via the metal bump in order to improve the degree of integration. . When this structure is used in a semiconductor device such as gallium arsenide or indium antimony that needs to be used after being cooled to an extremely low temperature, the metal bump is easily broken due to metal fatigue based on thermal expansion and contraction. In particular, when one chip is made of a different kind of semiconductor such as silicon and the other is gallium arsenide, the tendency is large. To avoid this drawback, the height of the metal bump may be increased, but this height is limited by the thickness of the photoresist due to the method of manufacturing the metal bump. In order to avoid this limitation, a multi-layer structure may be used, but it is not easy to form a multi-layer structure due to a positioning error. In view of the above, the above-described drawbacks have been solved by realizing a high-height metal bump as a multilayer in which the area becomes larger in the upper layer and the thickness of the upper layer is sufficiently thick.
本発明は、複数の半導体チップが金属バンプを介して
接続されてなるハイブリッド型の半導体装置の改良に関
する。特に、その金属バンプの高さを高くする改良に関
する。The present invention relates to an improvement in a hybrid semiconductor device in which a plurality of semiconductor chips are connected via metal bumps. In particular, the present invention relates to an improvement for increasing the height of the metal bump.
集積度を向上するため、半導体チップの表面に、金属
バンプと称する厚さの厚い柱状の金属膜を形成し、この
金属バンプを表面に有する半導体装置チップ2枚を対向
して接触し、金属バンプを介して接続してなるハイブリ
ッド型の半導体装置がある。In order to improve the degree of integration, a thick columnar metal film called a metal bump is formed on the surface of the semiconductor chip, and two semiconductor device chips having the metal bump on the surface are opposed to and contact with each other. There is a hybrid type semiconductor device that is connected through a.
ところが、ガリウムヒ素等のキャリヤー移動度は極低
温において大きくなるので、ガリウムヒ素半導体装置は
極低温で使用することが望ましい。また、インジウムア
ンチモン等赤外線用の光半導体装置も極低温で使用する
必要がある。そのため、これらの半導体装置は、常温と
極低温の間を往復する機会が多い。However, since the carrier mobility of gallium arsenide or the like becomes large at extremely low temperatures, it is desirable to use the gallium arsenide semiconductor device at extremely low temperatures. In addition, it is necessary to use an optical semiconductor device for infrared light such as indium antimony at an extremely low temperature. Therefore, these semiconductor devices have many opportunities to reciprocate between room temperature and extremely low temperature.
金属バンプを介して接続されてなるハイブリッド型の
半導体装置が上記のサーマルサイクリングに曝される
と、膨張収縮のため、金属バンプが破損する機会が多
い。一方のチップがシリコンで他方のチップがガリウム
ヒ素である場合等、異種の半導体の組み合わせをもって
構成されている場合にこの傾向が大きく、欠点は顕著で
ある。When a hybrid semiconductor device connected via a metal bump is exposed to the above-described thermal cycling, the metal bump often breaks due to expansion and contraction. This tendency is significant when the chip is composed of a combination of different types of semiconductors, such as when one chip is silicon and the other chip is gallium arsenide, and the disadvantage is significant.
これを防止するためには、金属バンプの高さを高くす
ればよいが、金属バンプは一般にリフトオフ法使用して
形成されるため、その高さはフォトレジスト膜の膜厚に
よって制限され、5〜6μm程度が限度であり、金属バ
ンプの高さを高くして上記の欠点を回避することは容易
ではない。In order to prevent this, the height of the metal bumps may be increased. However, since the metal bumps are generally formed by using a lift-off method, the height is limited by the thickness of the photoresist film. The limit is about 6 μm, and it is not easy to increase the height of the metal bumps to avoid the above-mentioned disadvantages.
本発明の目的は、この欠点を解消することにあり、金
属バンプの高さが高く、サーマルサイクリングに曝され
ても破損しない半導体装置の製造方法を提供することに
ある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device in which the height of a metal bump is high and which is not damaged even when subjected to thermal cycling.
本発明に係る半導体装置の要旨に係る金属バンプ10の
断面図を第1図に示す。本発明に係る半導体装置は、複
数の半導体装置チップが金属バンプ10を介して接続され
ている半導体装置において、金属バンプ10は、第1の開
口を有する第1のレジストパターンを用いて、第1の開
口内に表出する下地上に形成した下層6と、第1の開口
より大きな第2の開口を有する第2のレジストパターン
を用いて、第2の開口内に表出する下地及び下層6上に
形成した上層9とを含む多層構造であり、上層9の面積
は、下層6の面積より大きい半導体装置である。FIG. 1 is a cross-sectional view of the metal bump 10 according to the gist of the semiconductor device according to the present invention. In a semiconductor device according to the present invention, in a semiconductor device in which a plurality of semiconductor device chips are connected via metal bumps 10, the metal bumps 10 are formed by using a first resist pattern having a first opening. A lower layer 6 formed on the base exposed in the second opening and a second resist pattern having a second opening larger than the first opening, using the lower layer 6 and the lower layer 6 exposed in the second opening. The semiconductor device has a multilayer structure including an upper layer 9 formed thereon, and the area of the upper layer 9 is larger than the area of the lower layer 6.
高さの高い金属バンプを形成するには金属バンプを多
層とすればよいが、位置合わせ誤差のため、正確に積層
することができず、また、第2層、第3層形成用のフォ
トレジスト膜の形成が困難であるから多層の金属バンプ
は形成が困難である。To form a metal bump having a high height, the metal bump may be formed in a multilayer structure. However, the metal bump cannot be laminated accurately due to an alignment error. Since it is difficult to form a film, it is difficult to form a multilayer metal bump.
そこで、これらの制約を回避するため、上層になるほ
ど面積を大きくすることとして、位置合わせ誤差の裕度
を確保し、上層形成用のフォトレジスト膜の塗布を可能
とし、その結果、多層の金属バンプの製造を可能にし
て、高さの高い金属バンプを実現したものである。Therefore, in order to avoid these restrictions, the area is increased as the upper layer is formed, so that a margin for alignment error is secured, and a photoresist film for forming the upper layer can be applied. And a metal bump having a high height is realized.
以下、図面を参照しつゝ、本発明の一実施例に係る半
導体装置の要旨に係る高さの高い金属バンプの製造方法
についてさらに説明する。Hereinafter, with reference to the drawings, a method for manufacturing a tall metal bump according to the gist of a semiconductor device according to an embodiment of the present invention will be further described.
第2図参照 半導体基板1上にフィールド絶縁膜2が形成され、そ
の一部領域上に引き出し電極3が形成された状態におい
て、フォトレジスト膜4を6〜7μm程度の厚さに形成
し、フォトリングラフィー法を使用してこのフォトレジ
スト膜4をバンプ形成領域から幅20μm程度の正方形状
に除去し、インジウム膜5を厚さ5〜6μm程度に形成
する。Referring to FIG. 2, in a state where a field insulating film 2 is formed on a semiconductor substrate 1 and a lead electrode 3 is formed on a partial region thereof, a photoresist film 4 is formed to a thickness of about 6 to 7 μm. The photoresist film 4 is removed from the bump formation region into a square shape having a width of about 20 μm by using a lithography method, and an indium film 5 is formed to a thickness of about 5 to 6 μm.
第3図参照 フォトレジスト膜4を溶解除去して、第1層金属バン
プ6をリフトオフ形成する。Referring to FIG. 3, the photoresist film 4 is dissolved and removed, and the first layer metal bumps 6 are lifted off.
つゞいて、フォトレジスト膜7を6〜7μm程度の厚
さに形成し、フォトリングラフィー法を使用して、この
フォトレジスト膜7を、上記の第1層金属バンプ6を囲
む幅40μm程度の正方形状の領域から除去し、インジウ
ム膜8を厚さ5〜6μm程度に形成する。Subsequently, a photoresist film 7 is formed to a thickness of about 6 to 7 μm, and this photoresist film 7 is formed into a thickness of about 40 μm surrounding the first layer metal bump 6 by using a photolithography method. The indium film 8 is removed from the square region to form an indium film 8 having a thickness of about 5 to 6 μm.
第1図参照 フォトレジスト膜7を溶解除去して、第2層金属バン
プ9をリフトオフ形成し、第1層金属バンプ6との二重
層よりなり、高さの高い金属バンプ10を形成する。Referring to FIG. 1, the photoresist film 7 is dissolved and removed, and the second-layer metal bumps 9 are lifted off to form a metal bump 10 having a double layer with the first-layer metal bumps 6 and having a high height.
多少の位置合わせ誤差は避けられないが、上層ほど面
積が大きくしてあるので、高さの高い金属バンプが形成
される。Although some positioning errors are inevitable, the higher the upper layer, the larger the metal bumps are formed.
以上説明せるとおり、本発明においては、上層の面積
が下層の面積よりも大きく上層の厚さが少なくとも下層
の厚さと同程度にしてある柱状金属層が積層されて多層
とされ、この多層の金属層をもって金属バンプが構成さ
れているので、高さの高い金属バンプを有する半導体装
置が提供される。As described above, in the present invention, a columnar metal layer in which the area of the upper layer is larger than the area of the lower layer and the thickness of the upper layer is at least about the same as the thickness of the lower layer is laminated to form a multilayer, Since the metal bumps are constituted by the layers, a semiconductor device having a metal bump having a high height is provided.
第1図は、本発明に係る半導体装置の要旨に係る金属バ
ンプの断面図である。 第2〜3図は、本発明の一実施例に係る半導体装置の主
要製造工程完了後の基板断面図である。 1……半導体基板、2……フィールド絶縁膜、3……引
き出し電極、4……フォトレジスト膜、5……インジウ
ム膜、6……第1層金属バンプ、7……フォトレジスト
膜、8……インジウム膜、9……第2層金属バンプ、10
……金属バンプ。FIG. 1 is a sectional view of a metal bump according to the gist of the semiconductor device according to the present invention. 2 and 3 are cross-sectional views of the semiconductor device according to one embodiment of the present invention after the main manufacturing steps are completed. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Field insulating film, 3 ... Lead electrode, 4 ... Photoresist film, 5 ... Indium film, 6 ... First layer metal bump, 7 ... Photoresist film, 8 ... ... Indium film, 9 ... Second layer metal bump, 10
...... Metal bumps.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭55−150279(JP,A) 特開 昭57−207362(JP,A) 特公 昭51−4633(JP,B1) ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-55-150279 (JP, A) JP-A-57-207362 (JP, A) JP-B-51-4633 (JP, B1)
Claims (1)
0)を介して接続されてなる半導体装置において、 前記金属バンプ(10)は、第1の開口を有する第1のレ
ジストパターンを用いて、前記第1の開口内に表出する
下地上に形成した下層(6)と、 前記第1の開口より大きな第2の開口を有する第2のレ
ジストパターンを用いて、前記第2の開口内に表出する
前記下地及び前記下層(6)上に形成した上層(9)と
を含む多層構造であり、 前記上層(9)の面積は、前記下層(6)の面積より大
きい ことを特徴とする半導体装置。A plurality of semiconductor device chips are connected to a metal binder (1).
0), wherein the metal bump (10) is formed on a base exposed in the first opening by using a first resist pattern having a first opening. Formed on the underlayer and the lower layer (6) exposed in the second opening by using a lower layer (6) formed and a second resist pattern having a second opening larger than the first opening. And an upper layer (9), wherein the area of the upper layer (9) is larger than the area of the lower layer (6).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60099212A JP2574145B2 (en) | 1985-05-10 | 1985-05-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60099212A JP2574145B2 (en) | 1985-05-10 | 1985-05-10 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61256745A JPS61256745A (en) | 1986-11-14 |
| JP2574145B2 true JP2574145B2 (en) | 1997-01-22 |
Family
ID=14241347
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60099212A Expired - Fee Related JP2574145B2 (en) | 1985-05-10 | 1985-05-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2574145B2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS514633A (en) * | 1974-07-02 | 1976-01-14 | Showa Denko Kk | KAITENSHIKI ABURABAANAA |
| JPS55150279A (en) * | 1979-05-10 | 1980-11-22 | Fujitsu Ltd | Infrared ray camera device |
| JPS57207362A (en) * | 1981-06-16 | 1982-12-20 | Mitsubishi Electric Corp | Semiconductor device |
-
1985
- 1985-05-10 JP JP60099212A patent/JP2574145B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61256745A (en) | 1986-11-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |