JP3305807B2 - Semiconductor chip mounting structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip mounting structure such as a semiconductor package.

[0002]

2. Description of the Related Art A semiconductor chip is usually mounted on a plastic package, a ceramic package, or the like for the purpose of protection from an external environment and improvement of handling. As a method of mounting a semiconductor chip on such a package, first, a tape carrier so-called TA
There is known a method of bonding a semiconductor chip to a B (tape automated bonding) tape and mounting the TAB chip in a package.

Conventionally, when a tape carrier type semiconductor chip as described above is mounted on a package, FIG.
As shown in FIGS. 1A and 1B, a semiconductor chip 2 bonded to a lead 1 of a TAB tape is connected to a package multilayer circuit board having lead connection pads 3 provided on its surface, for example, a ceramic multilayer circuit board 4. The lead 1 of the TAB tape is connected to the lead connection pad 3 on the ceramic multilayer circuit board 4 (connection portion 5). In the drawing, reference numeral 6 denotes a support ring, which is provided on the upper surface side of the TAB lead 1. In a conventional ceramic multilayer circuit board 4 on which such a TAB chip is mounted, as shown in FIG. 7, the lead connection pads 3 are formed in a single row.
Are connected in a single row.

By the way, the number of input / output signals to / from the semiconductor chip has been increasing year by year due to recent high integration of the semiconductor chip and the like, so that the pitch for forming the TAB lead tends to be further narrowed. Therefore, the lead connection pads on the circuit board side must also be formed at a narrow pitch. However, with the conventional lead connection pads formed in a single row,
As the pad formation pitch becomes narrower, alignment with the TAB lead becomes extremely difficult, and there is a problem that a connection failure between the TAB lead and the lead connection pad is likely to occur.

On the other hand, with respect to a circuit board on which a semiconductor chip is mounted, fine wiring technology such as thin film wiring must be applied to the surface wiring layer including the lead connection pads in order to form lead connection pads at a narrow pitch. However, the manufacturing cost of the semiconductor package is increased. Further, even if a thin film wiring or the like is applied, the allowable range of the positional deviation between the TAB lead and the lead connection pad does not change, so that the problem of poor connection cannot be solved.

[0006]

As described above, the mounting structure of the conventional TAB chip cannot sufficiently cope with the narrowing of the lead pitch, resulting in poor connection between the TAB lead and the pad for lead connection. This causes problems such as an increase in manufacturing cost.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and stably connects a TAB lead to a lead connection pad even when the pitch for forming the TAB lead is narrowed. It is an object of the present invention to provide a semiconductor chip mounting structure capable of performing the above and preventing an increase in manufacturing cost.

[0008]

According to the present invention, there is provided a semiconductor chip mounting structure comprising a ceramic multilayer circuit board having a plurality of rows of lead connection pads on the surface of a semiconductor chip bonded to a tape carrier having a plurality of support rings. A semiconductor chip mounted on the tape carrier, wherein a semiconductor chip bonded to the tape carrier is arranged such that the plurality of support rings are positioned on the ceramic multilayer circuit board side, and the lead of the tape carrier is provided. And a connection portion between the portion and the lead connection pad of the ceramic multilayer circuit board is mounted in a plurality of rows.

[0009]

In the semiconductor chip mounting structure of the present invention,
Since the lead connection pads are arranged in a plurality of rows, the distance between the lead connection pads in each pad row can be set sufficiently large, and thus the width of the lead connection pads can be made sufficiently large. . Thereby, even for the lead portion of the tape carrier having a narrow pitch, it is possible to set the lead position deviation allowable range widely, so that the lead portion and the lead connection pad can be favorably aligned, It is possible to stably prevent the occurrence of connection failure. Further, since a plurality of support rings are arranged on the ceramic multilayer circuit board side, even if the connection portions are arranged in a plurality of rows as described above, it is possible to prevent a short circuit at a portion other than the connection portions. Furthermore, since it is possible to set sufficiently wide distance between lead connection pads, without applying a fine wiring technology for thin film wiring or the like, it is possible to form the lead connection pads, the increase in manufacturing cost Can be prevented.

[0010]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a view showing the configuration of an embodiment of a semiconductor package to which the semiconductor chip mounting structure of the present invention is applied. FIG. 1 (a) is a sectional view of a main part thereof, and FIG. 1 (b).
FIG. 3 is a plan view of a main part. In the figure, reference numeral 11 denotes a semiconductor chip, and bumps 1 provided on the semiconductor chip 11 are provided.
A TAB lead 12 is bonded to 1a. FIG. 1 shows a state after the semiconductor chip 11 is mounted on the circuit board 14. The semiconductor chip 11 is a so-called TAB chip which is bonded and supported on a TAB tape as a tape carrier.

On the circuit board 14 side of the TAB lead 12, a plurality of support rings 13a, 13b, 13c (three in this embodiment) are provided.
2 prevents short-circuiting at portions other than the connection portion.

On the other hand, the circuit board 14 on which the TAB chip 1 is mounted is, for example, a ceramic multilayer circuit board. Various insulating ceramics can be used as a constituent material of the ceramic multilayer circuit board, and examples thereof include aluminum nitride, aluminum oxide, and silicon nitride. In particular, since the aluminum nitride multilayer circuit board has excellent thermal conductivity, it can cope with an increase in the number of input / output signals, achieve high heat dissipation as a package, and reduce the size of the multilayer circuit board. It is possible to do.

A lead connection pad 15 is provided on the surface of the ceramic multilayer circuit board 14. As shown in FIG. 2, the lead connection pad 15 includes a plurality of pad rows 16a, 16b, 16c (3 in this embodiment).
Columns). Then, the pad row 16a
From the pad rows 16a to 16c so that the pitch between adjacent lead connection pads 15 corresponds to the pitch at which the TAB leads 12 are formed.
b, 16c are formed. In other words, pad row 1
Pitch between the lead connection pads 15 adjacent between the pad row 16a and the pad row 16b, the pad row 16b and the pad row 1
The formation pitch between the lead connection pads 15 adjacent to each other and the formation pitch between the lead connection pads 15 between the pad row 16c and the pad row 16a correspond to the formation pitch of the TAB leads 12, respectively. Each lead connection pad 15 is connected to an external terminal 18 such as an I / O pin for connection to a mounting board via a signal wiring 17 inside the ceramic multilayer circuit board 14. In addition, 1 in the figure
9 is a via hole that becomes a part of the signal wiring 17.

The shape of the lead connection pad 15 is as follows.
The concentric connection formed around the via hole 19 as shown in FIG. 2 is not limited to the configuration in which a rectangular pad portion is provided. For example, as shown in FIG. A continuous rectangular shape, a concentric connection formed around the via hole 19 as a pad portion as shown in FIG. 4, and a via hole 19 directly as a pad portion as shown in FIG. Various shapes can be used, such as those described above.

The TAB lead 12 bonded to the semiconductor chip 11 is connected to the lead connection pad 15 of the ceramic multilayer circuit board 14 as described above.
Are sequentially connected between the support rings 13 and TA
Connection part 20 between B lead 12 and lead connection pad 15
Is composed of a plurality of columns.

In the semiconductor package of the embodiment described above, the lead connection pads 15 are
a, 16b, and 16c, the distance between the lead connection pads 15 in each pad row can be set sufficiently large.
5 can be made sufficiently wide. As a result, it is possible to set a wide allowable range of lead position deviation even for a TAB lead 12 having a narrow pitch.
The lead 12 and the lead connection pad 15 can be favorably aligned, and the occurrence of connection failure can be stably prevented. Also, as shown in FIG.
Even if the connecting portion 20 between the lead connection pad 15 and the lead connection pad 15 is formed in a plurality of rows, the TAB lead 12 is provided with a plurality of support rings 13a, 13b, and 13c on the circuit board 14 side. A short circuit can be prevented at portions other than the connection portion.

Next, a specific example of the semiconductor package will be described.

That is, a TAB chip 1 in which TAB leads 12 having a width of 50 μm are bonded at a formation pitch of 100 μm.
1 was used to fabricate a semiconductor package. The lead connection pad 15 on the surface of the ceramic multilayer circuit board 14 has a width.
200μm and the formation pitch in each pad row is 300μ
As m, the pad rows 16a, 16b and 16c were each formed by normal screen printing. Ceramic multilayer circuit board 14 having such lead connection pads 15
In response to the above, the connecting portion 20 connects the TAB chip 11
Joined in rows. In this semiconductor package, the lead width is 50 μm, and the lead connection pad width is 200
Because of the μm, a lead position deviation of ± 70 μm was acceptable, and a good TAB connection could be implemented.

On the other hand, in the conventional semiconductor package shown in FIGS. 6 and 7, a TAB chip having the same shape was mounted. In order to support this TAB chip, the width of the lead connection pad is 60 μm and the pitch is
100 μm (single row). Since such wiring cannot be formed by screen printing, a thin film fine wiring was used. The above-described TAB chip was joined to the ceramic multilayer circuit board having such lead connection pads such that the connection portions were arranged in a single row. In this semiconductor package, the lead width is 50 μm and the pad width for lead connection is 60 μm.
m, only a lead position deviation of ± 5 μm could be tolerated, and the cost was increased due to thin-film fine wiring, and connection failure occurred.

In the above embodiment, an example is shown in which the semiconductor chip mounting structure of the present invention is applied to a PGA (pin grid array) package, but various semiconductors such as an LGA (land grid array) package and a QFP package are used. The present invention can be applied to a package, general board mounting, and the like.

[0022]

As described above, according to the semiconductor chip mounting structure of the present invention, even when the pitch for forming the leads of the tape carrier is narrowed, the connection between the leads and the pads for lead connection is stabilized. You can do
In addition, it is possible to provide a mounting structure at low cost.

[Brief description of the drawings]

FIG. 1 is a view showing a configuration of a semiconductor package according to an embodiment to which a semiconductor chip mounting structure of the present invention is applied,
(A) is a sectional view of the main part, and (b) is a plan view of the main part.

FIG. 2 is a diagram illustrating an example of the arrangement of lead connection pads on a multilayer circuit board in the semiconductor chip illustrated in FIG. 1;

FIG. 3 is a diagram showing another configuration example of the lead connection pad.

FIG. 4 is a diagram showing still another configuration example of a lead connection pad.

FIG. 5 is a diagram showing still another configuration example of the lead connection pad.

6A and 6B are diagrams showing a configuration of a conventional semiconductor package, in which FIG. 6A is a sectional view of a main part thereof, and FIG. 6B is a plan view of a main part thereof.

FIG. 7 is a diagram showing an example of the arrangement of lead connection pads on a multilayer circuit board in the conventional semiconductor chip shown in FIG. 6;

[Explanation of symbols]

 11 Semiconductor chip (TAB chip) 12 TAB lead 13a, 13b, 13c Support ring 14 Ceramic multilayer circuit board 15 Lead connection pad 16a, 16b, 16c Pad row

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/60 311

Claims (4)

(57) [Claims] 1. A semiconductor chip mounting structure in which a semiconductor chip joined to a tape carrier having a plurality of support rings is mounted on a ceramic multilayer circuit board having a plurality of rows of lead connection pads on the surface, A semiconductor chip joined to the tape carrier is arranged so that the plurality of support rings are positioned on the ceramic multilayer circuit board side, and a lead portion of the tape carrier and a lead connection pad of the ceramic multilayer circuit board are arranged. A semiconductor chip mounting structure, wherein connection portions are mounted in a plurality of rows. 2. The semiconductor chip mounting structure according to claim 1, wherein the ceramic multilayer circuit board includes an insulating ceramic selected from aluminum nitride, aluminum oxide, and silicon nitride as a constituent material. Chip mounting structure. 3. The semiconductor chip mounting structure according to claim 1, wherein the ceramic multilayer circuit board has a via hole. 4. The semiconductor chip mounting structure according to claim 1, wherein said semiconductor chip mounting structure is a PGA package, and
A semiconductor chip mounting structure, which is an A package or a QFP package.