JP2575106B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for activating and reflowing by lamp annealing (RTA).

[Summary of the Invention]

The present invention relates to a method of manufacturing a semiconductor device in which an impurity region is activated or an interlayer insulating film is reflowed by heat treatment, wherein the heat treatment is performed in a short time by infrared irradiation by lamp annealing, thereby simplifying the manufacturing process and out-diffusion. And the controllability of the junction depth is improved.

[Conventional technology]

Generally, in the manufacturing process of a semiconductor device such as a MOS transistor, after the source and drain regions of the MOS transistor are formed on a substrate by ion implantation, these regions are activated. After being deposited, reflow may take place.

Such activation and reflow are performed by a heat treatment. As a heat source, there is a method using a laser beam, an electron beam, a lamp, or the like in addition to a conventionally used electric furnace.

Here, MO is used as an example of a conventional method for manufacturing a semiconductor device.
The activation step and the reflow step of the impurity region of the S transistor will be described.

As shown in FIG. 7, a conventional method of manufacturing a semiconductor device includes, as shown in FIG. 7, an annealing step Q2 for activating the source and drain regions from an ion implantation step Q1 for forming a source region and a drain region. Thereafter, the steps are performed in the order of a deposition step Q3 for depositing an impurity-containing insulating film such as PSG (phosphorus silicate glass) as an interlayer insulating film.
After the formation of the impurity-containing insulating film, a reflow process Q5 for planarizing the impurity insulating film is performed, for example, through a window opening process Q4 for making a contact.
Note that a process such as electrode formation may be included as a process before the reflow process Q5, but description thereof will be omitted.

Here, the reflow step Q5 will be described. In order to reflow the impurity-containing insulating film, after the insulating film is formed, the substrate is placed in a furnace (electric furnace) together with a predetermined temperature (for PSG, 1050 ° C), time (eg 1
(For about 0 minutes).

At this time, it is experimentally known that the junction depth x increases. That is, impurities for forming source and drain regions, for example, B ⁺ and BF ₂ ⁺ are implanted under the conditions of 50 keV and 2 to 3 × 10 ¹⁵ / cm ² , and the conditions (normally performed at 950 ° C., 2
0 minutes), the junction depth x is approximately
Although it becomes about 0.3 μm, it is redistributed through the heat treatment performed in the reflow step Q5, and the junction depth x is about 0.
It is about 5 μm.

[Problems to be solved by the invention]

In accordance with the trend toward miniaturization of semiconductor devices, it is required to reduce the junction depth for higher performance.

However, a shallow junction cannot be realized by the above-described process. This is because redistribution of impurities as described above in the reflow step Q5 is particularly problematic.

In addition, before the reflow step Q5, there is a window opening step Q4, for the purpose of simplifying the step, patterning the impurity-containing insulating film above the source and drain regions, and forming a contact with the source and drain regions. After forming such a contact hole, the impurity-containing insulating film may be reflowed in some cases. When the contactor hole is opened and exposed in this way, a phenomenon such as so-called out diffusion in which impurities in the surface layer escape into the gas to be contacted or the like during the heat treatment tends to occur.

That is, as shown in FIG. 8A, the impurity concentration distribution N after the annealing step Q2 is a curve falling rightward from the surface layer portion (junction depth x = 0). However, as shown in FIG. 8B, in the conventional reflow process Q5, the temperature is 1050 ° C.
The heat treatment is performed for 10 minutes, so that the junction depth x is increased to about 0.5 μm, and furthermore, the concentration of impurities in the surface layer portion (symbol OD in FIG.
Indicated by ) Lowers, causing adverse effects such as an increase in resistance due to reflow. 8A and 8B, the vertical axis represents the impurity concentration N, and the horizontal axis represents the junction depth x.

In the manufacturing process of a semiconductor device, there is a demand for simplification of a manufacturing process in order to reduce costs and the like. However, a conventional method of manufacturing a semiconductor device requires a large number of steps and requires a long time for processing. It depends a lot.

In view of the above problems, an object of the present invention is to disclose a method of manufacturing a semiconductor device that simplifies a manufacturing process, suppresses out diffusion, and improves controllability of a junction depth.

[Means for solving the problem]

The present invention forms an arsenic silicate glass film or a boron phosphorus silicate glass film which can be reflowed at a temperature not higher than the activation temperature of the impurity region on an element having an impurity region, and activates the impurity region by lamp annealing and The above-mentioned problem is solved by a method of manufacturing a semiconductor device in which an arsenic silicate glass film or a boron phosphorus silicate glass film is simultaneously reflowed.

[Action]

As the impurity-containing insulating film to be reflowed, an arsenic silicate glass (AsSG) film or a boron phosphorus silicate glass (BPSG) film having a property of being reflowable at a temperature lower than the activation temperature, that is, 1100 ° C. or lower is used. . An infrared lamp that performs heat treatment in a short time is used as a time condition. Therefore, there is no problem that the junction depth is increased even if activation and reflow are performed at the same time. Further, since lamp annealing is performed, it is possible to eliminate adverse effects such as out diffusion. Then, since activation and reflow are performed simultaneously, what was conventionally two steps becomes a single step, and the manufacturing process can be simplified.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

As the impurity-containing insulating film used in the method for manufacturing a semiconductor device of the present invention, the activation temperature of the impurity region or less, that is,
An AsSG film or a BPSG film that can be reflowed at a low temperature of 1100 ° C. or lower can be used. Further, as the infrared lamp used for the lamp annealing of the present invention, a lamp that emits continuous incoherent light having a wavelength of 0.4 to 4.0 μm is preferable.

This embodiment describes an example of a MOS transistor as a method of manufacturing a semiconductor device, uses an AsSG film as an impurity-containing insulating film, and uses an infrared lamp beam such as a halogen lamp as a heat source for performing a short-time heat treatment.

First, as shown in FIG. 1, in the method of manufacturing a semiconductor device according to the present embodiment, after an ion implantation step P1 for forming source and drain regions of a MOS transistor, an impurity-containing insulating film, that is, an AsSG film is used as an interlayer insulating film. Deposition process P2
It has become. Here, ion implantation is performed, for example, by a usual method such as BF ₂ ⁺
Is implanted into a predetermined region under the conditions of 50 keV and 2-3 × 10 ¹⁵ / cm ² , and the AsSG film is
It is applied to a thickness of about 5000 mm. This AsSG film
The As content is about 20 wt%, but is not particularly limited, and can be optimized by the temperature and time conditions of the reflow performed in a later step.

After the deposition step P2 for depositing the interlayer insulating film, a window opening step P3 is performed. In the window opening step P3, a predetermined region of the AsSG film corresponding to the upper part of the source and drain regions of the MOS transistor is subjected to photolithography. The window is opened using technology.

After the window opening step P3, annealing and activation are performed simultaneously with the activation of the impurity implanted in the ion implantation step P1 and the reflow of the AsSG film deposited in the interlayer insulating film deposition step P2.
This is the reflow process P4. In the annealing / reflow step P4, the annealing and the reflow are simultaneously performed by a short-time heat treatment. The lamp annealing is performed using an infrared lamp beam, and a sufficient reflow characteristic can be obtained in about 10 seconds as described later due to its short-time heating performance. As the temperature condition, for example, when the interlayer insulating film to be deposited is an AsSG film or a BPSG film as described above, fluidization at a lower temperature is possible as compared with PSG (phosphorus silicate glass) or the like. Therefore, it is possible to easily set the temperature, and it is possible to set conditions compatible with the activation of the S / D layer.

Simultaneously with this reflow, annealing is also performed by a high-temperature heat treatment in a short time.
Due to the number of times, a shallow junction can be formed and maintained without re-diffusion of the junction. Similarly, since the time is short, adverse effects such as out-diffusion can be suppressed.

The characteristics of such reflow will be described based on data of an experiment conducted by the present inventors.

First, the temperature dependence of reflow will be described.
The temperature dependence of the reflow has such a characteristic that it gradually rises to the right as shown in FIG. Here, the horizontal axis represents temperature, while the vertical axis uses numerical values A / B quantifying the shape of reflow. Lamp annealing time is 10
For example, at 1050 ° C. for 10 seconds, A / B has a value of about 2.12, where A / B is the distance A between the top opening of the interlayer insulating film and the bottom A as shown in FIG. This is the ratio of the opening B. Therefore, the larger the value of A / B, the larger the amount of reflow.

FIG. 2 shows, for reference, AsS using a conventional furnace (electric furnace) annealing (temperature: 900 ° C., time: 10 minutes).
An example in which the G film is reflowed is also shown.

Compared to this conventional example, when the AsSG film is used for the interlayer insulating film, it is possible to obtain the same or better reflow characteristics in a short time of about 10 seconds at a temperature condition of 1050 ° C. to 1150 ° C. I understand.

 Next, the time dependency of reflow will be described.

As shown in FIG. 3, the time dependency of the reflow has an exponential rising characteristic. Sufficient reflow characteristics are obtained in about 10 seconds of infrared irradiation, and the AsSG film tends to flow gradually with irradiation of 10 seconds or more. Therefore, when reflow is performed effectively, irradiation with infrared rays for about 10 seconds is sufficient. In FIG. 3, time is plotted on the horizontal axis, and A / B values are plotted on the vertical axis, as in FIG. The temperature condition in this case is 1100 ° C.

From the above experimental data, the present inventor
When reflowing the SG film, the interlayer insulating film with a thickness of 5000 mm, use an infrared lamp beam, and temperature conditions of 1050 ~ 1100
It has been found that sufficient reflow can be performed at about 10 ° C. for about 10 seconds. Then, since the heat treatment is performed in such a short time of about 10 seconds, it is possible to easily remove the problems such as the outdiffusion, which have been a problem in the past.

In this way, using infrared lamp light, temperature condition 10
When reflow is performed at 50 to 1100 ° C. for about 10 seconds, annealing can be performed at the same time. That is, when annealing is performed simultaneously under the above-mentioned temperature conditions of 1050 to 1100 ° C. for about 10 seconds, the junction depth x does not increase,
A shallow junction can be formed with good reproducibility. When ion implantation is performed, for example, when BF ₂ ⁺ is implanted into a predetermined region under the conditions of 50 keV and 2 to 3 × 10 ¹⁵ / cm ² , and annealing is performed simultaneously under the above-described reflow condition, the junction depth x = 0.
Data such as 18 to 0.23 μm and sheet resistance ρs = 83 to 90Ω / □ are obtained.

As described above, the manufacturing method of the semiconductor device of the present embodiment uses the lamp light of the infrared ray to reflow the interlayer insulating film of the AsSG film and simultaneously anneal it. Conventionally, the reflow step and the annealing step are two independent steps. However, these can be integrated into a single process. As described above, reflow can be performed in a short period of time, and the adverse effects of out diffusion can be suppressed. In addition, a shallow junction can be easily obtained by simultaneous annealing.

An example of an infrared lamp device which realizes the method of manufacturing a semiconductor device according to the present embodiment having such excellent advantages is described in FIG.
This will be described with reference to the drawings.

As shown in FIG. 5, the infrared lamp device 3 is disposed above and below the quartz tube 2 in which a substrate 1 on which a semiconductor element is formed is placed. A plurality of halogen lamps 4 for emitting continuous incoherent light having a wavelength of 0.4 to 4.0 μm are attached to the infrared lamp device 3, and a parabolic reflector 5 is attached to each of the halogen lamps 4. I have. The substrate 1 is hollowly supported by a frame-shaped suspender 6, and the substrate 1 is irradiated with continuous incoherent light from each halogen lamp 4 on both main surfaces.

By performing the method of manufacturing a semiconductor device of this embodiment using such an infrared lamp device 3, the above-described predetermined effects can be obtained.

Here, a semiconductor device manufactured using the above-described method for manufacturing a semiconductor device of the present embodiment will be further described.

As shown in FIG. 6, in the semiconductor device manufactured by the method of manufacturing a semiconductor device according to the present embodiment, a silicon oxide film 12 serving as an element isolation region is formed on the main surface of a substrate 11 similarly to a normal MOSFET. The source region 16 and the drain region 17 are formed in the element formation region. Above the channel forming region between the source region 16 and the drain region 17, a gate electrode 14 is formed via a silicon oxide film 15. Then, an AsSG film 13 is formed as an insulating film over the source region 16 and the drain region 17 with openings 18 and 19 by opening a window, and reflow is performed.

When an impurity-containing insulating film that requires a high temperature for reflow, such as PSG, is used in a semiconductor device having such a structure, it is difficult to realize the semiconductor device due to factors such as aud diffusion and controllability of the junction depth. However, the impurity-containing insulating film
This is possible by using a material that can be reflowed at a low temperature, such as an AsSG film, and can be manufactured by applying the semiconductor device manufacturing method of the present embodiment. That is, the reflowed AsSG film 13
Is reflowed at a low temperature, so that even if activation and reflow are performed at the same time, it is possible to prevent the adverse effect of increasing the junction depth, and to perform heat treatment in a short time, thereby preventing out diffusion and the like. Is possible. Since the activation and the reflow are performed simultaneously, it is possible to simplify the manufacturing process in terms of the number of processes and time. In addition, since a semiconductor device can have a miniaturized structure and is reflowed as an insulating film, it is needless to say that various problems such as disconnection can be eliminated when a wiring layer is formed by deposition.

In the embodiment described above, the impurity-containing insulating film
AsSG membrane was used, but is not limited to this, for example, BPSG, BS
An insulating film that can be reflowed at a low temperature equal to or lower than the activation temperature of the impurity region such as G or SbSG can be used. Furthermore, it is a matter of course that reflow may be performed by the heat treatment according to the present invention after opening the window with respect to the impurity-containing insulating film formed between the first wiring layer and the second wiring layer.

〔The invention's effect〕

The method for manufacturing a semiconductor device of the present invention uses an AsSG film or a BPSG film having a reflowable substance at a temperature condition equal to or lower than the activation temperature of the impurity region as the impurity-containing insulating film to be reflowed, and can be heat-treated in a shorter time. Since lamp annealing is performed, there is no problem that the junction depth is increased even if activation and reflow are performed at the same time. Further, since heat treatment is performed in a short time, it is possible to eliminate adverse effects such as out diffusion. Since the activation and the reflow are performed simultaneously, the number of steps and the manufacturing process can be simplified in terms of time.

[Brief description of the drawings]

FIG. 1 is a process chart showing a method of manufacturing a semiconductor device according to the present invention in the order of steps, FIG. 2 is a characteristic diagram illustrating the temperature dependence of reflow according to the present invention, and FIG. FIG. 9 is a characteristic diagram illustrating the time dependency of the reflow, and FIG.
The figure is a schematic diagram illustrating reflow quantification. FIG. 5 is a sectional view showing an example of a device suitable for realizing the method of manufacturing a semiconductor device according to the present invention, and FIG. 6 is an example of a semiconductor device manufactured by the method of manufacturing a semiconductor device of the present invention. FIG. 7 is a process chart showing an example of a conventional method of manufacturing a semiconductor device in the order of steps, and FIG. 8A shows a distribution of impurity concentration after annealing in a conventional method of manufacturing a semiconductor device. FIG. 8B is a characteristic diagram showing a distribution of impurity concentration after reflow in a conventional method of manufacturing a semiconductor device. DESCRIPTION OF SYMBOLS 1 ... Substrate 3 ... Infrared lamp device 11 ... Substrate 13 ... AsSG film (impurity-containing insulating film) 16 ... Source region 17 ... Drain region 18,19 ... Opening

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-57-102052 (JP, A) JP-A-57-23223 (JP, A) JP-A-56-130949 (JP, A) JP-A-58-58 206121 (JP, A) JP-A-59-44846 (JP, A) JP-A-52-104087 (JP, A)

Claims (1)

(57) [Claims] An arsenic silicate glass film or a boron phosphorus silicate glass film which can be reflowed at a temperature not higher than the activation temperature of the impurity region is formed on an element having an impurity region, and lamp annealing is performed at a temperature of 1100 ° C. or less. A method of manufacturing a semiconductor device, comprising simultaneously activating the impurity region and reflowing the arsenic silicate glass film or the boron phosphorus silicate glass film.