JP2581371B2 - Film forming method for thin film transistor - Google Patents
Film forming method for thin film transistorInfo
- Publication number
- JP2581371B2 JP2581371B2 JP4019195A JP1919592A JP2581371B2 JP 2581371 B2 JP2581371 B2 JP 2581371B2 JP 4019195 A JP4019195 A JP 4019195A JP 1919592 A JP1919592 A JP 1919592A JP 2581371 B2 JP2581371 B2 JP 2581371B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- film transistor
- substrate
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010408 film Substances 0.000 title claims description 95
- 238000000034 method Methods 0.000 title claims description 22
- 239000010409 thin film Substances 0.000 title claims description 17
- 239000000758 substrate Substances 0.000 claims description 21
- 239000004065 semiconductor Substances 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 230000003746 surface roughness Effects 0.000 description 6
- 229910004205 SiNX Inorganic materials 0.000 description 5
- 238000010574 gas phase reaction Methods 0.000 description 5
- 238000006557 surface reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
- Chemical Vapour Deposition (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は、薄膜トランジスタ(T
FT)におけるアモルファスシリコン膜や多結晶シリコ
ン膜といったシリコン半導体膜と、これに積層されるゲ
ート絶縁膜(SiNx等)のプラズマCVD法による形
成方法に関する。The present invention relates to a thin film transistor (T
The present invention relates to a method of forming a silicon semiconductor film such as an amorphous silicon film or a polycrystalline silicon film in FT) and a gate insulating film (such as SiNx) laminated thereon by a plasma CVD method.
【0002】[0002]
【従来の技術】薄膜トランジスタにおけるシリコン半導
体膜やこれに積層されるゲート絶縁膜は、プラズマCV
D法により形成されることが多い。この場合、それら膜
を形成するための原料ガスのプラズマ化は、所定周波数
の高周波電力を連続的に印加する連続放電によってい
る。2. Description of the Related Art A silicon semiconductor film in a thin film transistor and a gate insulating film laminated thereon are formed by plasma CV.
Often formed by the D method. In this case, the source gas for forming these films is turned into plasma by continuous discharge in which high-frequency power of a predetermined frequency is continuously applied.
【0003】[0003]
【発明が解決しようとする課題】しかし、このような連
続放電によるプラズマCVDにより得られるシリコン半
導体膜やゲート絶縁膜はその表面粗度が30Å〜50Å
程度と平坦度がきわめて悪く、そのため、シリコン半導
体膜とこれに接するゲート絶縁膜の界面の平坦度が悪く
なり、その結果、ソース・ドレイン間の電子移動度が低
くなり(0.3cm2 /V・s以下)、最終製品トラン
ジスタの性能が満足できるものでなくなるという問題が
あった。However, the surface roughness of a silicon semiconductor film or a gate insulating film obtained by plasma CVD using such a continuous discharge is 30 ° to 50 °.
The degree of flatness is extremely poor, so that the flatness of the interface between the silicon semiconductor film and the gate insulating film in contact with the silicon semiconductor film is deteriorated. As a result, the electron mobility between the source and the drain is reduced (0.3 cm 2 / V). S or less), which causes a problem that the performance of the final product transistor is not satisfactory.
【0004】そこで本発明は、薄膜トランジスタ(TF
T)用のシリコン半導体膜及びこれに接するゲート絶縁
膜の界面の平坦度を向上させ、それによってTFTにお
けるソース・ドレイン間の電子移動度を大きくさせ得る
プラズマCVD法による薄膜トランジスタ用の膜形成方
法を提供することを目的とする。Therefore, the present invention provides a thin film transistor (TF)
A method for forming a film for a thin film transistor by a plasma CVD method capable of improving the flatness of an interface between a silicon semiconductor film for T) and a gate insulating film in contact therewith, thereby increasing electron mobility between a source and a drain in a TFT. The purpose is to provide.
【0005】[0005]
【課題を解決するための手段】本発明者は、前記連続放
電による原料ガスのプラズマ化によると、気相反応が律
促となり、反応種が基板から離れた位置から基板へ向け
降り注ぐことになるため、成膜表面粗度が大きくなって
しまうことに着目し、さらに研究を進め、パルス変調を
かけた高周波、換言すれば断続を繰り返す高周波を印加
すると、従来の気相反応だけでなく、基板表面及び(又
は)それに近い位置での反応(以下「表面反応」とい
う)も起こり、これによって、成膜表面粗度が小さくな
ることを見出し、本発明を完成した。According to the present inventor, according to the present invention, when the raw material gas is converted into plasma by the continuous discharge, the gas phase reaction is promoted, and the reactive species pours from a position away from the substrate toward the substrate. Therefore, focusing on the fact that the surface roughness of the film becomes large, further research has been carried out, and when applying a high frequency subjected to pulse modulation, in other words, applying a high frequency that repeats intermittent, not only the conventional gas phase reaction but also the substrate The present inventors have found that a reaction at the surface and / or at a position close thereto (hereinafter, referred to as “surface reaction”) also occurs, thereby reducing the surface roughness of the film formed, and completed the present invention.
【0006】すなわち本発明は、薄膜トランジスタ用の
シリコン半導体膜及びゲート絶縁膜をそれぞれプラズマ
CVD法により薄膜トランジスタ用の基板上に形成し、
前記それぞれの膜形成にあたり該膜形成のための原料ガ
スのプラズマ化を、基板への反応種の降り注ぎと基板表
面及び(又は)それに近い位置での反応種の供給とが交
互に行われて膜形成されるように、所定周波数の基本高
周波電力にパルス変調をかけた状態の高周波電力の印加
により行うことを特徴とする薄膜トランジスタ用の膜形
成方法(第1の方法)、及び、薄膜トランジスタ用のシ
リコン半導体膜としてアモルファスシリコン膜を、ゲー
ト絶縁膜として窒化シリコン膜を、それぞれプラズマC
VD法により薄膜トランジスタ用の基板上に形成し、前
記それぞれの膜形成にあたり該膜形成のための原料ガス
のプラズマ化を、100mTorrから600mTor
rの範囲内における成膜真空度下に、所定周波数の基本
高周波電力に400Hzから1000Hzの範囲内でパ
ルス変調をかけた状態の高周波電力の印加により行うこ
とを特徴とする薄膜トランジスタ用の膜形成方法(第2
の方法)を提供するものである。前記第1の方法におい
ても、前記パルス変調の条件として、前記両膜界面の平
坦度を向上させる観点から、また、成膜速度を低下させ
ない観点から例えば第2の方法と同様に400〜100
0Hzの条件が考えられる。That is, according to the present invention, a silicon semiconductor film and a gate insulating film for a thin film transistor are formed on a substrate for a thin film transistor by a plasma CVD method, respectively .
In forming each of the films, the plasma of the raw material gas for forming the film is formed by dropping reactive species onto the substrate,
Supply of reactive species at and / or near the surface
A basic height of a predetermined frequency so that the films are formed
A method for forming a film for a thin film transistor (first method), characterized in that the method is performed by applying high frequency power in a state where pulsed modulation is applied to the high frequency power;
An amorphous silicon film is used as a recon semiconductor film.
A silicon nitride film as a gate insulating film and a plasma C
Formed on a substrate for a thin film transistor by the VD method,
In each film formation, a source gas for the film formation
From 100 mTorr to 600 mTorr
Under a vacuum degree of film formation within the range of
Pass high frequency power within the range of 400 Hz to 1000 Hz.
This is performed by applying high-frequency power with
A film forming method for a thin film transistor (second
Method) . The first method smell
It is, as a condition of the pulse modulation, from the viewpoint to improve the flatness of both film interface, also reduce the deposition rate
From the point of view, for example , 400 to 100 as in the second method.
A condition of 0 Hz is conceivable.
【0007】[0007]
【作用】本発明方法によると、薄膜トランジスタ用のシ
リコン半導体膜及びこれに積層されるゲート絶縁膜は、
プラズマCVD法により順次、且つ、各膜の原料ガスを
パルス変調をかけた高周波電力の印加でプラズマ化する
ことにより形成される。パルス変調をかけた高周波電力
の印加、換言すれば断続的な高周波電力の印加によりプ
ラズマの発生、停止が繰り返されるので、基板又はその
上に先に形成された膜から離れた位置で反応種が生成さ
れる気相反応が起こるほか、プラズマ停止時に原料ガス
が基板表面又はその上に先に形成された膜表面及び(又
は)その近くまで達し、引き続きこれがプラズマ化され
ることで反応種がそれら表面及び(又は)その近くで生
成される表面反応も進み、その結果、表面粗度の小さい
膜が形成されることになり、シリコン半導体膜とこれに
接するゲート絶縁膜の界面の平坦度は良好となる。According to the method of the present invention, a silicon semiconductor film for a thin film transistor and a gate insulating film laminated thereon are
It is formed by a plasma CVD method in which the source gas of each film is turned into plasma by applying a pulse-modulated high-frequency power. The application and application of pulsed high-frequency power, in other words, the intermittent application of high-frequency power repeatedly generates and stops the plasma, so that the reactive species is separated from the substrate or the film previously formed thereon. In addition to the generated gas phase reaction, when the plasma is stopped, the source gas reaches the substrate surface or the surface of the film previously formed thereon and / or close to the substrate surface, and then this is converted into plasma, whereby the reactive species are converted to the reactive species. A surface reaction generated on the surface and / or near the surface also proceeds, and as a result, a film with small surface roughness is formed, and the flatness of the interface between the silicon semiconductor film and the gate insulating film in contact with the silicon semiconductor film is good. Becomes
【0008】[0008]
【実施例】以下、本発明の実施例を図面を参照して説明
する。図1は本発明方法の実施に使用するプラズマCV
D装置の一例の概略断面を示している。図示の装置は、
真空チャンバ1、該チャンバに電磁弁21を介して接続
した真空ポンプ2、チャンバ1内に設置した電極3、
4、チャンバ1に電磁弁61を介して接続した成膜用ガ
ス源5を備えている。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a plasma CV used for carrying out the method of the present invention.
1 shows a schematic cross section of an example of a D device. The device shown is
A vacuum chamber 1, a vacuum pump 2 connected to the chamber via an electromagnetic valve 21, an electrode 3 installed in the chamber 1,
4. A film forming gas source 5 connected to the chamber 1 via an electromagnetic valve 61 is provided.
【0009】電極3は接地電極であり、これには成膜温
度調節用のヒータ31が付設されている。電極4は高周
波電極であり、それ自体既に知られているマッチングボ
ックス8を介して高周波電源7から高周波電圧が印加さ
れる。高周波電源7は、任意の高周波パルス変調が可能
な高周波信号発生器71及び高周波増幅器(RFパワー
アンプ)72を有しており、所定周波数の高周波(図2
の(A)図参照)に所望のパルス変調をかけた高周波電
力(図2の(B)図参照)を印加できるように構成して
ある。The electrode 3 is a ground electrode, which is provided with a heater 31 for adjusting the film forming temperature. The electrode 4 is a high-frequency electrode, to which a high-frequency voltage is applied from a high-frequency power source 7 via a matching box 8 which is already known. The high-frequency power supply 7 has a high-frequency signal generator 71 and a high-frequency amplifier (RF power amplifier) 72 that can perform arbitrary high-frequency pulse modulation.
(A) in FIG. 2) and a high-frequency power (see FIG. 2 (B) in FIG.
【0010】以上説明した装置によると、本発明方法は
次のように実施される。シリコン半導体膜及びゲート絶
縁膜のうち前者を先に形成する場合、後者を先に形成す
る場合のいずれも考えられる。いずれにしても、これら
膜は順次形成される。最初の膜を形成するにあたって
は、先ず、成膜すべき基板9を電極3上に設置する。し
かるのち、チャンバ1内を電磁弁21の開成とポンプ2
の運転にて所定圧まで真空引きし、成膜用ガス源5から
最初の成膜用原料ガスをチャンバ内に導入し、且つ、チ
ャンバ内を所定成膜真空度に維持する。また、基板9を
ヒータ31にて所定成膜温度に制御する。次いで、電源
7にてこのガスにパルス変調された高周波電圧を印加し
て該ガスをプラズマ化させ、基板9上に成膜させる。同
様にして、次の原料ガス源を準備し、そのガスを用いて
次の膜を形成する。かくしてシリコン半導体膜とゲート
絶縁膜の積層が形成される。According to the apparatus described above, the method of the present invention is carried out as follows. It is conceivable that the former is formed first of the silicon semiconductor film and the gate insulating film, and the latter is formed first. In any case, these films are formed sequentially. In forming the first film, first, the substrate 9 to be formed is placed on the electrode 3. Thereafter, the opening of the solenoid valve 21 and the pump 2
In the operation described above, a vacuum is evacuated to a predetermined pressure, the first film forming material gas is introduced from the film forming gas source 5 into the chamber, and the inside of the chamber is maintained at a predetermined film forming vacuum. Further, the substrate 9 is controlled to a predetermined film forming temperature by the heater 31. Next, a high-frequency voltage pulse-modulated is applied to this gas by the power supply 7 to turn the gas into plasma, and form a film on the substrate 9. Similarly, the next source gas source is prepared, and the next film is formed using the gas. Thus, a stack of the silicon semiconductor film and the gate insulating film is formed.
【0011】前記最初の成膜中、原料ガスには、パルス
変調された高周波電力が印加されるので、基板から離れ
た位置での気相反応だけでなく基板表面及び(又は)そ
れに近い位置での表面反応もあり、従って基板への成膜
は基板表面から離れた位置からの反応種の降り注ぎによ
るだけでなく、表面反応によるゆるやかな反応種の供給
によってもなされ、全体として成膜表面はそれだけ平坦
となる。また、この膜の上に形成される次の膜も先の平
坦な膜表面への気相反応による反応種の供給と表面反応
によるきめ細かい反応種の供給により形成されるので、
最初の膜とその上に形成される次の膜の界面の平坦度は
きわめて良好となる。During the first film formation, a pulse-modulated high-frequency power is applied to the source gas, so that not only a gas phase reaction at a position distant from the substrate but also a substrate surface and / or a position close thereto. Therefore, the film formation on the substrate is not only performed by pouring the reactive species from a position away from the substrate surface, but also by the gradual supply of the reactive species by the surface reaction. It becomes flat. Also, the next film formed on this film is formed by the supply of reactive species by gas phase reaction to the previous flat film surface and the supply of fine reactive species by surface reaction,
The flatness of the interface between the first film and the next film formed thereon is extremely good.
【0012】よってシリコン半導体膜、ゲート絶縁膜の
いずれが先で、いずれがあとに形成される場合でも、両
者の界面平坦度はきわめて良好となり、両者はよく密着
する。従って、このような膜を用いた最終TFTトラン
ジスタでは、ソース・ドレイン間の電子移動度は従来に
比べ高いものとなる。以上説明した方法により、次の具
体的条件で100mm角のガラス基板(コーニング70
59)上にアモルファスシリコン(a−Si)半導体膜
とSiNxゲート絶縁膜の積層膜を形成したところ、後
に掲げる結果を得た。Therefore, regardless of which of the silicon semiconductor film and the gate insulating film is formed first and which is formed later, the interface flatness between the two is extremely good, and the two are in close contact with each other. Therefore, in the final TFT transistor using such a film, the electron mobility between the source and the drain becomes higher than that of the related art. According to the method described above, a 100 mm square glass substrate (Corning 70
59), a laminated film of an amorphous silicon (a-Si) semiconductor film and a SiNx gate insulating film was formed, and the following results were obtained.
【0013】 成膜真空度:100〜600mTorr(但し、ここでは500mTorr) 高周波電源:13.56MHz、1000W パルス変調:500Hz 電極3、4の面積:700mm×700mm ガラス基板温度:a−Si膜形成時 300℃ SiNx膜形成時 350℃ 成膜ガス:a−Si膜については SiH4 50ccm H2 150ccm SiNx膜については SiH4 50ccm NH3 150ccm N2 50ccm (結果)注:以下において( )内はパルス変調をかけない従来方法の結果 a−Si SiNx 成膜速度 200 300 (Å/min ) (150) (250) 表面粗度 10 10 (Å) (30) (40) 作成したTFTに 0.9 おける電子移動度 (0.3) (cm2 /V・s) 上記結果から分かるように、本発明方法によると、従来
法に比べ、成膜の表面粗度は大きく低下し、TFTにお
ける電子移動度は約3倍に増加している。Degree of vacuum for film formation: 100 to 600 mTorr (here, 500 mTorr) High frequency power supply: 13.56 MHz, 1000 W Pulse modulation: 500 Hz Area of electrodes 3 and 4: 700 mm × 700 mm Glass substrate temperature: when forming a-Si film When forming a SiNx film at 300 ° C. 350 ° C. Deposition gas: SiH 4 50 ccm H 2 150 ccm for a-Si film SiH 4 50 ccm NH 3 150 ccm N 2 50 ccm for SiNx film (Result) Note: In the following, pulse modulation A-Si SiNx film formation rate 200 300 (Å / min) (150) (250) Surface roughness 10 10 (Å) (30) (40) mobility (0.3) (cm 2 / V · s) as seen from the above results According to the present invention method, compared with the conventional method, the surface roughness of the film formation is greatly reduced, the electron mobility in the TFT is increased by about 3 times.
【0014】[0014]
【発明の効果】以上説明したように本発明によると、薄
膜トランジスタ(TFT)用のシリコン半導体膜及びこ
れに接するゲート絶縁膜の界面の平坦度を向上させ、そ
れによってTFTにおけるソース・ドレイン間の電子移
動度を大きくさせ得るプラズマCVD法による薄膜トラ
ンジスタ用の膜形成方法を提供することができる。As described above, according to the present invention, the flatness of the interface between the silicon semiconductor film for a thin film transistor (TFT) and the gate insulating film in contact with the silicon semiconductor film is improved. A film formation method for a thin film transistor by a plasma CVD method which can increase mobility can be provided.
【図面の簡単な説明】[Brief description of the drawings]
【図1】本発明方法の実施に使用するプラズマCVD装
置の一例の概略構成図である。FIG. 1 is a schematic configuration diagram of an example of a plasma CVD apparatus used for carrying out the method of the present invention.
【図2】図(A)はパルス変調をかけない従来高周波
の、図(B)はパルス変調をかけた本発明に係る高周波
の概略を示す図である。FIG. 2A is a diagram schematically showing a conventional high frequency without pulse modulation, and FIG. 2B is a diagram schematically showing a high frequency according to the present invention with pulse modulation.
1 真空チャンバ 2 真空ポンプ 21 電磁弁 3 接地電極 31 ヒータ 4 高周波電極 5 成膜用原料ガス源 61 電磁弁 7 高周波電源 71 高周波信号発生器 72 RFパワーアンプ 8 マッチングボックス DESCRIPTION OF SYMBOLS 1 Vacuum chamber 2 Vacuum pump 21 Electromagnetic valve 3 Ground electrode 31 Heater 4 High frequency electrode 5 Source gas source for film formation 61 Electromagnetic valve 7 High frequency power supply 71 High frequency signal generator 72 RF power amplifier 8 Matching box
Claims (2)
及びゲート絶縁膜をそれぞれプラズマCVD法により薄
膜トランジスタ用の基板上に形成し、前記それぞれの膜
形成にあたり該膜形成のための原料ガスのプラズマ化
を、基板への反応種の降り注ぎと基板表面及び(又は)
それに近い位置での反応種の供給とが交互に行われて膜
形成されるように、所定周波数の基本高周波電力にパル
ス変調をかけた状態の高周波電力の印加により行うこと
を特徴とする薄膜トランジスタ用の膜形成方法。1. A thin by each plasma CVD silicon semiconductor film and the gate insulating film of the thin film transistor
Forming on a substrate for a film transistor, in forming each of the above-mentioned films, forming a plasma of a source gas for the film formation by pouring a reactive species onto the substrate,
The supply of reactive species at a position close to the
To form a pulse at
A method for forming a film for a thin film transistor, wherein the method is performed by applying high-frequency power in a state in which a modulation is applied .
としてアモルファスシリコン膜を、ゲート絶縁膜としてAmorphous silicon film as gate insulating film
窒化シリコン膜を、それぞれプラズマCVD法により薄Each silicon nitride film is thinned by plasma CVD.
膜トランジスタ用の基板上に形成し、前記それぞれの膜The respective films formed on a substrate for a film transistor
形成にあたり該膜形成のための原料ガスのプラズマ化In the formation, plasma of source gas for the film formation
を、100mTorrから600mTorrの範囲内にWithin the range of 100 mTorr to 600 mTorr
おける成膜真空度下に、所定周波数の基本高周波電力にUnder a high vacuum power at a predetermined frequency
400Hzから1000Hzの範囲内でパルス変調をかPulse modulation within the range of 400 Hz to 1000 Hz
けた状態の高周波電力の印加により行うことを特徴とすIt is performed by applying high-frequency power in the
る薄膜トランジスタ用の膜形成方法。Film forming method for a thin film transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4019195A JP2581371B2 (en) | 1992-02-04 | 1992-02-04 | Film forming method for thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4019195A JP2581371B2 (en) | 1992-02-04 | 1992-02-04 | Film forming method for thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05218003A JPH05218003A (en) | 1993-08-27 |
| JP2581371B2 true JP2581371B2 (en) | 1997-02-12 |
Family
ID=11992569
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4019195A Expired - Fee Related JP2581371B2 (en) | 1992-02-04 | 1992-02-04 | Film forming method for thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2581371B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI512981B (en) | 2010-04-27 | 2015-12-11 | 半導體能源研究所股份有限公司 | Method for manufacturing microcrystalline semiconductor film and method for manufacturing semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2734021B2 (en) * | 1988-11-08 | 1998-03-30 | 日本電気株式会社 | Plasma vapor deposition method |
-
1992
- 1992-02-04 JP JP4019195A patent/JP2581371B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05218003A (en) | 1993-08-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US12486577B2 (en) | Pulsed plasma (DC/RF) deposition of high quality C films for patterning | |
| US5324360A (en) | Method for producing non-monocrystalline semiconductor device and apparatus therefor | |
| US6037017A (en) | Method for formation of multilayer film | |
| US5484746A (en) | Process for forming semiconductor thin film | |
| US10818507B2 (en) | Method of etching silicon nitride layers for the manufacture of microelectronic workpieces | |
| JP2002060945A (en) | TEOS oxide deposition using pulsed RF plasma | |
| JP3593363B2 (en) | Method for manufacturing active matrix type liquid crystal display device having semiconductor thin film | |
| JP2001189275A (en) | Semiconductor film forming method and thin film semiconductor device manufacturing method | |
| JP2581371B2 (en) | Film forming method for thin film transistor | |
| US20100062585A1 (en) | Method for forming silicon thin film | |
| US12021152B2 (en) | Process to reduce plasma induced damage | |
| JPH08279505A (en) | Forming method of insulating film | |
| JPH0793273B2 (en) | Film forming method for thin film transistor | |
| JPH0831753A (en) | VHF plasma processing method and apparatus | |
| JPS63233549A (en) | Thin film formation | |
| JP3257558B2 (en) | Hydrogen plasma processing method | |
| JP2798045B2 (en) | Method of controlling threshold voltage of field effect transistor | |
| JPH02166283A (en) | Formation of insulating film | |
| JP3380922B2 (en) | Method of forming silicon oxide film | |
| JP3473297B2 (en) | Method for forming silicon oxide film and method for manufacturing thin film transistor | |
| JPS5965479A (en) | Thin film transistor and manufacture thereof | |
| JP2795781B2 (en) | Method of forming impurity layer | |
| JP3244501B2 (en) | Hydrogen plasma processing method | |
| GB2179679A (en) | Forming a dielectric film and semiconductor device including said film | |
| JPH04243166A (en) | Thin film transistor and manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19961001 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081121 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081121 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091121 Year of fee payment: 13 |
|
| LAPS | Cancellation because of no payment of annual fees |