JP2589006B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inter-processor communication processing method for performing communication between processors, wherein an information processing apparatus comprising two processors for performing information processing by mutually transmitting and receiving commands is provided. Read a large amount of data /
The present invention relates to an inter-processor communication processing method that reduces the time required for data editing work that occurs when performing writing and improves processing efficiency between both processors. Now that the performance of individual processors has been improved, there is a demand for improved system performance by constructing further multiprocessor systems. It is desired to reduce communication time between processors, which is a drawback of this multiprocessor system.

[0002]

2. Description of the Related Art In a conventional multiprocessor system which performs communication via a shared memory by transmitting and receiving commands, when a large amount of data is read / written, a certain processor A issues a request command and processes the request command to a processor B. Then, the processor B performs the requested processing, and returns the result to the processor A as a response command. At this time, as shown in FIG. 4, the processor B writes a header and data to the shared memory in the interface, and the processor A receives the data. Processor A that has received the header and data as illustrated in the response command copies the header and data to the memory in processor A as shown on the left. Next, similarly, the processor A sequentially issues request commands, and stores the processor B in the shared memory in the interface according to the response command received from the processor B.
Each time, only the header and data written therein, and the header and data, and the data from the header and data, are sequentially extracted and stored successively in the memory of the processor A as shown in the figure. Then, the continuous data is stored in a hard disk device or the like.

[0003]

For this reason, it is necessary for the processor A of the processing requester to edit the data received from the processor B of the processing request destination each time.
During this editing operation, the next request command cannot be issued, and there is a problem that the processing cannot be performed quickly in a multiprocessor system.

According to the present invention, an editing information flag is provided in a request command, edited by a requesting processor, stored in a shared memory, and received by the requesting processor, thereby reducing editing work and reducing multi-processing. It is intended to improve the overall processing efficiency of the processor system.

[0005]

Means for solving the problem will be described with reference to FIG. In FIG. 1, a request command 11 is a command including a processing request content, an edit information flag 13, and the like. The processors A and B are processors constituting a multiprocessor system, and perform communication via a shared memory in the interface 2.

The interface 2 comprises a shared memory for the processors A and B to send and receive processing requests and results.

[0007]

According to the present invention, as shown in FIG. 1, the processor A issues a request command 11 to another processor B, and the processor B performs the requested processing. Edit information flag 1
When the edit information flag 13 is on, the header section 12 and the data section 14 are stored in the shared memory in the interface 2. When the edit information flag 13 is on, the header section is stored in the header section storage area of the shared memory in the interface 2. After storing and storing the data portion at the designated address, the result is notified to the requesting processor A by the response command 16 in order as necessary, and the processor A transmits the data from the shared memory in the interface 2. In a batch.

Accordingly, an editing information flag 13 is provided in the request command 11, edited by the requesting processor, stored in the shared memory, and received by the requesting processor, thereby reducing editing work and reducing multi-processing. It is possible to improve the overall processing efficiency of the processor system.

[0009]

Next, the structure and operation of an embodiment of the present invention will be sequentially described in detail with reference to FIGS. Fig. 1 (a)
Shows a configuration block diagram. In FIG. 1A, an information processing device 1 is a device for processing information, which is composed of a multiprocessor system in which a processor A and a processor B are connected using an interface 2. The information processing apparatus 1 is a system that is further connected to another information processing apparatus 3 via an interface 5 and another information processing apparatus 4 via an interface 6 and performs processing by a plurality of processors as a whole.

FIG. 1B shows an example of a request command. This request command is, for example, a command that the processor A in FIG. 1A issues to the processor B via the interface 2 to request processing. Here, access target: requested access target (for example, control storage, etc.) access address: address for accessing the access target Read / Write
e: Type of read or write for the access address to be accessed. Access length: Length of access (for example, byte length). Processing result: Result of request processing by request command (for example, normal, abnormal, etc.). Data pointer: Pointer (address) / edit information flag of the data part of the shared memory in the interface: A flag of the present invention, which specifies the data part of the processing result to the processor of the processing request in the shared memory in the interface 2. Flag read / write data to be stored in the address: data stored in the data section setting area of the shared memory in the interface 2 (data section 14) Next, according to the flowchart of FIG. The operation when the command and the response command are issued in the order from B) it will be described in detail with reference to.

In FIG. 2A, the processor A issues a request command 1 in S1. This means that processor A issues request command 1 of FIG. In S2, the processor B that has received the request command 1 of FIG. 3 issued in S1 performs the processing requested by the request command, and stores the result in the shared memory. This is the access address (00 00 10) of the access target (00 00 03, control storage) requested by the request command in FIG.
Since the read (02) is performed only for the access length (00 04 00 bytes) and the edit information flag 13 is off (00 00),
The read result is obtained from the address indicated by the pointer 00 2 00 to the shared memory in the interface 2 as shown in FIG.
They are stored sequentially as shown in the header and data.

At S3, the processor B issues a response command 1. This means that the processor B issues the response command 1 in FIG. In the response command of FIG. 3, as shown in the figure, a message indicating normal termination and a start address for writing a header portion and a data portion in the shared memory in the interface 2 are set. At S4, the processor A receives the response command 1 of FIG. 3 issued at S3. Thereby, it is received that the header part and the data part are stored as shown in the figure after the address indicated by the pointer to the shared memory in the interface 2 in (b) of FIG.

In step S5, the edit information flag 13 is set to ON, and a request command 2 is issued. This is followed by the processor A issuing the request command 2 in FIG. 3 (the editing information flag 13 is set to ON here). In S6, the processor B sends the request of FIG.
Performs the process requested by the command and stores the result in the shared memory. That is, the access target (00 00 03,
Control storage access address (00 4
Since the read (02) is performed for the access length (00 04 00 bytes) from (0 10) and the edit information flag 13 is ON (00 10), the read result is stored in the shared memory 00 21 00 in the interface 2. Is stored from the address indicated by, as shown in (b) data of FIG. 2, and the header part is stored in the header part setting area.

At S7, a response command 2 is issued. This is because after the processor B performs the processing of S6,
The response command 2 of FIG. 3 is issued. As described above, the processor A receives the request command 1 shown in FIG.
Is issued, and after the processor B performs the processing requested by the request command 1, the processor B issues a response command 1, and then the processor A issues the request command 1.
After issuing the command 2 (the edit information flag 13 is turned on) and the processor B performs the processing requested by the request command, the processor B issues the response command 2, thereby obtaining the interface shown in FIG. 2, a header, data, and data are stored in a continuous area in the shared memory, and the header is stored in the header section setting area.

Similarly, after the processor A performs the request command 3 and the request command 4 shown in FIG.
By issuing the command and the request command, as shown in FIG. 2B, the header section, the data section, and the like are stored in a continuous area. , Data part,... Can be quickly stored without being edited collectively in an external storage device or the like.

FIG. 2B shows a state where the header section and the data section are stored in the shared memory in the interface 2. This is because, as described above, the processor A requests the command 1 with the edit information flag 13 of FIG.
A request command 2, a request command 3, and a request command 4 in which the edit information flag 13 is ON are sequentially issued, and the processor B stores the request command 2, the request command 3, and the request command 4 in the shared memory in the interface 2 in response thereto. In this state, the processor A collectively stores the data (header portion, data portion,...) Edited by the processor B, for example, quickly in an external storage device, that is, converts the data on the right in FIG. It is possible to store the data without performing the editing of making multiple copies.

FIG. 3 shows an example of a command according to the present invention. In the configuration shown in FIG. 1, processor A sequentially issues request command 1, request command 2, request command 3, and request command 3, and processor B performs the processing requested by these request commands. Thereafter, the response command 1, the response command 2, the response command 3, and the response command 4 are issued.

[0018]

As described above, according to the present invention,
An editing information flag 13 is provided in the request command 11, is set, edited by the requesting processor, stored in the shared memory in the interface, and received by the requesting processor. Therefore, editing work can be reduced and the overall processing efficiency of the multiprocessor system can be improved. This makes it possible to efficiently transmit and receive commands between processors, which are indispensable for a command processing type multiprocessor system, by improving only the internal program, and to construct a multiprocessor system with high processing efficiency. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of one embodiment of the present invention.

FIG. 2 is a diagram illustrating the operation of the present invention.

FIG. 3 is a command example of the present invention.

FIG. 4 is an explanatory diagram of a conventional data storage method.

[Description of Reference Codes] 1, 3, 4: Information processing device 2, 5, 6: Interface having shared memory 11: Request command 12: Header 13: Edit information flag 14: Data 15: Response command

Claims (1)

(57) [Claims] 1. A command exchanged between processors .
Data part storage area for storing the data part and within the command
Sharing with a header part storage area for storing the header part of
Set the edit information flag in the memory and in the request command to process
Request for management, and based on the edit information flag,
Receives processing results stored in the data storage area of the existing memory
A first processor to execute, and an edit information flag from the first processor,
Processing result in response to a processing request from the first processor
Edit the data part and the header part and share each
Stored in the data area storage area and header area
And a second processor for storing the information.
Information processing device .