JPH0685154B2 - Intermediate buffer control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In the present invention, a main memory and a CPU have different capacities.
Regarding data transfer control when there is a set of buffer storage, the buffer storage capacity of the MCU is intended to increase the processing efficiency of the CPU by quickly transferring necessary data and controlling the transfer timing of unnecessary data for the time being. On the other hand, when the block size of the buffer storage on the CPU side is small, the move-in address register for accessing the main memory, the access counter for counting the data transfer amount during access, and the value of the access counter are set in advance. And a means for lowering the main memory access priority of the move-in address register when it reaches a predetermined value.

[Field of Industrial Application] The present invention has different capacities between a main memory and a CPU.
Regarding data transfer control when there is a pair of buffer storages, it is possible to improve CPU processing efficiency especially when the block size of the local buffer storage on the CPU side is smaller than the global buffer storage provided on the MCU side. Control system.

[Prior Art] FIG. 2 is a diagram for explaining data transfer between a main memory and a CPU. 51 is a CPU, 52 is a memory control unit (abbreviated as MCU in the figure), and 53 is main storage. A unit, 54 is a local buffer storage (abbreviated as LBS in the figure), and 55 is global buffer storage (GBS as abbreviated in the figure).

In the figure, when the CPU 51 reads data from the main storage unit (hereinafter also referred to as MSU) 53,
The data is once stored in the GBS 55 of the MCU 52, and at the same time, the data is sent to the CPU side and stored in the LBS 54. Then, if the CPU does not have data in LBS54, it looks for GBS55, and if not, it accesses MSU and stores these data in each buffer.

FIG. 3 is a block diagram showing the configuration of the memory control unit in FIG. 2, 52 and 55 are the same as those in FIG. 2, 56 is a CPU address port register, 57 is a GBS priority selection circuit, and 58. Is an MSU priority selection circuit, 59 is an interface with the CPU, and 60 is an interface with the main storage unit.

As shown in the figure, access to GBS55 or MSU is
The GBS priority selection circuit 57 or the MSU priority selection circuit 58 selects the one with the highest priority and processes it with priority.

[Problems to be Solved by the Invention] In the above-described access to the main storage unit, the access from the CPU to the main storage unit is reversed in the order of read (hereinafter also referred to as fetch) and write (hereinafter also referred to as store). Then, since the data becomes inconsistent, it is necessary to move to the processing for the next access after the processing for the access that occurred earlier is completed.

Therefore, when the block size of GBS is larger than that of LBS, it may be necessary to wait for access.

For example, when the LBS is 32 bytes / 1 block and the GBS is 64 bytes / 1 block, there is an access request in the order of block fetch → store, and during the block fetch process
Considering the case of GBS miss, in order to access the main storage unit and move the necessary data into the GBS, it is necessary to obtain priority for 64 bytes (hereinafter also referred to as priority).

In the case of this example, since data transfer between the main storage 53 and the MCU 52 shown by the letter A in FIG. 2 is performed in 8-byte units, the CPU address report register shown in FIG. 3 is incremented by 8, MSU priority selection circuit 58
To get priority. Therefore, the store access is kept waiting for "8 bytes x 8 times" (8τ).

Then, this data is transferred to LBS, which is 32 bytes.
Since it is / 1 block, there is a problem that the data for 4τ in the latter half is not immediately required, and the store data is kept meaningless for 4τ.

The present invention has been made in view of such conventional problems, and an object thereof is to provide a control unit that enables efficient memory access.

[Means for Solving Problems] According to the present invention, the above-mentioned object is achieved by the means described in the claims. That is, the present invention provides a global buffer storage that holds data from the main memory for each fixed block size between the main memory and the CPU, and the global buffer storage that holds data transferred from the global buffer storage. In a computer including a local buffer storage having a smaller block size, a move-in address register for accessing the main memory, an access counter for counting the amount of data transferred during access, and the value of the access counter are set in advance. And a means for lowering the main memory access priority of the move-in address register when the value reaches a predetermined value.

[Operation] In the above means, for example, LBS is 32 bytes / 1 block, GBS is 64 bytes / 1 block, and MSU → MCU
The case where the transfer method is in units of 8 bytes is explained. When an access request comes in the order of block fetch → store, the first 32 bytes from the MSU (8 bytes ×
After the transfer of 4) is completed, the subsequent store processing is performed before the transfer of the latter half 32 bytes, and the transfer of the latter half 32 bytes is controlled in the vacant time thereafter. As a result, the strobe is processed by waiting for 4τ.

In this way, by controlling the move-in address register, the access processing required only by GBS
By executing during the free time of access from, it is possible for subsequent CPU access to skip this and process.

[Embodiment] FIG. 1 is a block diagram of an embodiment of the present invention.
Shows the configuration of. In the figure, 1 is an MCU, 2 is a CPU
Address port register, 3 is GBS priority selection circuit,
Reference numeral 4 is an MSU priority selection circuit, 5 is GBS, 6 is an MS block fetch address register with an increment function, 7 is an access counter, 8 is an interface with the CPU, and 9 is an interface with the main storage unit.

In the figure, when the data required by the CPU is not in GBS (GBS
When you miss S), you need to move data from MSU to GBS. At this time, the CPU address port register 2 is connected to the MS block fetch address register 6, and the address value held in the CPU address port register 2 is changed to the MS block fetch address register 6
Then, the value of the access counter is set to "0" and access (move-in) to the MSU is started.

At this time, “8” is added to the MS block fetch address register 6 each time the MSU is accessed,
“1” is added to the access counter 7. And MS
The MSU is repeatedly accessed until the value of the block fetch address register 6 becomes "7".

When the value of the access counter 7 is "3" or less (within 32 bytes), the MSU priority selection circuit 4 operates so as to preferentially take the MSU priority of the MS block fetch address register 6.

On the other hand, when the value of the access counter is "4" or more (32 bytes or more), if there is a request to the CPU address port register, the MS block fetch address register will be given priority so that it will have the MSU priority. The priority of 6 is controlled to be lower than the request.

As a result, the remaining processing of the MS block fetch address register is performed in the idle time when there is no request from other ports.

As described above, according to the method of the present invention, when the CPU accesses the main storage unit, only the data corresponding to the block size of the LBS of the CPU is received first,
Data that can be processed immediately and stored in GBS in the latter half can be processed by using idle time after the processing of other access is completed. Because you can
The main storage can be used efficiently, and the throughput seen from the CPU is improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram for explaining data transfer between a main memory and a CPU, and FIG. 3 is a block diagram showing a configuration of a memory control unit. 1 ... MCU, 2 ... CPU address port register, 3 ...
GBS priority selection circuit, 4 ... MSU priority selection circuit, 5
...... GBS, 6 ... MS block fetch address register, 7 ... Access counter, 8 ... CPU interface, 9 ... Main storage unit interface

Claims (1)

[Claims] 1. A global buffer storage that holds data from the main memory for each fixed block size between the main memory and the CPU, and a global buffer storage that holds data transferred from the global buffer storage. In a computer equipped with a local buffer storage having a small block size, a move-in address register for accessing the main memory, an access counter for counting the data transfer amount during access, and a value for the access counter are predetermined. And a means for lowering the main memory access priority of the move-in address register.