JP2590867B2 - Manufacturing method of memory device - Google Patents
Manufacturing method of memory deviceInfo
- Publication number
- JP2590867B2 JP2590867B2 JP62073420A JP7342087A JP2590867B2 JP 2590867 B2 JP2590867 B2 JP 2590867B2 JP 62073420 A JP62073420 A JP 62073420A JP 7342087 A JP7342087 A JP 7342087A JP 2590867 B2 JP2590867 B2 JP 2590867B2
- Authority
- JP
- Japan
- Prior art keywords
- concave portion
- dram
- manufacturing
- memory device
- separation band
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Landscapes
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、複数のメモリセルを有し各々のメモリセル
が井戸状の容量素子を有しているメモリ装置の製造方法
に関するものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a memory device having a plurality of memory cells, each of which has a well-shaped capacitance element.
〔発明の概要〕 本発明は、上記の様なメモリ装置の製造方法におい
て、巾の広い凹部よりも巾の狭い凹部の方が深くエッチ
ングされる条件で、容量素子用の凹部と少なくとも容量
素子同士の間にあってこの容量素子よりも巾が狭い溝状
の分離帯用の凹部とを同時に形成することによって、集
積度の高いメモリ装置を効率的に製造することができる
様にしたものである。[Summary of the Invention] The present invention relates to a method for manufacturing a memory device as described above, wherein the concave portion for the capacitor and at least the capacitive element are connected under the condition that the narrow concave portion is etched deeper than the wide concave portion. By forming simultaneously a groove-shaped recess for a separation band having a width smaller than that of the capacitive element, a memory device with a high degree of integration can be manufactured efficiently.
DRAM等の様に複数のメモリセルを有し各々のメモリセ
ルが容量素子を有しているメモリ装置では、集積度を高
めるために、容量素子を三次元的に形成する様になって
きている。In a memory device such as a DRAM having a plurality of memory cells and each memory cell having a capacitance element, the capacitance element is being formed three-dimensionally in order to increase the degree of integration. .
第３図及び第４図は、本発明の一実施例で製造したDR
AMを示している。このDRAMを示している。この従来例で
は、１個のメモリセル11が１個のMOSキャパシタ12と１
個のMOSトランジスタ13とで構成されている。FIGS. 3 and 4 show the DR manufactured in one embodiment of the present invention.
AM is shown. This DRAM is shown. In this conventional example, one memory cell 11 is composed of one MOS capacitor 12 and 1
And the MOS transistors 13.
MOSキャパシタ12では、Si基板14に形成された四角柱
状の凹部15の内面に沿って形成されているSiO2膜16が誘
導体となっている。また、凹部15を取り囲む様に形成さ
れてMOSトランジスタ13の一方のソース・ドレイン領域1
7に連なる反転層18と、凹部15を埋める様に形成されて
いる第１層目の多結晶Si層21とが、MOSキャパシタ12の
電極となっている。従ってMOSキャパシタ12は、全体と
して井戸状を成している。In the MOS capacitor 12, the SiO 2 film 16 formed along the inner surface of the rectangular column-shaped concave portion 15 formed on the Si substrate 14 is a derivative. Also, one source / drain region 1 of the MOS transistor 13 is formed so as to surround the recess 15.
The inversion layer 18 connected to 7 and the first polycrystalline Si layer 21 formed so as to fill the recess 15 are electrodes of the MOS capacitor 12. Therefore, the MOS capacitor 12 has a well shape as a whole.
MOSトランジスタ13のゲート電極ともなっているワー
ド線22は、第２層目の多結晶Si層によって形成されてお
り、PSGから成る層間絶縁膜23に覆われている。また、A
1から成るデータ線24が、MOSトランジスタ13のもう一方
のソース・ドレイン領域25に接続されている。The word line 22 also serving as the gate electrode of the MOS transistor 13 is formed of a second-layer polycrystalline Si layer, and is covered with an interlayer insulating film 23 made of PSG. Also, A
A data line 24 made of 1 is connected to the other source / drain region 25 of the MOS transistor 13.
この様なDRAMでは、MOSキャパシタ12が井戸状を成し
ているので、MOSキャパシタが平板状である場合に比べ
て、集積度を高めることができる。In such a DRAM, since the MOS capacitor 12 has a well shape, the degree of integration can be increased as compared with the case where the MOS capacitor is a flat plate.
ところで、MOSキャパシタ12同士を上述の従来例の場
合よりも更に近接させれば、このDRAMの集積度を更に高
めることができる。By the way, if the MOS capacitors 12 are brought closer to each other than in the case of the above-described conventional example, the integration degree of the DRAM can be further increased.
しかし、MOSキャパシタ12同士の間にはLOCOS酸化膜26
しか介在しておらず、MOSキャパシタ12同士をこれ以上
に近接させれば、両者間にパンチスルーが発生する。However, between the MOS capacitors 12 LOCOS oxide film 26
However, if the MOS capacitors 12 are brought closer to each other, punch-through occurs between them.
従って上述の従来例の製造方法では、集積度を必ずし
も十分には高めることができない。Therefore, in the above-described conventional manufacturing method, the degree of integration cannot always be sufficiently increased.
本発明によるメモリ装置の製造方法は、巾の広い凹部
よりも巾の狭い凹部の方が深くエッチングされる条件
で、容量素子12用の凹部15と少なくとも前記容量素子12
同士の間にあってこの容量素子12よりも巾が狭い溝状の
分離帯33用の凹部34とを同時に形成する工程を具備して
いる。The method for manufacturing a memory device according to the present invention includes the step of forming the concave portion 15 for the capacitive element 12 and at least the capacitive element 12 under the condition that the narrow concave portion is etched deeper than the wide concave portion.
And a step of simultaneously forming a groove-shaped concave portion 34 for a separation band 33 which is located between them and has a width smaller than that of the capacitive element 12.
本発明によるメモリ装置の製造方法では、容量素子12
用の凹部15と少なくとも容量素子12同士の間にあってこ
の容量素子12よりも巾が狭い溝状の分離帯33用の凹部34
とを同時に形成しているが、これらの凹部15、34の形成
に際して、巾の広い凹部よりも巾の狭い凹部の方が深く
エッチングされる条件を採用している。In the method for manufacturing a memory device according to the present invention, the capacitance element 12
Recess 15 for the groove-shaped separation band 33 which is located between the recess 15 and at least the capacitor 12 and has a width smaller than that of the capacitor 12.
Are formed at the same time, but in forming these recesses 15 and 34, a condition is adopted in which a narrow recess is etched deeper than a wide recess.
このため、容量素子12用の凹部15よりも分離帯33用の
凹部34の方が深く形成されて、巾が狭いにも拘らず容量
素子12同士のパンチスルー耐圧が高い分離帯33を形成す
ることができる。For this reason, the concave portion 34 for the separation band 33 is formed deeper than the concave portion 15 for the capacitor element 12, and the separation band 33 having a high punch-through withstand voltage between the capacitive elements 12 is formed despite its narrow width. be able to.
しかも、容量素子12用の凹部15と分離帯33用の凹部34
とを同時に形成しているので、これらの凹部15、34を別
個に形成する場合に比べて、工程数を少なくすると共に
容量素子12と分離帯33とを容易に位置合わせすることが
できる。Moreover, the concave portion 15 for the capacitive element 12 and the concave portion 34 for the separation band 33
Are formed at the same time, so that the number of steps can be reduced and the capacitive element 12 and the separation band 33 can be easily aligned as compared with the case where these concave portions 15 and 34 are separately formed.
〔実施例〕 以下、DRAMの製造に適用した本発明の一実施例を第１
図及び第２図を参照しながら説明する。[Embodiment] An embodiment of the present invention applied to the manufacture of a DRAM will be described below as a first embodiment.
This will be described with reference to FIGS.
本実施例で製造したDRAMは、P+形のSi基板31上のP-形
のSi層32にメモリセル11が形成されており、Si基板31に
まで達する溝状の分離帯33によってメモリセル11同士が
分離されていることを除いて、既述の一従来例で製造し
たDRAMと実質的に同様の構成を有している。In the DRAM manufactured in the present embodiment, the memory cell 11 is formed in a P − type Si layer 32 on a P + type Si substrate 31, and a memory cell 11 is formed by a groove-shaped separation band 33 reaching the Si substrate 31. Except for the fact that the DRAMs 11 are separated from each other, the DRAM has a configuration substantially similar to that of the DRAM manufactured in the above-described conventional example.
本実施例でDRAMを製造するためには、まず、Si層32上
にCVDによってSiO2膜を形成する。そして、MOSキャパシ
タ12用の凹部15と分離帯33とを形成すべき部分に開口を
有するレジスト層を、通常のフォトリソグラフィによっ
て上記のSiO2膜上に形成する。このとき、分離帯33用の
開口の巾は凹部15用の開口の巾に比べて十分に狭くして
おく。In order to manufacture a DRAM in this embodiment, first, an SiO 2 film is formed on the Si layer 32 by CVD. Then, a resist layer having an opening in a portion where the concave portion 15 for the MOS capacitor 12 and the separation band 33 are to be formed is formed on the SiO 2 film by ordinary photolithography. At this time, the width of the opening for the separation band 33 is sufficiently smaller than the width of the opening for the concave portion 15.
次に、上記のレジスト層をマスクとして上記のSiO2膜
に開口を形成した後、レジスト層を除去する。Next, an opening is formed in the SiO 2 film using the resist layer as a mask, and then the resist layer is removed.
次に、開口を形成されたSiO2膜をマスクとして、Si層
32およびSi基板31をエッチングする。このときのエッチ
ング条件はSiCl4/O2＝10/10SCCM、3Pa、200W程度であ
る。Next, using the SiO 2 film with the opening formed as a mask, the Si layer
32 and the Si substrate 31 are etched. The etching conditions at this time are about SiCl 4 / O 2 = 10/10 SCCM, 3 Pa, and 200 W.
すると、第１図に示す様に、MOSキャパシタ12用の凹
部15と分離帯33用の凹部34とが同時に形成されるが、凹
部34の方が深く形成され、凹部34のみをSi基板31にまで
到達させることができる。Then, as shown in FIG. 1, the concave portion 15 for the MOS capacitor 12 and the concave portion 34 for the separation band 33 are formed at the same time, but the concave portion 34 is formed deeper, and only the concave portion 34 is formed on the Si substrate 31. Can be reached.
これは、SiCl4とO2とがプラズマ中で反応してSiO2が
形成され、このSiO2の堆積とClラジカルによるエッチン
グとの競合反応のために、巾の広い凹部15ではSiO2が堆
積し易く、巾の狭い凹部34の方が深くエッチングされる
ためではないかと考えられる。なお、凹部15の深さと凹
部34の深さとの比は、エッチング条件を選択することに
よって、容易に変更することができる。This, SiO 2 is formed with SiCl 4 and O 2 react in the plasma, this of SiO 2 deposition and by Cl radicals to competing reactions between the etching, SiO 2 in width wide recess 15 is deposited This is probably because the narrow recesses 34 are etched more easily. The ratio between the depth of the recess 15 and the depth of the recess 34 can be easily changed by selecting the etching conditions.
次に、CVDや酸化等によってSiO2膜16を形成するが、
凹部34の巾が狭いために、この凹部34はSiO2膜16によっ
て埋められる。Next, the SiO 2 film 16 is formed by CVD, oxidation, or the like.
Since the width of the concave portion 34 is narrow, the concave portion 34 is filled with the SiO 2 film 16.
次に、Ｐ形のDOPOSのCVDによって第１層目の多結晶Si
層21を形成するが、この多結晶Si層21によって凹部15も
埋められる。そしてその後は、既述の一従来例と同様な
工程によって、このDRAMが製造される。Next, the first layer of polycrystalline Si was formed by P-type DOPOS CVD.
The layer 21 is formed, and the concave portion 15 is filled with the polycrystalline Si layer 21. Thereafter, the DRAM is manufactured by the same steps as those of the above-described conventional example.
この様な本実施例で製造したDRAMでは、井戸状のMOS
キャパシタ12よりも深い溝状の分離帯33によってメモリ
セル11同士が分離されているので、MOSキャパシタ12同
士のパンチスルーに対する耐圧が既述の従来例で製造し
たDRAMよりも高い。In the DRAM manufactured in this embodiment, a well-shaped MOS
Since the memory cells 11 are separated from each other by the groove-shaped separation band 33 deeper than the capacitor 12, the withstand voltage of the MOS capacitors 12 against punch-through is higher than that of the DRAM manufactured in the above-described conventional example.
従って、第１図及び第２図と第３図及び第４図との比
較からも明らかな様に、従来例における場合よりもメモ
リセル11同士を近接させることができて、集積度を高め
ることができる。Therefore, as is clear from the comparison between FIGS. 1 and 2 and FIGS. 3 and 4, the memory cells 11 can be closer to each other than in the conventional example, and the degree of integration can be increased. Can be.
なお、MOSキャパシタ12用の凹部15と分離帯33用の凹
部34との深さが互いに異なるために、別個のマスクを用
いる別個の工程でこれらの凹部15、34を形成することも
考えられる。Since the depths of the concave portion 15 for the MOS capacitor 12 and the concave portion 34 for the separation band 33 are different from each other, it is conceivable to form these concave portions 15 and 34 in separate steps using different masks.
しかしこの様にすると、工程数が増加するのみなら
ず、マスク同士の位置合せも容易でないので、DRAMを効
率的に製造することができない。However, in this case, not only the number of steps is increased, but also it is not easy to align the masks, so that the DRAM cannot be manufactured efficiently.
本発明によるメモリ装置の製造方法では、巾が狭いに
も拘らず容量素子同士のパンチスルー耐圧が高い分離帯
を形成することができ、しかも、工程数を少なくすると
共に容量素子と分離帯とを容易に位置合わせすることが
できるので、集積度の高いメモリ装置を効率的に製造す
ることができる。In the method of manufacturing a memory device according to the present invention, it is possible to form a separation band having a high punch-through withstand voltage between the capacitance elements despite its narrow width, and to reduce the number of steps and to separate the capacitance element and the separation band. Since the alignment can be easily performed, a highly integrated memory device can be efficiently manufactured.
【図面の簡単な説明】 第１図及び第２図は本発明の一実施例で製造したDRAMを
示しており、第１図は第２図のＩ−Ｉ線における側断面
図、第２図は平面図である。 第３図及び第４図は本発明の一従来例で製造したDRAMを
示しており、夫々第１図及び第２図に対応する側断面図
及び平面図である。 なお図面に用いた符号において、 11……メモリセル 12……MOSキャパシタ 33……分離帯 である。BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 show a DRAM manufactured according to an embodiment of the present invention. FIG. 1 is a side sectional view taken along line II of FIG. 2, and FIG. Is a plan view. FIGS. 3 and 4 show a DRAM manufactured according to a conventional example of the present invention, and are a side sectional view and a plan view corresponding to FIGS. 1 and 2, respectively. In the reference numerals used in the drawings, reference numerals 11... Memory cells 12... MOS capacitors 33.
Claims (1)
が井戸状の容量素子を有しているメモリ装置の製造方法
において、 巾の広い凹部よりも巾の狭い凹部の方が深くエッチング
される条件で、前記容量素子用の凹部と少なくとも前記
容量素子同士の間にあってこの容量素子よりも巾が狭い
溝状の分離帯用の凹部とを同時に形成する工程を具備す
ることを特徴とするメモリ装置の製造方法。In a method of manufacturing a memory device having a plurality of memory cells and each memory cell having a well-shaped capacitance element, a narrow recess is etched deeper than a wide recess. A step of simultaneously forming a concave portion for the capacitive element and a concave portion for a groove-shaped separator between the capacitive elements and having a width smaller than that of the capacitive element. Device manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62073420A JP2590867B2 (en) | 1987-03-27 | 1987-03-27 | Manufacturing method of memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62073420A JP2590867B2 (en) | 1987-03-27 | 1987-03-27 | Manufacturing method of memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63239971A JPS63239971A (en) | 1988-10-05 |
| JP2590867B2 true JP2590867B2 (en) | 1997-03-12 |
Family
ID=13517706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62073420A Expired - Fee Related JP2590867B2 (en) | 1987-03-27 | 1987-03-27 | Manufacturing method of memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2590867B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2597022B2 (en) * | 1990-02-23 | 1997-04-02 | シャープ株式会社 | Method of forming element isolation region |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58137245A (en) * | 1982-02-10 | 1983-08-15 | Hitachi Ltd | Semiconductor memory and its manufacture |
| JP2604705B2 (en) * | 1985-04-03 | 1997-04-30 | 松下電子工業株式会社 | Method of manufacturing MOS capacitor |
-
1987
- 1987-03-27 JP JP62073420A patent/JP2590867B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63239971A (en) | 1988-10-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |