JP2597022B2 - Method of forming element isolation region - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an element isolation region for electrically isolating elements constituting a semiconductor integrated circuit, and more particularly, to a method for element isolation formed on a semiconductor substrate. The present invention relates to a method for forming a so-called trench element isolation region in which a groove is filled with an insulating film.

<Conventional technology> For example, DRAM (Dynamic Random Access
Memory), for example, so far almost every three years
As the degree of integration has increased by a factor of two, the minimum linewidth of circuits has been reduced from almost 60% to 70% for each generation. As a result, in the current mass-produced 1Mb DRAM and 4Mb DRAM, the minimum line width of each is 1.2 μm and
0.8 μm. In addition, the minimum line width used in a 16 Mb DRAM that has not yet been mass-produced is 0.6 to 0.5 μm, and will be 0.4 to 0.3 μm in a 64 Mb DRAM to be developed in the future.

With such miniaturization of semiconductor elements, an element isolation region for isolating elements from each other has been gradually narrowed. Minimum separation width is 1.0-0.8μm for 4Mb DRAM, 16M
It will be 0.8-0.6 μm for DRAM b, and will be reduced to 0.5-0.4 μm for 64 Mb DRAM.

The formation of the element isolation region having a width of 0.6 μm or more was possible by a selective oxidation method (LOCOS method) or an improved selective oxidation method. In the selective oxidation method, a silicon nitride film covering a silicon substrate is patterned and opened, and the exposed silicon substrate surface is selectively oxidized to form a silicon oxide film as an insulating film.

However, when the element isolation width is 0.5 μm or less,
The selective oxidation method cannot be used for the following reasons. In other words, in the selective oxidation method, unless the oxide film thickness of the isolation region is extremely reduced, the oxidation of the silicon substrate proceeds to the region covered with the silicon nitride film, and the lateral direction of the silicon oxide film called bird's beak is increased. Elongation occurs,
This is because the isolation region expands beyond the mask size, and it is impossible to form a narrow element isolation region.

Therefore, a method called a trench isolation method has been proposed as an element isolation method instead of the selective oxidation method. In this method, a concave groove (trench) is dug in a silicon substrate using a resist pattern formed by lithography as an etching mask, and an insulator such as a silicon oxide film is buried in the trench.

FIG. 4 is a process chart of a conventional trench isolation method. 4th
The conventional trench isolation method will be described with reference to the drawings.

First, after forming a thin oxide film 44 on the surface of a silicon substrate 41, a polycrystalline silicon film 45 is deposited, and portions 42 and 43 serving as element isolation regions are etched by a reactive ion etching method to form a narrow trench 42. (FIG. 4 (a)).

Next, after cleaning the inside of the trenches 42 and 43 and oxidizing the surface to form a thin oxide film 46 and subsequently a thin silicon nitride film 47, the depth substantially corresponds to the depth of the trench to bury the inside of the trench. A silicon oxide film 48 having a thickness is deposited and formed. At this stage, a high gap 49 is formed around the wide element isolation region 43 (FIG. 4B).

Next, a dummy resist 50 is formed in the wide element isolation region 43. This is to prevent the silicon oxide film 48 existing in the wide element isolation region 43 from being removed when the silicon oxide film 48 existing in the active region for forming the transistor is removed. After the formation of the dummy resist 50, a polyimide resin 51 is applied to fill the gap between the dummy resist 50 and the gap 49 to flatten the surface (FIG. 4C).

Next, in order to remove the polyimide resin 50 and the oxide film on the active region, the entire surface is etched by a reactive etching method under the conditions of uniform etching of the oxide resin and the polyimide resin or the resin material of the resist. Etching is stopped when the polycrystalline silicon film 45 comes to the surface (FIG. 4D).

After the polycrystalline silicon film 45 is removed by etching, cleaning is performed, and the oxide film 44 is removed with hydrofluoric acid, and the process proceeds to the next transistor formation step (FIG. 4E).

As described above, since only the trench region becomes the isolation region by using the trench isolation method, the isolation width can be reduced to the limit of lithography. It is suitable.

<Problems to be Solved by the Invention> In the above-described conventional trench isolation method, the thickness of the oxide film 48 that must be deposited in the above-described process is as large as about 1 μm. It is necessary to use a low pressure CVD (chemical vapor deposition) method capable of depositing an oxide film with good coverage. However, this method has the disadvantage that the film deposition rate is low and the throughput is poor.

Even if the in-plane uniformity of the uniform etching conditions of the resin film and the oxide film is as good as ± 2%, if the combined etching of the resin film and the oxide film is about 2 μm, the fastest etching is possible. As a result, the oxide film is over-etched for 800. Therefore, if the etching rate of the polycrystalline silicon film 45 under the uniform etching condition cannot be sufficiently suppressed, the active region is etched,
Damage will result. Even if the etching is successfully stopped by the polycrystalline silicon film 45, a steep difference of about 800 ° occurs between the element isolation region and the active region in the wafer surface.

When the oxide film surface inside the trench is lower than the silicon surface of the active region, the gate electrode is wired so as to cover the corner portion of the active region, so that electric field concentration occurs at the edge of the active region,
There is also a problem that a leak current occurs in a sub-threshold region of the transistor.

Further, as shown in FIG. 4 (e), in the trench 42 having a large aspect ratio, a fine wedge-shaped groove 52 is generated at the center of the trench due to the hydrofluoric acid treatment. Usually, after the formation of the element isolation region, the formation of the gate insulating film of the MOS transistor and the wiring of the gate electrode are performed. However, if the above-mentioned fine groove 52 exists in the element separation region, the wiring is disconnected or the wiring is formed in the fine groove. There is also a problem that the material remains and the wiring is short-circuited.

Therefore, an object of the present invention is to provide a method for forming an element isolation region using a trench isolation method, which includes the deterioration of electric characteristics due to processing damage, the deterioration of transistor characteristics due to flatness of an isolation portion, and the short circuit between wirings. An object of the present invention is to provide a method which can solve a problem peculiar to the conventional trench isolation method and can form an element isolation region suitable for a semiconductor integrated circuit with high integration by a relatively simple process.

<Means for Solving the Problems> In order to achieve the above object, a method for forming an element isolation region according to the present invention includes forming a trench defining a narrow width element isolation region on a semiconductor substrate, and then forming the trench on the semiconductor substrate. Forming an oxide film and a silicon nitride film sequentially on the semiconductor substrate including the side wall surface and the bottom surface of the trench, and then forming a first polycrystalline silicon film on the semiconductor substrate including the trench, Etching is performed only on both side walls of the trench by etching.
After the polycrystalline silicon film is left, the remaining first polycrystalline silicon film is completely oxidized to form oxide films on both side walls of the trench, and a second polycrystalline silicon film is formed on the semiconductor substrate including the trench. A silicon film is formed, followed by anisotropic etching, leaving the second polycrystalline silicon film only between the oxide films on both side walls of the trench, and then forming the silicon nitride film in a region which becomes a wide element isolation region. Removing the film, and then simultaneously oxidizing at least a surface portion of the second polycrystalline silicon film remaining in the trench and selectively oxidizing a semiconductor substrate portion to be a wide element isolation region. I have.

<Operation> Since the method of the present invention does not include a step of depositing a thick oxide film and etching back this oxide film as in the related art,
There is no problem of damage to the active region due to over-etching or a difference between the active region and the element isolation region. Also, the first
Polycrystalline silicon film is equivalent to about 1/4 of the minimum trench width
The second polycrystalline silicon film may have a thickness of about 0.1 μm, and a thickness of about half the trench depth. In the etching process performed on such a thin polycrystalline silicon film, the second polycrystalline silicon film may have On the other hand, since etching conditions having a large selectivity can be used, there is very little risk of damaging the active region, and a large difference does not occur at the boundary between the active region and the trench. Deterioration of the sub-threshold characteristic of the transistor is prevented.

Further, since the deposited film thickness of the first and second polycrystalline silicon films is extremely thin as compared with the film thickness of the oxide film deposited by the conventional trench isolation method of 1 μm, the time required for film deposition is small. And throughput is improved.

Further, since the oxide film in the trench is not formed by deposition, a fine groove is not formed at the center of the trench, and a short circuit between wirings caused by such a groove is prevented.

Also, by using the selective oxidation method together, oxidation for forming a wide isolation region can be simultaneously performed in the oxidation step of the polycrystalline silicon film.

<Example> Hereinafter, the present invention will be described in detail with reference to an illustrated example.

Embodiment 1 FIG. 1 is a process chart showing a first embodiment of a method for forming an element isolation region according to the present invention. Hereinafter, description will be made with reference to FIG. The following steps (a), (b), (c), (d),
(E), (f), (g) and (h) are (a), (b), (c), (d), (e), (f),
(G) and (h) are supported.

(A) P-type silicon substrate 1 is oxidized to form a thin oxide film 2
Is formed on the substrate surface, a silicon nitride film 3 is deposited,
Further, an oxide film 4 is deposited by a CVD method. Next, a resist pattern (not shown) of the trench for the isolation region is formed by an i-line stepper (exposure device), and the laminated films 2, 3, and 4 are removed by a reactive ion etching method using the resist pattern as a mask. After removing the resist pattern, the silicon substrate 1 is processed by a reactive ion etching method using the pattern of the oxide film 4 as a mask, and has a width of 0.5 to 1.0 μm and a depth of 0.6 μm.
Is formed. In this step, the etching of the silicon substrate is performed using the oxide film 4 as a mask. However, the silicon substrate may be etched using the resist pattern as a mask without the oxide film 4.

(B) After the inside of the trench 5 is washed with acid, the oxide film 4 is removed by etching, and the inside of the trench is oxidized by a mixed gas of hydrochloric acid and oxygen. The thin oxide film formed by this oxidation treatment is removed by etching, and the inside of the trench is oxidized again to form a thin oxide film 6 again. Further, the silicon nitride film 7 is decompressed.
Deposit thinly by CVD method. This silicon nitride film 7 is for preventing oxidation of the inner wall of the trench in a later oxidation step.

(C) Next, a polycrystalline silicon film having a thickness of 0.1 μm is deposited by a low pressure CVD method, anisotropic etching is possible, and
The entire surface is etched by a reactive ion etching method having a large selectivity with respect to the silicon nitride film, and the trench 5 is etched.
The polycrystalline silicon film 8 is left only on the side wall portion of FIG. The thickness of the polycrystalline silicon film is best when the oxide film thickness when it is completely oxidized is approximately half the minimum width of the trench. Since silicon is oxidized to an oxide film having almost twice the thickness, the thickness of the polycrystalline silicon film is approximately 1/1 / the minimum width of the trench.
And 4.

(D) Next, the polycrystalline silicon film 8 is wet-oxidized at 1050 ° C., thereby forming oxide films 9 and 9 on the inner wall of the trench.
To form At this time, in the case of a trench having a small groove width, a fine groove 10 remains between the oxide films 9 and 9 in the case of a trench having a large groove width. Since the surface of the silicon substrate 1 is protected by the silicon nitride films 3 and 7, it is not oxidized in this step.

(E) In order to fill the trench 10 remaining in the central portion of the trench 5, a polycrystalline silicon film is again deposited to a thickness of 0.3 μm, and the entire surface is etched back in the same manner as in the step (c). The crystalline silicon 11 is embedded. In this step, the thickness of the polycrystalline silicon film to be deposited is desirably larger than the thickness corresponding to half the width of the groove 10 in the widest trench.

(F) In order to oxidize the polycrystalline silicon film in the trench 5 and to form a wide element isolation region by the selective oxidation method in the same step, the silicon nitride film 3 in the region 12 to be selectively oxidized is etched.

(G) Thereafter, wet oxidation is performed at an oxidation temperature of 1050 ° C. or more to grow an oxide film 13 on the surface of the polycrystalline silicon 11 in the trench 10 and form a wide isolation region 14 by the oxide film.

As described above, according to the present embodiment, the formation of the wide isolation region by the selective oxidation method can be performed together with the oxidation of the polycrystalline silicon film by being incorporated in the steps (f) and (g). Separation regions of various widths can be formed efficiently.

(H) Finally, the silicon nitride film 3 is removed, and the thin oxide film 2 is further removed to complete the element isolation region.

When the above-described step of forming the element isolation region is completed, an element such as a MOS transistor is formed on the surface of the silicon substrate 1 according to a known method.

According to this example, an element isolation region having an extremely fine width of 0.5 μm was obtained. Then, an N-type MOS transistor (not shown) having a channel length of 0.5 μm electrically separated by the element isolation region having this extremely fine width was formed. As a result of measuring this transistor, no increase in junction leakage current was observed as compared with a transistor separated by a wide isolation region formed by a conventional selective oxidation method. Also, despite the separation width of 0.5 μm, the parasitic M
The leakage current between the devices due to the OS transistor was suppressed to a level below the conventional level. Further, the transistor having a channel width of 0.5 μm, which cannot be formed by the selective oxidation method, has good operating characteristics.

Embodiment 2 FIG. 2 shows a process diagram of a second embodiment of the present invention. 2 (a), (b), (c), (d), (e), (f),
1 (a), (b), (c) and (c) of FIG. 1 except for the following points.
Since they correspond to the steps (d), (e), (f), (g), and (h), detailed description is omitted.

That is, the present embodiment is directed to a polycrystalline silicon pad LOCOS (LOCOS) which is one of the improved selective oxidation methods as a selective oxidation method.
The first embodiment differs from the first embodiment in that the method is used.
In connection with the use of the polycrystalline silicon pad LOCOS method, a polycrystalline silicon film 21 for a pad is formed between the thin oxide film 2 and the thin nitride film 3 in the step (a).

In this embodiment, the same effects as those of the first embodiment were obtained.

Embodiment 3 FIG. 3 shows the steps of the third embodiment. The respective steps (a), (b), (c), (d),
(E), (f), (g), and (h) are (a), (b), (c), (d), (e), (f),
(G) and (h) are supported. Also in this embodiment,
As in the second embodiment, a polycrystalline silicon pad LOCOS method, which is one of the improved selective oxidation methods, is used as the selective oxidation method. However, this embodiment is different from the first and second embodiments in that the second polycrystalline silicon oxidation step and the oxidation step for a wide isolation region oxidized by the selective oxidation method are performed separately. .

(A) First, a P-type silicon substrate 1 is oxidized to form a thin oxide film 2, a silicon nitride film 3 is deposited, and an oxide film 4 is further deposited by a CVD method. Next, a resist pattern (not shown) of a trench for an element isolation region is formed by an i-line stepper, and the laminated film is used as a mask.
2,3,4 are removed by reactive ion etching. After removing the resist pattern, the silicon substrate 1 is processed by a reactive ion etching method using the pattern of the oxide film 4 as a mask to form a trench 5 having a width of 0.5 to 1.0 μm and a depth of 0.6 μm.
To form In this step, the silicon substrate is etched using the oxide film 4 as a mask. However, the silicon substrate may be etched without using the oxide film 4 using a resist pattern as a mask.

(B) After the inside of the trench 5 is cleaned with an acid, the first and second
Unlike the embodiment, a thin oxide film is formed by oxidizing the inside of the trench with a mixed gas of hydrochloric acid and oxygen while the oxide film 4 is left. After the thin oxide film formed by this oxidation treatment is removed by etching, the inside of the trench is oxidized again to form a thin oxide film 6. Further, a silicon nitride film 7 is deposited by a low pressure CVD method. This silicon nitride film 7 is for preventing oxidation of the inner wall of the trench in a later oxidation step.

(C) Next, a polycrystalline silicon film having a thickness of 0.1 μm is deposited by a low pressure CVD method, anisotropic etching is possible, and
The whole surface is etched back by a reactive ion etching method having a large selectivity with respect to the silicon nitride film, and the polycrystalline silicon film 8 is left only on the side wall of the trench 5. As already mentioned, the thickness of the polycrystalline silicon film is best when the oxide film thickness when it is completely oxidized is almost half the minimum width of the trench. Since silicon is oxidized into an oxide film having a film thickness almost doubled, the thickness of the polycrystalline silicon film is set to be approximately 1/4 of the minimum width of the trench.

(D) Next, the polycrystalline silicon film 8 is wet-oxidized at 1050 ° C. to form oxide films 9 and 9 on the inner wall of the trench. At this time, in the case of a trench having a small groove width, a fine groove 10 remains, and in the case of a trench having a large groove width, a relatively wide groove 10 remains. Since the surface of the silicon substrate 1 is protected by the silicon nitride films 3 and 7, it is not oxidized in this step.

(E) In order to fill the trench 10 remaining in the center of the trench 5, a polycrystalline silicon film is again deposited to a thickness of 0.3 μm, and the entire surface is etched back in the same manner as in the step (c).
Polycrystalline silicon 11 is embedded in groove 10. In this step, the thickness of the polycrystalline silicon film to be deposited is desirably larger than the thickness corresponding to half the width of the trench 10 that can be formed as the widest trench.

(F) Next, the surface of the polycrystalline silicon 11 in the trench is
After the oxide film 25 is formed by wet oxidation at 1050 ° C., the silicon nitride film 7, the oxide film 4, the silicon nitride film 3 and the oxide film 2 are sequentially removed by wet etching. Then, in order to form a wide isolation region by the polycrystalline silicon pad LOCOS method, the pad oxide film 26 and the polycrystalline silicon film for the pad are formed.
27 and silicon nitride film 28 are formed and selectively oxidized
The silicon nitride film 29 is removed by etching by a reactive ion etching method.

(G) Thereafter, wet oxidation is performed at an oxidation temperature of 1050 ° C. or more to form a wide isolation region 14 of an oxide film. As described above, in the present embodiment, unlike the first and second embodiments, the oxidation of the polycrystalline silicon film in the trench and the oxidation for forming a wide isolation region are performed separately.

If there is a trench isolation region in a wide isolation region, the polycrystalline silicon film 27 is oxidized,
Oxidation of the polycrystalline silicon 11 in the trench will proceed.

(H) Finally, the silicon nitride film 28 and the polycrystalline silicon film 27 are removed, and further, the thin oxide film 26 is removed to complete the element isolation region.

When the above-described step of forming the element isolation region is completed, elements such as MOS transistors are formed on the surface of the silicon substrate 1 according to a usual method.

In this embodiment, the same effects as those of the first embodiment were obtained.

<Effects of the Invention> As is clear from the above, according to the present invention, since a step unique to the conventional trench element isolation method of depositing a thick oxide film and etching it back is not included, the activity due to over-etching is reduced. There is no problem of damage to the region or a difference at the boundary between the active region and the trench isolation region. Therefore, it is possible to prevent deterioration of electrical characteristics due to processing damage in the active region and deterioration of element characteristics due to poor flatness.

Further, since the deposited film thickness of the first and second polycrystalline silicon films is extremely thin as compared with the film thickness of the oxide film deposited by the conventional trench isolation method of 1 μm, the time required for film deposition is short. , The throughput is improved.

Further, according to the present invention, the trench is filled with polycrystalline silicon, and the oxide film is formed in the trench by oxidizing the polycrystalline silicon. There is no problem of a fine groove generated in the portion. Therefore, a short circuit between wirings caused by such a fine groove can be prevented.

Therefore, when an integrated circuit is constructed using the method according to the present invention, good isolation of the semiconductor element can be achieved in an extremely fine area, thereby contributing to a large improvement in the degree of integration and increasing the level of the integrated circuit. Yield and reliability can be obtained.

Further, according to the present invention, in the step of oxidizing the polycrystalline silicon film, the oxidation of the wide isolation region by the selective oxidation method can be simultaneously performed, so that the element isolation regions having various widths can be efficiently formed. It also has the advantage of being able to.

[Brief description of the drawings]

FIG. 1 is a process diagram showing a first embodiment of the present invention, FIG. 2 is a process diagram showing a second embodiment of the present invention, and FIG.
FIG. 4 is a process chart showing an embodiment, and FIG. 4 is a view for explaining a conventional trench element isolation method. 1 ... P-type silicon substrate, 2, 26 ... thin oxide film, 3, 28 ... silicon nitride film, 4 ... oxide film, 5 ... trench, 6 ... thin oxide film, 7 ... thin silicon nitride Film, 8,11… First and second polycrystalline silicon films, 9,13,25… Oxide film, 10… Groove, 21,27… Thin polycrystalline silicon film.

Claims (1)

(57) [Claims] 1. A trench for defining a narrow isolation region is formed on a semiconductor substrate, and an oxide film and a silicon nitride film are sequentially formed on the semiconductor substrate including a side wall surface and a bottom surface of the trench. Next, a first polycrystalline silicon film is formed on the semiconductor substrate including the trench, and then the first polycrystalline silicon film is left only on both side walls of the trench by anisotropic etching. An oxide film is formed on both side walls of the trench by completely oxidizing the remaining first polysilicon film. Further, a second polysilicon film is formed on the semiconductor substrate including the trench. The second polycrystalline silicon film is left only between the oxide films on both side walls of the trench by the reactive etching. Next, the silicon nitride film in a region to be a wide element isolation region is removed. The second least and oxidation of the surface portion, the method of forming the device isolation region, characterized in that simultaneously and selectively oxidized semiconductor substrate portion serving as an element isolation region having a width of the polycrystalline silicon film remaining in the trench.