JP2594678B2 - System control unit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system control device, and more particularly to a system control device that receives a request from a processing device and stores the request in a buffer.

[Conventional technology]

Conventionally, this type of system control device initializes the buffer at that time when the connection with the processing device is released.

FIG. 3 is a block diagram showing the configuration of a conventional example of this type of system control device.

The system control device 3 of this conventional example indicates a request receiving means 11 for receiving a request from the processing device 5, a buffer 12 for storing the request, and indicates valid if the processing device 5 is connected, and invalid if not connected. Interface status signal output means 13 for outputting an interface status signal; buffer initialization means 14 for initializing the buffer 12, the read counter 15 and the write counter 16 when the interface status signal is changed from valid to invalid; , A read counter 15 indicating the position of the request to be read next from the buffer 12, a write counter 16 indicating a position to write the request next to the buffer 12, and a buffer status dump for reading the contents of the read counter 15 and the write counter 16. And means 17.

Since the number of requests stored in the buffer 12 is given by subtracting the value of the read counter 15 from the value of the write counter 16, the contents of the read counter 15 and the write counter 16 can be read by the buffer state dumping unit 17. Thus, the state of the buffer 12 can be known.

When the connection with the processing device 5 is released, the interface status signal output from the interface status signal output means 13 changes from valid to invalid, and the buffer initialization means 14 makes the buffer 12, the read counter 15, and the write The counter 16 is initialized. Therefore, the processing device 5
The state of the buffer 12 read by the buffer state dump unit 17 after the connection with the buffer is released is the state after the initialization.

FIG. 4 is a block diagram showing a configuration of another conventional system control device.

The system control device 4 of the conventional example includes a request receiving unit 21 for receiving a request from the processing device 5, a request status flag 22 set when the request is valid, and an address buffer 23 for holding the address of the request. Valid when the data buffer 24 holding the data of the request and the processing device 5 are connected,
Interface state signal output means 25 for outputting an interface state signal indicating invalid when not connected,
A buffer initialization means 26 for initializing the request status flag 22, the address buffer 23, and the data buffer 24 when the interface status signal is changed from valid to invalid; It is constituted by buffer state dump means 27 for reading the contents.

By reading the contents of the request state flag 22, the address buffer 23 and the data buffer 24 by the buffer state dump means 27, the state of the stored request can be known and the state of the buffer can be known.

When the connection with the processing device 5 is released, the interface status signal output from the interface status signal output means 25 changes from valid to invalid, and the buffer initialization means 26 sets the request status flag 22 and the address buffer 23 at this timing. And the data buffer 24 are initialized. Therefore, the state of the buffer read by the buffer state dump unit 27 after the connection with the processing device 5 is released is the state after the initialization.

[Problems to be solved by the invention]

In the above-described conventional system control device, the buffer is initialized when the connection with the processing device is released. Therefore, the state of the buffer at the time when the connection with the processing device is released is not saved. However, there is a disadvantage that it is not possible to know the processing status of the request at the time when the connection is released.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a system control device capable of knowing the processing status of a request at the time when the connection with the processing device is released even after the connection with the processing device is released.

[Means for solving the problem]

The system control device of the present invention is an interface status signal output unit that outputs an interface status signal indicating valid when connected to a processing device and indicating invalid when not connected to the processing device; and A system control device having a buffer for storing a received request, buffer initialization means for initializing the buffer, and buffer status dump means for acquiring the status of the buffer when the connection with the processing device is disconnected. An interface state signal change point detecting means for detecting a timing at which the interface state signal changes from invalid to valid; and the buffer initializing means for initializing the buffer at a timing detected by the interface state signal change point detecting means. Initialization means for instructing the initialization means Including the.

[Action]

The buffer is not initialized when the connection with the processing device is released, and the buffer is initialized when the processing device is connected again. Therefore, even after the connection of the processing device is released, the processing device is not initialized. Can know the state of the buffer at the time when the connection is released.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a system control device according to one embodiment of the present invention.

This system control device 1 includes an interface status signal change point detecting means 18 for detecting a timing at which an interface status signal is changed from invalid to valid, and a buffer at the aforementioned timing.
A buffer initialization instructing means 19 for instructing the buffer initializing means 14 to initialize the read counter 12, the read counter 15, and the write counter 16 is added. When the buffer initialization instruction means 19 issues the above instruction to the buffer initialization means 14, the buffer initialization means 14 outputs a signal having the same characteristics as those when the interface state signal changes from valid to invalid, and the buffer initialization means 14 It does not operate due to factors other than the instruction from the initialization instruction means 19.

 Next, the operation of this embodiment will be described.

In the initial state, no request is stored in the buffer 12, the contents of the read counter 15 and the write counter 16 are 0, and the processing device 5 is connected, indicating that the interface state signal is valid.

When a request is issued from the processing device 5, the request is accepted by the request accepting means 11 and written into the buffer 12, and the write counter 16 is incremented by one. When a request is read from the buffer 12, the read counter 15 is incremented by one. The number of requests stored in the buffer 12 is obtained by subtracting the value of the read counter 15 from the value of the write counter 16, and the contents of the read counter 15 and the write counter 16 are read by the buffer state dumping unit 17. Thus, the state of the buffer 12 can be known.

When the connection of the processing device 5 is released, the interface state signal changes from valid to invalid, but the interface state signal change point detecting means 18 does not detect this change. No output, so buffer 12, read counter 15, and write counter 16
Is not initialized. Therefore, the buffer state dumping unit 17 can know the state of the buffer 12 at the time when the connection of the treatment device 5 is released.

When the processing device 5 is connected again, the interface state signal changes from invalid to valid, the interface state signal change point detecting means 18 detects the timing of this change, and the buffer initialization instructing means 19 sets the buffer initializing at this timing. Since an initialization instruction is issued to the initialization means 14, the buffer initialization means 14 initializes the buffer 12, the read counter 15, and the write counter 16. This state is the same as the above-mentioned initial state, and the above-described operation is repeated thereafter. After the processing device 5 is reconnected, the state of the buffer at the time when the connection of the processing device 5 is released cannot be known.

FIG. 2 is a block diagram showing a configuration of a system control device according to another embodiment of the present invention.

This system control device 2 includes an interface status signal change point detecting means 28 for detecting a timing at which an interface status signal becomes effective from invalid, and a request status at the above-mentioned timing. Flag 22, address buffer 23, and data buffer
And a buffer initialization instructing means 29 for instructing the buffer initializing means 26 to initialize the memory 24. The buffer initialization means 26 does not operate due to factors other than the instruction from the buffer initialization instruction means 29.

 Next, the operation of the present embodiment will be described.

In the initial state, the request state flag 22 is reset, the contents of the address buffer 23 and the data buffer 24 are invalid, the treatment apparatus 5 is connected, and the interface state signal indicates valid.

When a request is issued from the processing device 5, the request receiving means 21 receives the request, sets the request status flag 22, and stores the address and data of the request in the address buffer 23 and the data buffer 24, respectively. When the request is read, the request status flag 22 is reset, and the contents of the address buffer 23 and the data buffer 24 become invalid. By reading the contents of the request state flag 22, address buffer 23 and data buffer 24 by the buffer state dumping means 27, the state of the buffer can be known.

When the connection of the processing device 5 is released, the interface state signal changes from valid to invalid. However, the interface state signal change point detecting means 28 does not detect this change, so that the buffer initialization instructing means 29 sets the buffer Therefore, the initialization of the request state flag 22, the address buffer 23, and the data buffer 24 is not performed. Therefore, the buffer state dump unit 27 can know the state of the buffer at the time when the connection of the processing device 5 is released.

When the processing device 5 is connected again, the interface state signal changes from invalid to valid, the interface state signal change point detecting means 28 detects the timing of this change, and the buffer initialization instructing means 29 transmits the buffer initializing signal at this timing. Since the initialization instruction is given to the initialization means 26, the buffer initialization means 26
And the data buffer 24 are initialized. This state is the same as the above-mentioned initial state, and the above-described operation is repeated thereafter. After the processing device 5 is reconnected, the state of the buffer at the time when the connection of the processing device 5 is released cannot be known.

〔The invention's effect〕

As described above, according to the present invention, the initialization of the buffer is performed when the connection of the processing device is released and then the processing device is connected again, so that the connection is performed until the processing device is connected again. The state of the buffer at the time when the processing is released is saved, and the processing status of the request at the time when the connection of the processing device is released can be known.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a system control device according to one embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a system control device according to another embodiment of the present invention, and FIG. FIG. 4 is a block diagram showing the configuration of another conventional example of the system control device. 1,2,3,4 ... system control device, 5 ... processing device, 11,21 ... request receiving means, 12 ... buffer, 13,25 ... interface status signal output means, 14,26 ... buffer Initializing means, 15: Read counter, 16: Write counter, 17, 27: Buffer state dumping means, 18, 28: Interface state signal change point detecting means, 19, 29 ... Buffer initialization instructing means, 22: Request valid flag, 23: Address buffer, 24: Data buffer.

Claims (1)

(57) [Claims] An interface status signal output means for outputting an interface status signal indicating valid when connected to a processing device and invalid when not connected to the processing device, and a request received from the processing device. And a buffer initialization means for initializing the buffer, and a buffer state dump means for acquiring the state of the buffer when the connection to the processing device is disconnected. An interface state signal change point detecting means for detecting a timing at which the interface state signal changes from invalid to valid; and the buffer initializing means for initializing the buffer at a timing detected by the interface state signal change point detecting means. And buffer initialization instructing means. The system controller according to symptoms.